CN1225020C - Process for manufacturing the memory unit for flash storage device - Google Patents
Process for manufacturing the memory unit for flash storage device Download PDFInfo
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- CN1225020C CN1225020C CN 02123103 CN02123103A CN1225020C CN 1225020 C CN1225020 C CN 1225020C CN 02123103 CN02123103 CN 02123103 CN 02123103 A CN02123103 A CN 02123103A CN 1225020 C CN1225020 C CN 1225020C
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Abstract
The present invention relates to a process for manufacturing a memory unit for a flash memory, which comprises the following steps that an active region is mainly formed on the surface of a semiconductor substrate, and a first insulation layer, a first conducting layer and a shielding layer are orderly formed in the active region; a first opening is formed after a part of the shielding layer is removed, an ion implantation process is carried out, and an oxidation process is carried out to form a floating grid insulation layer; after the shielding layer is removed, a part of the first conducting layer and a part of the first insulation layer are removed to form a floating grid; after a second insulation layer and a second conducting layer are formed, a part of the second conducting layer and a part of the second insulation layer are removed to form a control grid, and a second opening and a third opening are simultaneously formed; subsequently, a source region is formed on a surface layer of the semiconductor substrate at the bottom of the second opening, and an insulation side wall layer is formed on the side wall of the second opening and the side wall of the third opening; finally, a drain region is formed on the surface layer of the semiconductor substrate at the bottom of the third opening. The manufacturing process of the present invention can improve the acuity of the point of compound crystal silicon and increase the point discharge speed of the floating grid.
Description
Technical field
The present invention relates to a kind of manufacture method of memory, refer to a kind of manufacture method of flash memory mnemon especially
Background technology
Complementary metal oxide semiconductors (CMOS) (CMOS) memory can be divided into two big classes: random access memory (Random Acces Memory, RAM) with read-only memory (Read Only Memory, ROM).Random access memory is a volatile memory, turns off after the power supply, and the stored data of memory also disappear thereupon.But read-only memory but differs widely, and turning off power supply does not influence its stored data.In the middle of in the past several years, the occupation rate of market of read-only memory enlarges year by year, wherein attracts people's attention especially with flash memory again.Flash memory (Flash Memory) can write at the mode of single mnemon (memory cell) with electrically programmable (electricallyprogrammable) because of it simultaneously, mnemon block at majority is revised its content in the mode of electric erasable (electrically erasable), the flexibility of its utilization and convenience have surmounted EPROM (Electrically Programmable Read OnlyMemory, EPROM), Electrically Erasable Read Only Memory (Electrically ErasableProgrammable Read Only Memory, EEPROM) and programmable read only memory (Programmable Read Only Memory) on, and more prior be the low cost of manufacture of flash memory.Because these above advantages, nowadays flash memory is applied on the E-consumer product widely, for example: on digital camera, digital camera, mobile phone, laptop computer, walkman and the personal electric assistant products such as (PDA), and have more and more E-consumer products that the trend of using flash memory is arranged.These E-consumer products are owing to will satisfy the popular demand that is convenient for carrying of consumption, not only volume is done littler and littler, and additional function is also more and more, therefore need processing or data quantity stored also more and more huger, therefore be responsible for the flash memory of access data, its memory capacity also is increased to the 256M byte from four megabit units rapidly, and in the near future, the flash memory of 1G bytes store capacity also is about to listing.Traditional flash memory, its all processing procedure all must be dependent on the utilization of light shield, and the floating grid (floatinggate) that connects most critical is not always the case with the manufacturing of controlling grid (control gate).An explanation is done with regard to the processing procedure of the mnemon (memory cell) of known manufacturing separation gate (split gate) flash memory by following elder generation:
Shown in Figure 1A, at first P type silicon base 100 is implemented the thermal oxidation processing procedure, (LOCOS) forms the field insulating layer (not shown) as regional oxidizing process, and borrows this field insulating layer to isolate active area.Substrate in active area 100 surfaces then, the silica that forms the about 50-200 dust of thickness is as first insulating barrier 110.Secondly, on first insulating barrier 110,, and mix an amount of impurity to form first conductive layer 115 with the polysilicon layer of the about 100-2000 dust of chemical vapour deposition technique (CVD) deposition one layer thickness.Then, form first shielding layer (masking layer) 120 of the about 500-2000 dust of thickness, with as rigid cover act (hard mask) at first conductive layer, 115 surface deposition one deck silicon nitride layers.
Shown in Figure 1B, first shielding layer 120 that removes part exposes first conductive layer, 115 surfaces to form first opening 125.
Shown in Fig. 1 C, then carry out oxidation process, make first conductive layer, 115 surfaces of exposing form floating grid oxide layer 130.Wherein beak (bird ' s beak) 137 is formed at the tip portion of floating grid oxide layer 130 left and right two sides.
Shown in Fig. 1 D, remove after first shielding layer 120 with the isotropic etching step, with floating grid oxide layer 130 is rigid cover curtain, implement the anisotropic etching step, remove first conductive layer 115 and first insulating barrier 110 of part in regular turn, stay first conductive layer 115 and first insulating barrier 110 of floating grid oxide layer below 130, expose substrate 100 surfaces.The first residual conductive layer 115 is floating grid 136, and the first residual insulating barrier 110 is since then with 112 expressions of first grid insulating barrier.Wherein, being positioned at the polysilicon tip (polytip) 138 at the floating grid 136 side tips of beak 137 belows, is that point discharge is used when eliminating memory as flash memory.Then, implementing the formation of oxidizing process or chemical vapour deposition technique (CVD) is made of silica, thickness is about second insulating barrier 132 of 50-250 dust, covers substrate 100 and floating grid oxide layer 130 surfaces, and covers the sidewall of floating grid 136 and first grid insulating barrier 112.
Shown in Fig. 1 E, form second conductive layer 135 of the about 1000-2000 dust of thickness, for example be through doped polycrystalline silicon layer, cover second insulating barrier, 132 surfaces.
Shown in Fig. 1 F, implement little shadow and etch process, remove second conductive layer 135 partly and second insulating barrier 132 to form second opening 142 and the 3rd opening 144, the second residual conductive layer 135 is control grid 170, and 132 of second residual insulating barriers are with 155 expressions of second grid insulating barrier.
Shown in Fig. 1 G, to inject N type foreign ions such as phosphorus or arsenic and enter the semiconductor-based end 100, the top layer, the semiconductor-based ends 100 in second opening 142 forms source area 180.Then, the sidewall of surface, floating grid 136 and the first grid insulating barrier 112 of the sidewall of the surface of deposition layer of oxide layer (not shown) Coverage Control grid 170 and sidewall, second grid insulating barrier 155, floating grid oxide layer 130.Then implement an etch process and remove the aforementioned oxide layer of part, in the sidewall formation insulative sidewall layer 150 of second opening 142 and the 3rd opening 144.Secondly, inject N type foreign ions such as phosphorus or arsenic and enter the semiconductor-based end 100, the top layer, the semiconductor-based ends 100 in the 3rd opening 144 forms drain region 190, so far promptly finishes the manufacturing of the mnemon of known flash memory.
When the integrated level of flash memory increases rapidly, for reaching the requirement of high integration, the size of all memory cell devices all must be dwindled.Refer again to Fig. 1 D, when making floating grid 136 because of known technology, its floating grid insulating barrier 130 is to adopt oxidizing process to form, the beak (bird ' s beak) 137 that is formed at floating grid insulating barrier 130 2 sides is point but also long not only, when being rigid cover curtain with floating grid insulating barrier 130 when forming floating grid 136, polysilicon tip (poly tip) 138 promptly is formed at two sides of floating grid 136 and is positioned at beak 137 belows, but because of beak 137 points and long, cause polysilicon tip (poly tip) 138 sharp-pointed inadequately, therefore, the point discharge speed that flash memory is carried out when eliminating memory makes that the release of electric charge is incomplete slowly, has a strong impact on the bulk life time and the product performance of flash memory.
Summary of the invention
In view of this, the technical problem to be solved in the present invention provides a kind of manufacture method of mnemon of flash memory, improves the sharpness at polysilicon tip with brand-new processing procedure, improves the point discharge speed of floating grid 136.
In order to achieve the above object, the present invention proposes a kind of manufacture method of mnemon of flash memory, its manufacture method comprises the following steps: to provide the semiconductor-based end, be formed with the source region in this semiconductor-based basal surface, in active area this substrate surface forms first insulating barrier again, form first conductive layer in this first surface of insulating layer then, form a shielding layer in this first conductive layer surface more afterwards.Then, remove the part shielding layer and form first opening, first conductive layer surface of exposed portions serve, then, carry out ion implantation process, with ion to become with normal greater than 0 degree and less than incident angles first conductive layer surface that injects first open bottom and expose of 60 degree, carry out oxidation process again, make the first conductive layer surface oxidation that is positioned at first open bottom and is injected into ion, to form the floating grid oxide layer, wherein two sides of floating grid oxide layer form beak.Implement an etch process, to remove shielding layer, implement another etch process again, with the floating grid oxide layer is rigid cover curtain, remove first conductive layer and first insulating barrier of part in regular turn, expose substrate surface, only stay first conductive layer and first insulating barrier that are covered by the floating grid oxide layer, the first wherein residual conductive layer forms floating grid, the first residual insulating barrier forms the first grid insulating barrier, the tip that is positioned at floating grid two sides of beak below then forms the polysilicon tip, secondly, form second insulating barrier and cover substrate and the surface of floating grid oxide layer and the sidewall of floating grid and first grid insulating barrier, then, form second conductive layer and cover second surface of insulating layer, remove second conductive layer partly and second insulating barrier to form second opening and the 3rd opening, the second residual conductive layer forms the control grid, and the second residual insulating barrier forms the second grid insulating barrier.Then, this top layer, semiconductor-based end in this second opening forms source area, form again after the surface and sidewall that an insulating barrier covers the sidewall of the surface of this control grid and sidewall, this second grid insulating barrier and this floating gate polar region, remove this insulating barrier of part, each sidewall in first opening and second opening forms insulative sidewall layer, then, top layer, the semiconductor-based end of this in the 3rd opening forms after the drain region again, promptly finishes the manufacturing of flash memory mnemon.
Because of the present invention when the oxidation process, oxygen molecule can more go deep into the inside of first conductive layer, and make the oxidation process on the conductive layer top layer of winning more abundant, therefore the beak of formed floating grid oxide layer can the formed plumpness of more known processing procedure and shorter, therefore the more known processing procedure in the formed polysilicon of processing procedure of the present invention tip is more sharp-pointed, and its discharge effect is better.
For above-mentioned and other purposes of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphic elaborating.
Description of drawings
The key step of the manufacture method of the flash memory mnemon of Figure 1A to Fig. 1 G demonstration known technology;
Fig. 2 A to Fig. 2 G is the key step of manufacture method of the flash memory mnemon of one embodiment of the invention.
Embodiment
Initial step is shown in Fig. 2 A, and substrate 200 is the semiconductor material just like silicon, germanium, and generation type then has on crystalline substance of heap of stone or the insulating barrier silicon etc. is arranged, and for convenience of explanation, is example at this with a P type silicon base.At first be that P type silicon base 200 regional oxidizing process of enforcement or shallow channel isolation (STI) processing procedure are formed the field insulating layer (not shown), and borrow this field insulating layer to isolate the active area (not shown).Secondly substrate 200 surfaces in active area form first insulating barrier 210, and these first insulating barrier, 210 thickness are about the 50-200 dust, are made of the formed silica of oxidizing process.First conductive layer 215 that then forms the about 100-2000 dust of thickness is in first insulating barrier, 210 surfaces, this first conductive layer 215 is made of the polysilicon layer that chemical vapour deposition technique (CVD) deposits, for making first conductive layer 215 have conductivity, can utilize diffusion or ion implantation to inject arsenic ion or phosphonium ion, perhaps utilize the mode of mixing synchronously to form through doped polycrystalline silicon layer.Then, form shielding layers 220 in first conductive layer 215 surface, this shielding layer 220 can be that the silica by Low Pressure Chemical Vapor Deposition (LPCVD) or the about 500-2000 dust of thickness that thermal oxidation method forms is constituted.
Please refer to Fig. 2 B, carry out little shadow and etch process, the shielding layer 220 that removes part exposes first conductive layer, 215 surfaces to form first opening 225.Then, in ion implantor, carry out ion implantation process, with ion, for example be phosphonium ion, arsenic ion or belong to the argon ion of blunt gas ion or the ion of other blunt gas, inject first opening, 225 bottoms with specific incident angle, first conductive layer, 215 surfaces of exposing, this specific angle becomes the 0-60 degree approximately with normal, the energy that ion injects can be because of the kind of ion and weight different and variant, be about between 20KeV one 200KeV.Utilize ionic bombardment one conductive layer 215 top layers at a high speed with thorough destruction silicon lattice structure, the degree of depth that the big more then conductive layer 215 of ion wrecks is dark more.If first conductive layer 215 is to inject arsenic ion or phosphonium ion with diffusion or ion implantation to form when the doped polycrystalline silicon layer, then the ion that injected of this ion implantation step can be the argon ion of blunt gas ion; If first conductive layer 215 is to utilize the mode of mixing synchronously to form when doped polycrystalline silicon layer, then the ion that injected of this ion implantation step can be arsenic ion or phosphonium ion, argon ion that also can sufficient blunt gas ion.
Please refer to Fig. 2 C, then carry out oxidation process, make first conductive layer, 215 surface oxidations that are positioned at first opening, 225 bottoms and are injected into ion to form floating grid oxide layer 230.This oxidation process can be the wet oxidation processing procedure.In the ion implantation process of Fig. 2 B, because of the silicon crystal lattice on first conductive layer, 215 top layers of exposing because the bump of ion damages, when carrying out this oxidation process, oxygen molecule can more go deep into the inside of first conductive layer 215, and make the oxidation process on conductive layer 215 top layers of winning more abundant, therefore the beak 237 of formed floating grid oxide layer 230 can the formed plumpness of more known processing procedure and shorter.
Please refer to Fig. 2 D, implement first-class tropism's etching step to remove shielding layer 220, then, with floating grid oxide layer 230 is rigid cover curtain, implement the anisotropic etching step, remove first conductive layer 215 and first insulating barrier 210 of part in regular turn, expose substrate 200 surfaces, only stay first conductive layer 215 and first insulating barrier 210 that are covered by floating grid oxide layer 230, the first residual conductive layer 215 is floating grid 236, and the first residual insulating barrier 210 is since then with 212 expressions of first grid insulating barrier.Wherein, being positioned at the polysilicon tip (poly tip) 238 at the floating grid 236 side tips of beak 237 belows, is the usefulness of point discharge when eliminating memory as flash memory.Beak 237 survivors that more known processing procedure produces that scheme formed floating grid oxide layer 230 in the described oxidation process because of Fig. 2 C are plump and shorter, so the formed polysilicon of processing procedure tip 238 of adopting present embodiment, its tip is can more known processing procedure more sharp-pointed, so the formed tip of the more known processing procedure of its discharge effect is better.Then, implementing the formation of oxidizing process or chemical vapour deposition technique (CVD) is made of silica, thickness is about second insulating barrier 232 of 50-250 dust, to cover substrate 200 and the surface of floating grid oxide layer 230 and the sidewall of floating grid 236 and first grid insulating barrier 212.
Please refer to Fig. 2 E, second conductive layer 235 that forms the about 1000-2000 dust of thickness is to cover second insulating barrier, 232 surfaces, this second conductive layer 235 is made of the polysilicon layer that chemical vapour deposition technique (CVD) deposits, for making second conductive layer 235 have conductivity, can use diffusion or ion implantation to inject arsenic ion or phosphonium ion, perhaps utilize the mode of mixing synchronously to form through doped polycrystalline silicon layer.
Please refer to Fig. 2 F, implement little shadow and etch process, remove second conductive layer 235 partly and second insulating barrier 232 to form second opening 242 and the 3rd opening 244, the second residual conductive layer 23 5 is control grid 270, and 232 of second residual insulating barriers are with 255 expressions of second grid insulating barrier.
Please refer to Fig. 2 G, inject N type foreign ions such as phosphorus or arsenic and enter the semiconductor-based end 200, the top layer, the semiconductor-based ends 200 in second opening 242 forms source area 280.Then, deposit the surface, floating grid 236 of sidewall, the floating grid oxide layer 230 of the surface of a layer insulating (not shown) Coverage Control grid 270 and sidewall, second grid insulating barrier 255 and the sidewall of first grid insulating barrier 212, this insulating barrier can be made up of silica, silicon nitride or silicon oxynitride.Then implement an etch process and remove the aforementioned oxide layer of part, in the sidewall formation insulative sidewall layer 250 of second opening 242 and the 3rd opening 244.Secondly, inject N type foreign ions such as phosphorus or arsenic and enter the semiconductor-based end 200, the top layer, the semiconductor-based ends 200 in the 3rd opening 244 forms drain region 290, so far promptly finishes the manufacturing of the mnemon of flash memory of the present invention.
Though the present invention is disclosed in preferred embodiment, so it is not in order to restriction the present invention.Anyly have the knack of this operator, without departing from the spirit and scope of the present invention, when doing equivalent transformation and modification.Therefore protection scope of the present invention is when being as the criterion with claims.
Claims (14)
1, a kind of manufacture method of mnemon of flash memory is characterized in that comprising the following steps:
The semiconductor-based end, be provided;
Be formed with the source region in this semiconductor-based basal surface;
This substrate surface in active area forms first insulating barrier;
Form first conductive layer in this first surface of insulating layer;
Form a shielding layer in this first conductive layer surface;
Remove this shielding layer of part and form first opening, this of exposed portions serve first conductive layer surface;
Carry out ion implantation process, with ion to become with normal greater than 0 degree and less than incident angles this first conductive layer surfaces of injecting this first open bottom and exposing of 60 degree;
Carry out oxidation process, make this first conductive layer surface oxidation that is positioned at this first open bottom and is injected into ion, to form the floating grid oxide layer;
Implement an etch process, to remove this shielding layer;
Implement another etch process, with this floating grid oxide layer is rigid cover curtain, remove this first conductive layer and first insulating barrier of part in regular turn, expose this substrate surface, only stay this first conductive layer and first insulating barrier that are covered by this floating grid oxide layer, this wherein residual first conductive layer forms floating grid, and residual this first insulating barrier forms the first grid insulating barrier;
Form second insulating barrier and cover the surface of this substrate and floating grid oxide layer and the sidewall of floating grid and first grid insulating barrier;
Form second conductive layer and cover this second surface of insulating layer;
Remove this second conductive layer partly and second insulating barrier to form second opening and the 3rd opening, residual this second conductive layer forms the control grid, and residual this second insulating barrier forms the second grid insulating barrier;
This top layer, semiconductor-based end in this second opening forms source area;
Sidewall in this second opening and the 3rd opening forms insulative sidewall layer; And
Top layer, semiconductor-based end of in the 3rd opening this forms the drain region.
2, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this semiconductor-based end that forms is a silicon base.
3, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this first insulating barrier that forms is made of the formed silica of oxidizing process.
4, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this first thickness of insulating layer that forms is the 50-200 dust.
5, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this first conductive layer that forms is made of the polysilicon through mixing.
6, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this first conductive layer thickness that forms is the 100-2000 dust.
7, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this shielding layer that forms is made up of silica.
8, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this shielding layer thickness that forms is the 500-2000 dust.
9, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that the employed ion of described ion implantation process can be phosphonium ion, arsenic ion or the argon ion that belongs to blunt gas ion.
10, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that ion implantation energy is about between the 20KeV-200KeV in the described ion implantation process.
11, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this second insulating barrier that forms is made of the formed silica of chemical vapour deposition technique.
12, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this second thickness of insulating layer that forms is the 50-250 dust.
13, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this second conductive layer that forms is made of the polysilicon through mixing.
14, the manufacture method of the mnemon of flash memory as claimed in claim 1 is characterized in that this second conductive layer thickness that forms is the 1000-2000 dust.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 02123103 CN1225020C (en) | 2002-06-10 | 2002-06-10 | Process for manufacturing the memory unit for flash storage device |
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| CN 02123103 CN1225020C (en) | 2002-06-10 | 2002-06-10 | Process for manufacturing the memory unit for flash storage device |
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| CN1464547A CN1464547A (en) | 2003-12-31 |
| CN1225020C true CN1225020C (en) | 2005-10-26 |
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| CN 02123103 Expired - Lifetime CN1225020C (en) | 2002-06-10 | 2002-06-10 | Process for manufacturing the memory unit for flash storage device |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1309047C (en) * | 2004-03-26 | 2007-04-04 | 力晶半导体股份有限公司 | Method for producing non-volatile memory unit |
| US7176084B2 (en) * | 2005-06-09 | 2007-02-13 | Taiwan Semiconductor Manufacturing Co., Ltd. | Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory |
| US7329578B2 (en) * | 2005-06-20 | 2008-02-12 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of forming floating-gate tip for split-gate flash memory process |
| CN102044498B (en) * | 2009-10-20 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Formation method for split gate storage device |
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