CN1309047C - Method for producing non-volatile memory unit - Google Patents
Method for producing non-volatile memory unit Download PDFInfo
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- CN1309047C CN1309047C CNB2004100312300A CN200410031230A CN1309047C CN 1309047 C CN1309047 C CN 1309047C CN B2004100312300 A CNB2004100312300 A CN B2004100312300A CN 200410031230 A CN200410031230 A CN 200410031230A CN 1309047 C CN1309047 C CN 1309047C
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- 238000004519 manufacturing process Methods 0.000 title abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 45
- 238000000034 method Methods 0.000 claims abstract description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 34
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 29
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 29
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 24
- 210000000352 storage cell Anatomy 0.000 claims description 23
- 239000000463 material Substances 0.000 claims description 21
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 18
- 229920005591 polysilicon Polymers 0.000 claims description 16
- 238000005530 etching Methods 0.000 claims description 11
- 238000000059 patterning Methods 0.000 claims description 10
- 238000005516 engineering process Methods 0.000 claims description 9
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 238000005229 chemical vapour deposition Methods 0.000 claims description 5
- 239000000377 silicon dioxide Substances 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 4
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 4
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 claims description 4
- VEALVRVVWBQVSL-UHFFFAOYSA-N strontium titanate Chemical compound [Sr+2].[O-][Ti]([O-])=O VEALVRVVWBQVSL-UHFFFAOYSA-N 0.000 claims description 4
- 229910001936 tantalum oxide Inorganic materials 0.000 claims description 4
- 238000001312 dry etching Methods 0.000 claims description 2
- 238000003701 mechanical milling Methods 0.000 claims description 2
- 239000000126 substance Substances 0.000 claims description 2
- 238000003860 storage Methods 0.000 abstract description 17
- 239000004215 Carbon black (E152) Substances 0.000 abstract 1
- 230000002146 bilateral effect Effects 0.000 abstract 1
- 230000007774 longterm Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 description 32
- 239000010703 silicon Substances 0.000 description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 29
- 210000004027 cell Anatomy 0.000 description 23
- 230000001590 oxidative effect Effects 0.000 description 12
- 238000007667 floating Methods 0.000 description 6
- 238000002955 isolation Methods 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- SCCCLDWUZODEKG-UHFFFAOYSA-N germanide Chemical compound [GeH3-] SCCCLDWUZODEKG-UHFFFAOYSA-N 0.000 description 2
- 150000002500 ions Chemical class 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 150000003376 silicon Chemical class 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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Abstract
The present invention relates to a making method of a fixed-hydrocarbon storage unit. Firstly, a bottom dielectric layer and an electronic trapping layer are orderly formed on a substrate; then the electronic trapping layer is patterned to expose one groove of part of the dielectric layer; another layer of top dielectric layer if formed on the substrate to cover the electronic trapping layer and the exposed bottom dielectric layer; after that a layer of conducting layer is formed on the substrate to cover the top dielectric layer; then the conducting layer, the top dielectric layer, the electronic trapping layer and the bottom dielectric layer are patterned to form a layered structure of which the width is bigger than that of the groove; then a source zone/drain region is formed on the bilateral substrate at each side of the layered structure. The electronic trapping layer of a single storage unit is divided into two independent structures, so the storage unit can match with element miniaturization development to manufacture the storage unit suitable for long-term operation.
Description
Technical field
The present invention relates to a kind of manufacture method of memory cell, and be particularly related to the manufacture method of a kind of Nonvolatile storage unit (non-volatile memory cell).
Background technology
In various non-volatile storage products, actions such as depositing in, read, wipe with the information of can carrying out repeatedly, and the erasable of the advantage that the information that deposits in also can not disappear after outage removes and formula read-only memory able to programme (EEPROM), become extensively a kind of memory element of employing of PC and electronic equipment institute.Typical erasable removing and polysilicon (polysilicon) the making floating grid (floating gate) and control grid (control gate) of the read-only storage of formula able to programme to mix.When memory write (program), the electronics that injects floating grid can be uniformly distributed among the whole polysilicon floating gate layer.Yet the tunnel oxide (tunneling oxide) below the polysilicon floating gate layer just causes the leakage current of element when defectiveness exists easily, influences the reliability of element.
Therefore, in order to solve the problem of electro-erasable programmable formula read-only memory element leakage current, present method is to adopt an electronics trapping layer (charge trapping layer) to replace the polysilicon floating gate of known storage, and the material of this electronics trapping layer for example is a silicon nitride.This silicon nitride electronics trapping layer respectively has one deck silica up and down usually, and form a kind of silicon oxide/silicon nitride/silicon oxide (oxide-nitride-oxide that comprises, be called for short ONO) layer stacked structure (stacked structure) that is constituted, read-only storage with this stacked structure can be described as " silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon (silicon-oxide-nitride-oxide-silicon is called for short SONOS) " memory cell.
This kind silicon/oxidative silicon/the nitrogenize silicon/oxidative silicon/the silicon memory cell as shown in Figure 1.Please refer to Fig. 1, silica/silicon nitride/silicon oxide layer 102 is arranged on substrate 100, the stacked structure that it is made of an end silicon oxide layer 104, a silicon nitride layer 106 and a top silicon oxide layer 108.In addition, one polysilicon gate 112 is arranged on silicon oxide/silicon nitride/silicon oxide layer 102, that is as word line (word line), and in the substrate 100 of silicon oxide/silicon nitride/silicon oxide floor 102 both sides, having source/leakage (source/drain) district 118, it is as embedded type bit line (buried bit line).In addition, in the common gapped wall 116 of polysilicon gate 112 sidewalls, and there are light doping section (lightly dopingregion) 114 and source/drain regions 118 to be electrical connected in the substrate 100 below clearance wall 116.
And known this silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon memory cell can be passed through read forward (forward read) and back read (reverse read), with left side or the right side of electron storage in the electronics trapping layer.And the difference of (programmed cell) start voltage of the programming unit between forward and the back read (Vt) is the quantity (quantity) and scope (area) that comes from the electronics that is absorbed in.But, along with the increase of programming cycle, the start voltage of read forward and back read can move closer to, and makes the electronics that is absorbed in a certain side of electronics trapping layer originally extend to opposite side and the error on programming.And more shape is serious under miniaturization of components trend for the problems referred to above.
Therefore, known proposition a solution, please refer to No. 6538292 disclosed a kind of dibit unit (twin bit cell) flash memory (flash memory devices) of United States Patent (USP), the difference of itself and Fig. 1 maximum is that the electronics trapping layer of this flash memory is one deck polycrystalline SiGe (polysilicon germanium) layer, and utilize ion to flow into insulating regions of formation in this layer polycrystalline silicon germanide layer, become two discontinuous conductive regions to separate the polycrystalline silicon germanide layer, thereby form the dibit meta structure.But, form,, cause the conductive region of the conductive region of source side and drain side not of uniform size, thereby influence the performance of memory cell so problems of missing aim may take place because the insulating regions in this silicon nitride layer is a mode of utilizing ion to inject.
So, a kind of method that forms dibit unit nitrogenize storage unit is proposed again at present, please refer to United States Patent (USP) No. 6639271.Wherein, isolation between electronics trapping layer both sides stop (isolation barrier) be on substrate in regular turn deposited oxide layer, isolate and to stop dielectric layer, top dielectric layer and polysilicon layer and after each layer definition, only will part isolate and stop that dielectric layer etch falls, stop dielectric layer to form the isolation of contracting in.Then, in oxide layer, in the isolation of contracting stop on the stepped construction sidewall that dielectric layer, top dielectric layer and polysilicon layer constituted and form silicon nitride gap wall.This layer silicon nitride gap wall can with in the isolation of contracting stop the space filling of dielectric layer both sides, the zone that is absorbed in as electronics.Yet the formed silicon nitride gap wall of this method is contact substrate and polysilicon layer directly, so still problem can take place in the operation of memory element.
Summary of the invention
Therefore, the purpose of this invention is to provide a kind of preparing non-volatile storage cell, produce the memory cell that is suitable for long period of operation with the development of co-operating member miniaturization.
A further object of the present invention provides a kind of preparing non-volatile storage cell, can prevent the situation of the electronics trapping layer generation aligning mistake in the memory cell and is unfavorable for the operation of element.
According to above-mentioned and other purpose, the present invention proposes a kind of preparing non-volatile storage cell, is included in to form dielectric layer at the bottom of one deck on the substrate, forms one deck electronics trapping layer again on end dielectric layer.Then, patterning electronics trapping layer exposes a groove of dielectric layer at the bottom of the part, the end dielectric layer that forms one deck top dielectric layer overlay electronic trapping layer and expose again with formation on substrate.Afterwards, on substrate, form one deck conductive layer and cover the top dielectric layer, patterned conductive layer, top dielectric layer, electronics trapping layer and end dielectric layer again, to form a stacked structure, wherein the width of stacked structure is greater than the width of groove.Then, in the substrate of stacked structure both sides, form source/drain regions.
The present invention proposes a kind of preparing non-volatile storage cell in addition, be included in and form dielectric layer at the bottom of one deck, one deck electronics trapping layer, one deck first top dielectric layer and one deck mask layer on the substrate in regular turn, etching mask layer afterwards exposes one first groove of the part first top dielectric layer with formation.Then, forming a plurality of first clearance walls on first trenched side-wall, is etching mask with first clearance wall again, the first top dielectric layer and electronics trapping layer is carried out etching, to form one first groove.Then, remove first clearance wall, on substrate, form one deck second top dielectric layer again and cover first groove and second flute surfaces.Subsequently, in first groove and first groove, form one deck conductive layer, remove second groove and first groove conductive layer and the second top dielectric layer in addition again.Then, remove the mask layer that exposes.Then, as mask, remove the first top dielectric layer, electronics trapping layer and the end dielectric layer that expose,, in the substrate of stacked structure both sides, form source/drain regions again to form a stacked structure with conductive layer.
The present invention is because be divided into two independent structures with the electronics trapping layer of single memory cell, and the memory cell that is suitable for long period of operation is produced in development that therefore can the co-operating member miniaturization.
In addition, the present invention because by clearance wall when as the mask of separating the electronics trapping layer, so can prevent the situation of the electronics trapping layer generation aligning mistake in the memory cell, and then help the operation of element.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
The profile that goes out for known silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon memory cell shown in Figure 1;
Fig. 2 A to Fig. 2 E is the profile according to the manufacturing process of a kind of Nonvolatile storage unit of the first embodiment of the present invention;
Fig. 3 A to Fig. 3 F is the manufacturing process profile of a kind of Nonvolatile storage unit according to a second embodiment of the present invention.
Description of reference numerals
100,200,300: substrate
102,211,311: the silicon oxide/silicon nitride/silicon oxide layer
104,108: silicon oxide layer
106: silicon nitride layer
112: grid
114,216,316: light doping section
116,218,313a, 318: clearance wall
118,222,322: source/drain regions
202,202a, 210,210a, 302,302a, 310a, 310b, 310c, 310d, 310e: dielectric layer
206: patterning photoresist layer
208,308,315: groove
204,204a, 204b, 304,304a, 304b: electronics trapping layer
212,212a, 312,312a: conductive layer
220,320: source/drain electrode doping process
306,306a: mask layer
313: material layer
W1, W2: width
Embodiment
First embodiment
Fig. 2 A to Fig. 2 E is the profile of the manufacturing process of a kind of Nonvolatile storage unit (non-volatile memory cell) according to the first embodiment of the present invention.
Please refer to Fig. 2 A, prior to dielectric layer 202 at the bottom of formation one deck on the substrate 200, and this step for example is to utilize thermal oxidation technology to form silicon oxide layers in substrate 200 surfaces.Then, form one deck electronics trapping layer (charge trapping layer) 204 on end dielectric layer 202, wherein the material of electronics trapping layer 204 for example is selected from the group that comprises that silicon nitride layer, tantalum oxide layer, strontium titanate layer and hafnium oxide layer are formed.Wherein, the step that forms electronics trapping layer 204 on end dielectric layer 202 for example utilizes chemical vapor deposition method (chemical vapor deposition is called for short CVD) to form one deck silicon nitride layer on end dielectric layer 202.Then, on electronics trapping layer 204, form one deck patterning photoresist layer 206.
Then, please refer to Fig. 2 B, as etching mask, etching electronics trapping layer 204 with patterning electronics trapping layer 204, and forms a groove 208 exposing dielectric layer 202 at the bottom of the part with patterning photoresist layer 206 (asking for an interview Fig. 2 A).Certainly except the method for present embodiment, other technology that also can adopt other those of ordinary skills to be familiar with obtains the patterning electronics trapping layer 204a shown in this figure.Then, remove patterning photoresist layer 206.
Afterwards, please refer to Fig. 2 C, on substrate 200, form one deck top dielectric layer 210 overlay electronic trapping layer 204a and the end dielectric layer 202 that exposes.Subsequently, form one deck conductive layer 212 and cover top dielectric layer 210 on substrate 200, wherein the material of conductive layer 212 for example is a polysilicon.
Then, please refer to Fig. 2 D, patterned conductive layer 212, top dielectric layer 210, electronics trapping layer 204a and end dielectric layer 202 (asking for an interview Fig. 2 C), to form a stacked structure 214, the width W 1 of wherein stacked structure 214 is greater than the width W 2 of groove 208.And the step of definition conductive layer 212, top dielectric layer 210, electronics trapping layer 204a and end dielectric layer 202 preferably includes and makes groove 208 be right against the central configuration of stacked structure 214.Be silicon oxide/silicon nitride/silicon oxide layer 211 and end dielectric layer 202a, electronics trapping layer 204b that abovementioned steps forms and top dielectric layer 210a constitute, Nonvolatile storage unit with this silicon oxide/silicon nitride/silicon oxide layer 211 can be described as " silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon (silicon-oxide-nitride-oxide-silicon is called for short SONOS) memory cell ".
Afterwards, please refer to Fig. 2 E, can select to carry out one light dope technology (lightly dopingprocess) earlier, in the substrate 200 that exposes, to form a plurality of light doping sections (lightly dopingregion) 216.Optionally form a plurality of clearance walls 218 in stacked structure 214 sidewalls, its material is silicon nitride or other suitable material for example.Afterwards, can carry out one source/drain electrode doping process (source/drain doping process) 220, to form a plurality of source/drain regions (source/drain region) 222 in the substrate 200 outside the clearance wall 218 of stacked structure 214 sidewalls.
In the above-described embodiments, because the electronics trapping layer of single memory cell is divided into two independent structures, the memory cell that is suitable for long period of operation is produced in development that therefore can the co-operating member miniaturization.
Second embodiment
After the size of memory cell is more and more little, for avoiding producing the problem of aligning mistake (misalignment), the present invention proposes another embodiment again, asks for an interview Fig. 3 A to Fig. 3 F, the profile of the manufacturing process of its a kind of Nonvolatile storage unit according to a second embodiment of the present invention.
Please refer to Fig. 3 A, prior to forming dielectric layer 302 at the bottom of one deck, one deck electronics trapping layer 304, one deck first top dielectric layer 310a and one deck mask layer 306 on the substrate 300 in regular turn, wherein the material of electronics trapping layer 304 is as being selected from the group that comprises that silicon nitride layer, tantalum oxide layer, strontium titanate layer and hafnium oxide layer are formed, the material of the first top dielectric layer 310a is silica for example, and the material of mask layer 306 for example is a silicon nitride.Wherein, the step that forms end dielectric layer 302 on substrate 300 for example utilizes thermal oxidation technology to form silicon oxide layer in substrate 300 surfaces, and for example utilizes chemical vapor deposition method to form one deck silicon nitride layer on end dielectric layer 302 in the step that forms electronics trapping layer 304 on the end dielectric layer 302.
Afterwards, please refer to Fig. 3 B, etching mask layer 306 exposes one first groove 308 of the part first top dielectric layer 310a with formation.Then, form the first clearance wall (not shown) on first groove, 308 sidewalls, its technology for example is the material layer 313 that forms one deck such as polysilicon earlier on substrate 300.
Then, please refer to Fig. 3 C, this layer of material 313 of etch-back is to form the first clearance wall 313a on first groove, 308 sidewalls.Afterwards, as etching mask, the first top dielectric layer 310a and electronics trapping layer 304 (asking for an interview Fig. 3 B) are carried out etching with the first clearance wall 313a, to form one second groove 315, it is arranged in the first top dielectric layer 310b and electronics trapping layer 304a.At this moment, second groove 315 is the central authorities that are self-aligned to first groove 308, so do not have the situation of aligning mistake.
Then, please refer to Fig. 3 D, remove the first clearance wall 313a, form one deck second top dielectric layer 310c again and cover second groove 315 and first groove, 308 surfaces on substrate 300, wherein the material of the second top dielectric layer 310c for example is a silica.Then, on substrate 300, form one deck conductive layer 312 and fill up second groove 315 and first groove 308.
Subsequently, please refer to Fig. 3 E, the conductive layer 312 and the second top dielectric layer 310c beyond second groove 315 and first groove 308 are removed with the chemical mechanical milling tech (CMP process) or the mode of etch back process (etch-back process), to expose mask layer 306a.Afterwards, remove the mask layer 306a expose, again with conductive layer 312a as mask, remove the first top dielectric layer 310b, electronics trapping layer 304a and the end dielectric layer 302 that exposes in the dry etching mode, to form a stacked structure 314.Be silicon oxide/silicon nitride/silicon oxide layer 311 and end dielectric layer 302a, electronics trapping layer 304b, the first top dielectric layer 310d and the second top dielectric layer 310e that abovementioned steps forms constitute, the Nonvolatile storage unit with this silicon oxide/silicon nitride/silicon oxide layer 311 is exactly so-called " silicon/oxidative silicon/nitrogenize silicon/oxidative silicon/silicon memory cell ".
Afterwards, please refer to Fig. 3 F, can select to carry out light dope technology earlier, in the substrate 300 that exposes, to form a plurality of light doping sections 316.Optionally form a plurality of clearance walls 318 in stacked structure 314 sidewalls, its material for example is silicon nitride or other suitable material.Afterwards, can utilize a source/drain electrode doping process 320, form source/drain regions 322 in the substrate 300 outside the clearance wall 318 of stacked structure 314 sidewalls.
In sum, one of characteristics of the present invention are the electronics trapping layer of single memory cell is divided into two independent structures, and the memory cell that is suitable for long period of operation is produced in development that therefore can the co-operating member miniaturization.
In addition, it is by the mask of clearance wall when conduct separation electronics trapping layer that the present invention also has characteristics, so can prevent the situation of the electronics trapping layer generation aligning mistake in the memory cell, and be beneficial to the operation of element.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those of ordinary skill in the art; without departing from the spirit and scope of the present invention; should make various changes and retouching, so protection scope of the present invention should be with being as the criterion that appending claims was defined.
Claims (18)
1. preparing non-volatile storage cell comprises:
On a substrate, form an end dielectric layer;
On this end dielectric layer, form an electronics trapping layer;
This electronics trapping layer of patterning exposes the groove that part should end dielectric layer with formation;
On this substrate, form this end dielectric layer that a top dielectric layer covers this electronics trapping layer and exposes;
On this substrate, form a conductive layer and cover this top dielectric layer;
This conductive layer of patterning, this top dielectric layer, this electronics trapping layer and should end dielectric layer, to form a stacked structure, wherein the width of this stacked structure is greater than the width of this groove; And
In this substrate of these stacked structure both sides, form a source/drain regions.
2. preparing non-volatile storage cell as claimed in claim 1 wherein forms this source/drain regions and also comprises before in this substrate of these stacked structure both sides:
In this substrate that exposes, form a plurality of light doping sections; And
On the sidewall of this stacked structure, form a plurality of clearance walls.
3. preparing non-volatile storage cell as claimed in claim 1, wherein this conductive layer of patterning, this top dielectric layer, this electronics trapping layer and step that should end dielectric layer comprise and make this groove be right against the central configuration of this stacked structure.
4. preparing non-volatile storage cell as claimed in claim 1, the step that wherein forms this end dielectric layer on this substrate comprise utilizes a thermal oxidation technology to form silicon oxide layer in this substrate surface.
5. preparing non-volatile storage cell as claimed in claim 1 wherein comprises in the step that forms this electronics trapping layer on this end dielectric layer and utilizes a chemical vapor deposition method to form silicon nitride layer on this end dielectric layer.
6. preparing non-volatile storage cell as claimed in claim 1, wherein the material of this conductive layer comprises polysilicon.
7. preparing non-volatile storage cell as claimed in claim 1, wherein the material of this electronics trapping layer is selected from the group that comprises that silicon nitride layer, tantalum oxide layer, strontium titanate layer and hafnium oxide layer are formed.
8. preparing non-volatile storage cell comprises:
On a substrate, form an end dielectric layer, an electronics trapping layer, one first top dielectric layer and a mask layer in regular turn;
This mask layer of etching exposes partly one first groove of this first top dielectric layer with formation;
On this first trenched side-wall, form a plurality of first clearance walls;
With described first clearance wall is etching mask, and this first top dielectric layer and this electronics trapping layer are carried out etching, to form one second groove;
Remove described first clearance wall;
On this substrate, form one second top dielectric layer and cover this second groove and this first flute surfaces;
In this first groove and this second groove, form a conductive layer;
Remove this second groove and this first groove this conductive layer and this second top dielectric layer in addition, to expose this mask layer;
This mask layer that removal exposes;
As mask, remove this first top dielectric layer expose, this electronics trapping layer and should end dielectric layer, with this conductive layer to form a stacked structure; And
In this substrate of these stacked structure both sides, form a source/drain regions.
9. preparing non-volatile storage cell as claimed in claim 8 wherein forms this source/drain regions and also comprises before:
In this substrate that exposes, form a plurality of light doping sections; And
On the sidewall of this stacked structure, form a plurality of second clearance walls.
10. preparing non-volatile storage cell as claimed in claim 8, the step that wherein forms this end dielectric layer on this substrate comprise utilizes a thermal oxidation technology to form silicon oxide layer in this substrate surface.
11. preparing non-volatile storage cell as claimed in claim 8 wherein comprises in the step that forms this electronics trapping layer on this end dielectric layer and utilizes a chemical vapor deposition method to form silicon nitride layer on this end dielectric layer.
12. preparing non-volatile storage cell as claimed in claim 8, wherein the material of this mask layer comprises silicon nitride.
13. preparing non-volatile storage cell as claimed in claim 8, the material of wherein said first clearance wall comprises polysilicon.
14. preparing non-volatile storage cell as claimed in claim 8, wherein the material of this conductive layer comprises polysilicon.
15. preparing non-volatile storage cell as claimed in claim 8, wherein the material of this electronics trapping layer is selected from the group that comprises that silicon nitride layer, tantalum oxide layer, strontium titanate layer and hafnium oxide layer are formed.
16. preparing non-volatile storage cell as claimed in claim 8, wherein the material of this first top dielectric layer and this second top dielectric layer comprises silica.
17. preparing non-volatile storage cell as claimed in claim 8, the method for wherein removing this conductive layer beyond this second groove and this first groove and this second top dielectric layer comprise chemical mechanical milling tech and etch back process one of them.
18. preparing non-volatile storage cell as claimed in claim 8, the method for wherein removing this mask layer that exposes comprises dry etching.
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| CNB2004100312300A CN1309047C (en) | 2004-03-26 | 2004-03-26 | Method for producing non-volatile memory unit |
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| CNB2004100312300A CN1309047C (en) | 2004-03-26 | 2004-03-26 | Method for producing non-volatile memory unit |
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| CN1309047C true CN1309047C (en) | 2007-04-04 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538292B2 (en) * | 2001-03-29 | 2003-03-25 | Macronix International Co. Ltd. | Twin bit cell flash memory device |
| CN1420552A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Silicon nitride read-only memory structure and mfg. method thereof |
| US6639271B1 (en) * | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
| CN1464547A (en) * | 2002-06-10 | 2003-12-31 | 南亚科技股份有限公司 | Process for manufacturing the memory unit for flash storage device |
| US20040009642A1 (en) * | 2002-07-10 | 2004-01-15 | Samsung Electronics Co., Ltd. | Method of fabricating non-volatile memory device having a structure of silicon-oxide-nitride-oxide-silicon |
-
2004
- 2004-03-26 CN CNB2004100312300A patent/CN1309047C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6538292B2 (en) * | 2001-03-29 | 2003-03-25 | Macronix International Co. Ltd. | Twin bit cell flash memory device |
| CN1420552A (en) * | 2001-11-21 | 2003-05-28 | 旺宏电子股份有限公司 | Silicon nitride read-only memory structure and mfg. method thereof |
| US6639271B1 (en) * | 2001-12-20 | 2003-10-28 | Advanced Micro Devices, Inc. | Fully isolated dielectric memory cell structure for a dual bit nitride storage device and process for making same |
| CN1464547A (en) * | 2002-06-10 | 2003-12-31 | 南亚科技股份有限公司 | Process for manufacturing the memory unit for flash storage device |
| US20040009642A1 (en) * | 2002-07-10 | 2004-01-15 | Samsung Electronics Co., Ltd. | Method of fabricating non-volatile memory device having a structure of silicon-oxide-nitride-oxide-silicon |
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| Publication number | Publication date |
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| CN1674256A (en) | 2005-09-28 |
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