CN1855443A - Non-volatile memory and its production - Google Patents
Non-volatile memory and its production Download PDFInfo
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- CN1855443A CN1855443A CN200510067466.4A CN200510067466A CN1855443A CN 1855443 A CN1855443 A CN 1855443A CN 200510067466 A CN200510067466 A CN 200510067466A CN 1855443 A CN1855443 A CN 1855443A
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- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 238000000034 method Methods 0.000 claims abstract description 60
- 239000000758 substrate Substances 0.000 claims abstract description 36
- 125000006850 spacer group Chemical group 0.000 claims abstract description 7
- 230000008569 process Effects 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 27
- 239000004020 conductor Substances 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 16
- 229920002120 photoresistant polymer Polymers 0.000 claims description 11
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 10
- 239000012811 non-conductive material Substances 0.000 claims description 10
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 8
- 238000000059 patterning Methods 0.000 claims description 7
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 7
- 230000003647 oxidation Effects 0.000 claims description 4
- 238000007254 oxidation reaction Methods 0.000 claims description 4
- 238000005468 ion implantation Methods 0.000 claims description 3
- 238000003701 mechanical milling Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 2
- 239000004065 semiconductor Substances 0.000 description 22
- 230000015572 biosynthetic process Effects 0.000 description 13
- 238000005516 engineering process Methods 0.000 description 10
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 239000002184 metal Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical group [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 239000002784 hot electron Substances 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 238000009825 accumulation Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000012163 sequencing technique Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- Non-Volatile Memory (AREA)
Abstract
The process provided for fabricating a non-volatile random access memory comprises: providing a substrate; forming multi stack structures each sequentially comprising a bottom dielectric layer, a charge-trapped layer, a top dielectric layer, a control grid layer and a roof covering; forming multi spacers on the sidewall of said stack structures; forming a gate dielectric layer on the substrate; forming words line between two adjacent stack structures; removing roof cover layer in each stack structure; forming a source region and a drain region in a portion of substrate except the area of each said stack structures beside both side of word line.
Description
Technical field
The present invention relates to a kind of non-volatility memorizer and manufacture method thereof, particularly relate to a kind of non-volatility memorizer and manufacture method thereof of improving the element electric characteristics and improving component reliability.
Background technology
At present in the non-volatility memorizer commonly a kind of be called " flash memory " but program read-only memory (the Electrically Erasable Programmable Read Only Memory that can electricity erases, EEPROM), it has the actions such as depositing in, read, erase that can carry out repeatedly data, and the advantage that the data that deposit in also can not disappear after outage, thus become personal computer and electronic equipment a kind of memory component of extensively adopting.
Typical flash memory with the doped polycrystalline silicon of mixing as floating grid (Floating Gate) and control grid (Control Gate).When memory carried out write-in program (Program), the electronics that injects floating grid can be uniformly distributed among the whole doped polycrystalline silicon floating gate layer.Yet, when the tunnel oxide defectiveness of doped polycrystalline silicon floating gate layer below exists, just cause the leakage current of element easily, influence the reliability of element.
Therefore, in order to solve the problem of flash memory leakage current, change at present and adopt a kind of non-volatility memorizer with charge immersing layer substitute doping polysilicon floating gate, it is called " silicon-oxide-nitride--oxide-semiconductor (silicon-oxide-nitride-oxide-semiconductor, SONOS) " memory.Because silicon-oxide-nitride--oxide-semiconductor memory has monoxide-nitride-oxide (oxide-nitride-oxide, be called for short ONO) dielectric structure, wherein nitride layer uses as charge immersing layer (electrode trapping layer).The channel hot electron (channel hot electron is called for short CHE) of bottom oxide that generally can be by oxide-nitride thing-oxide dielectric structure is injected and is written into.On the other hand, the tunnel of wearing of the bottom oxide by oxide-nitride thing-oxide dielectric structure is strengthened hot hole (tunneling enhanced hot hole is called for short TEHH) and is injected and erased.So silicon-oxide-nitride--oxide-semiconductor memory can overcome the problem of leakage current.But, along with component size is constantly dwindled, the problem of charge migration error takes place in the charge immersing layer in above-mentioned silicon-oxide-nitride--oxide-semiconductor memory easily.
Therefore, occur a kind of electric charge recently and be absorbed in the oxide-nitride thing-oxide dielectric structure (as shown in Figure 1) that occurs in the grid both sides, efficiently solve this problem.
Please refer to Fig. 1, it illustrates the profile of existing a kind of non-volatility memorizer.The word line 120 of this silicon-oxide-nitride--oxide-semiconductor (SONOS) non-volatility memorizer is formed on the gate oxide 110 in the substrate 100; And control gate 170 is formed on the sidewall of word line 120, and its shape is the clearance wall shape.Then separate with top dielectric layer 160 formed oxide-nitride thing-oxide (ONO) structures between word line 120 and the control gate 170 and between control gate 170 and the substrate 100 with end dielectric layer 140, charge immersing layer 150; Source electrode 180 then is formed in control grid gap wall 170 substrate 100 outward of word line 120 both sides with drain electrode 190.
This kind element is when carrying out sequencing, because electric charge is to be absorbed in the charge immersing layer 150 of word line 120 both sides, therefore can avoid dwindling the charge migration problem that causes because of element.Yet, when electric charge is absorbed in the oxide-nitride thing of sidewalls of wordlines in silicon-oxide-nitride--oxide-semiconductor non-volatility memorizer-oxide structure, because electric charge herein is difficult for removing, the result of electric charge accumulation is with the producing component reliability problems.
On the other hand, because the control grid is the clearance wall shape, its surface is that an arc surface is not to be a plane, in the technology of follow-up formation contact hole, contact hole with control being electrically connected and being not easy between the grid gap wall and carry out.
In addition, when forming the control grid gap wall, regular meeting damages oxide-nitride thing-oxide (ONO) structure in etch back process, and is follow-up when forming metal silicide (silicide) on word line and control grid gap wall, causes short circuit easily.
Summary of the invention
Purpose of the present invention is providing a kind of non-volatility memorizer exactly, to promote the reliability of memory component.
A further object of the present invention provides a kind of manufacture method of non-volatility memorizer, to improve the electrical of memory component.
The present invention proposes a kind of manufacture method of non-volatility memorizer, and a substrate at first is provided, and forms a plurality of stack architectures in substrate, and each stack architecture from bottom to top is end dielectric layer, charge immersing layer, top dielectric layer, control grid layer and cap layer in regular turn.Then, on the sidewall of stack architecture, form a plurality of clearance walls.Then, in substrate, form gate dielectric layer.Afterwards, between adjacent two stack architectures, form word line.Come again, remove the cap layer in each stack architecture.Then, form source area and drain region in the substrate outside each stack architecture of each word line both sides.
Described according to a preferred embodiment of the present invention, the method for formation clearance wall in the manufacture method of above-mentioned non-volatility memorizer forms the spacer material layer earlier and covers stack architecture in substrate.Then, etch-back spacer material layer is to form clearance wall on the sidewall of stack architecture.
Described according to a preferred embodiment of the present invention, the method that forms gate dielectric layer in the manufacture method of above-mentioned non-volatility memorizer comprises thermal oxidation method.
Described according to a preferred embodiment of the present invention, between adjacent two stack architectures, form the method for word line in the manufacture method of above-mentioned non-volatility memorizer, at first in substrate, form conductor layer, to cover stack architecture and to fill up space between adjacent two stack architectures.Then, remove the segment conductor layer, to expose the cap layer in each stack architecture.Then, in substrate, form the photoresist layer of patterning, be covered on two conductor layers between the stack architecture, make the cap layer of part expose out at least.Afterwards, be that mask removes the cap layer in each stack architecture with patterning photoresist layer.Come again, remove the photoresist layer of patterning.
Described according to a preferred embodiment of the present invention, remove the segment conductor layer in the manufacture method of above-mentioned non-volatility memorizer to expose the method for the cap layer in each stack architecture, comprise with the cap layer in each stack architecture serving as to grind stop layer to carry out a chemical mechanical milling tech.
Described according to a preferred embodiment of the present invention, remove the segment conductor layer in the manufacture method of above-mentioned non-volatility memorizer to expose the method for the cap layer in each stack architecture, comprise with the cap layer in each stack architecture being that etch stop layer carries out an etch back process.
Described according to a preferred embodiment of the present invention, the method that removes the cap layer in each stack architecture in the manufacture method of above-mentioned non-volatility memorizer comprises wet etching.
Described according to a preferred embodiment of the present invention, the method that forms source area and drain region in the manufacture method of above-mentioned non-volatility memorizer comprises ion implantation.
The present invention proposes a kind of non-volatility memorizer, comprises a substrate, a plurality of stack architecture, a plurality of word line, a plurality of clearance wall, a gate dielectric layer, plurality of source regions and a plurality of drain region.Wherein, a plurality of stack architectures are disposed in the substrate, and each stack architecture comprises end dielectric layer, charge immersing layer, top dielectric layer and control grid.In each stack architecture, end dielectric layer is disposed in the substrate, charge immersing layer is disposed on the bottom oxide, the top dielectric layer is disposed on the charge immersing layer, and the control grid is disposed on the oxide layer of top.In addition, a plurality of word lines be disposed in the substrate and each word line between adjacent two stack architectures.A plurality of clearance walls are disposed between stack architecture and pairing each word line.Between gate dielectric layer configuration word line and the substrate.Plurality of source regions and a plurality of drain region are disposed at respectively in each stack architecture substrate outward of each word line both sides.
Described according to a preferred embodiment of the present invention, the control grid comprises having a flat upper surfaces in the above-mentioned non-volatility memorizer.
Because non-volatility memorizer of the present invention does not have silica-silicon-nitride and silicon oxide structure on sidewalls of wordlines, do not have in existing silicon-oxide-nitride--oxide-semiconductor non-volatile memory structure, electric charge is absorbed in the problem of the oxide-nitride thing-oxide structure of sidewalls of wordlines, therefore, can promote the reliability of memory component.
Moreover the control gate of non-volatility memorizer of the present invention has a flat upper surfaces, and in the technology of follow-up formation contact hole, the control grid can be easier to be electrically connected with contact hole.
On the other hand, manufacture method according to non-volatility memorizer of the present invention, the clearance wall that forms between the grid in word line and control can effectively insulate, and is difficult for the phenomenon that is short-circuited in the technology of follow-up formation metal silicide, can effectively improve electric characteristics.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 is the profile that illustrates existing a kind of non-volatility memorizer.
Fig. 2 A～Fig. 2 C is the manufacturing process profile that illustrates the non-volatility memorizer of one embodiment of the present invention.
Fig. 3 is the profile that illustrates the non-volatility memorizer of one embodiment of the present invention.
The simple symbol explanation
100,200,300: the semiconductor-based end
110,224,324: gate oxide
120,230,330: word line
140,214,314: end dielectric layer
150,216,316: charge immersing layer
160,218,318: the top dielectric layer
170: the control grid gap wall
180,232,332: source area
190,234,334: the drain region
210: cap layer
212,312: stack architecture
220,320: the control grid
222,322: clearance wall
226: conductor layer
228: the photoresist layer
Embodiment
Fig. 2 A～Fig. 2 C is the manufacturing process profile that illustrates the non-volatility memorizer of one embodiment of the present invention.Please refer to Fig. 2 A, semiconductor substrate 200 is provided, and in substrate 200, form a plurality of stack architectures 212.Wherein, each rete in the stack architecture 212 from bottom to top is end dielectric layer 214, charge immersing layer 216, top dielectric layer 218, control grid 220 and cap layer 210 in regular turn.The formation method of above-mentioned stack architecture 212 for example is to form end dielectric layer 214, electric charge successively to be absorbed in material layer 216, top dielectric materials layer 218, control grid 208 and cap layer 210 in substrate 200, again each rete is carried out a Patternized technique and get it, known by those skilled in the art as for the detailed method, the material that form above-mentioned stack architecture with relevant coefficient of performance, do not giving unnecessary details in this.
Then, please continue the A with reference to Fig. 2, form a plurality of clearance walls 222 on the sidewall of each stack architecture 212, its material for example is silicon nitride or oxidation.In addition, the method for clearance wall 222 formation for example is to form spacer material layer (not illustrating) earlier and cover stack architecture 212 on the semiconductor-based end 200.Then, etch-back spacer material layer is to form clearance wall 222 on the sidewall of stack architecture 212.
Next, please refer to Fig. 2 B, form gate dielectric layer 224 on the semiconductor-based end 200, its material for example is a silica, and the formation method for example is a thermal oxidation method.Afterwards, on the semiconductor-based end 200, form conductor layer 226, cover stack architecture 212 and fill up space between adjacent two stack architectures 212.Wherein the material of conductor layer 226 for example is a doped polycrystalline silicon, and the method for formation for example is a chemical vapour deposition technique.Then, remove segment conductor layer 226, exposing the cap layer 210 in each stack architecture 212, its method for example is to serve as to grind stop layer to carry out a chemical mechanical milling tech with the cap layer in each stack architecture 212 210.In another preferred embodiment, removing segment conductor layer 226, to expose the method for the cap layer 210 in each stack architecture 212, for example is to be that etch stop layer carries out an etch back process with the cap layer in each stack architecture 212 210., on substrate form the photoresist layer 228 of patterning, be covered on two conductor layers 226 between the stack architecture 212, make the cap layer 210 of part expose out at least thereafter.
Afterwards, please refer to Fig. 2 C, the conductor layer 226 that removes the cap layer 210 in each stack architecture 212 and do not covered by photoresist layer 228 for example is to be mask with photoresist layer 228, carry out a wet etch process, between adjacent two stack architectures 212, to form word line 230.Wherein, remove the method for each stack architecture 212.
Continue it, please continue C, remove photoresist layer 228 with reference to Fig. 2.。Then, form an one source pole district 232 and a drain region 234, the method for its formation for example is an ion implantation at the semiconductor-based end 200 outside each stack architecture 212 of word line 230 both sides.
In the method for above-mentioned formation non-volatility semiconductor, formed clearance wall 222 has preferred quality between control grid 220 and word line 230, in the technology of follow-up formation metal silicide (not illustrating), is difficult for the phenomenon that is short-circuited thus.Therefore, can effectively promote the electric characteristics of non-volatility memorizer.
The follow-up technology of finishing non-volatility memorizer is known technology, does not repeat them here.
Below will cooperate Fig. 3 explanation to utilize the non-volatility memorizer of said method gained.Please refer to Fig. 3, this non-volatility memorizer comprises the semiconductor-based end 300, stack architecture 312, clearance wall 322, gate dielectric layer 324, word line 330, source area 332 and drain region 334.Wherein, a plurality of stack architectures 312 are disposed at at semiconductor-based the end 300, and each stack architecture 312 comprises end dielectric layer 314, charge immersing layer 316, top dielectric layer 318 and control grid 320.
Hold above-mentionedly, end dielectric layer 314 is disposed at at semiconductor-based the end 300, and its material for example is a non-conductive material, as silica.Charge immersing layer 316 is disposed on the bottom oxide 314, and its material for example is a non-conductive material, as silicon nitride.Top dielectric layer 318 is disposed on the charge immersing layer 316, and its material for example is a non-conductive material, as silica.Control grid 320 is disposed on the top oxide layer 318, and its upper surface for example is a smooth upper surface, and its material for example is a conductor material, as doped polycrystalline silicon.
And word line 330 is disposed at at semiconductor-based the end 300 and between adjacent two stack architectures 312, its material for example is a doped polycrystalline silicon.And a plurality of clearance walls 322 are disposed between stack architecture 312 and pairing each word line 330, and its material for example is a non-conductive material, as silicon nitride or silica.Gate dielectric layer 324 disposes word lines 330 and, its material for example is a silica at the semiconductor-based end 300.Source area 332 is disposed at each stack architecture 312 of word line 330 both sides respectively with drain region 334 at the semiconductor-based end 300 outward.
In the non-volatility semiconductor element proposed by the invention, because on word line 330 sidewalls, do not have silica-silicon-nitride and silicon oxide structure, electric charge can not take place be absorbed in the problem of the oxide-nitride thing-oxide structure of sidewalls of wordlines, can promote the reliability of memory component.On the other hand, the control grid 320 of non-volatility memorizer of the present invention has smooth surface, and its external form for example is a cuboid, and in the technology of follow-up formation contact hole, control grid 320 is easier to be electrically connected with contact hole (not illustrating).
In sum, the present invention has following advantage at least:
1. non-volatility memorizer of the present invention can solve that Charge Storage can improve the reliability of memory component in the problem of the silica-silicon-nitride and silicon oxide structure of sidewalls of wordlines in the prior art.
2. the control grid of non-volatility memorizer of the present invention for example is to have a smooth upper surface, and the technology that the subsequent control grid is electrically connected with contact hole is easier carries out.
3. according to the manufacture method of non-volatility memorizer of the present invention, clearance wall at word line and control gate interpolar has preferred quality, the phenomenon that is difficult for being short-circuited in the technology of follow-up formation metal silicide thus can be improved the electric characteristics of memory component.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (20)
1, a kind of manufacture method of non-volatility memorizer comprises:
One substrate is provided;
Form a plurality of stack architectures in this substrate, respectively this stack architecture from bottom to top is an end dielectric layer, a charge immersing layer, a top dielectric layer, a control grid layer and a cap layer in regular turn;
On the sidewall of those stack architectures, form a plurality of clearance walls;
In this substrate, form a gate dielectric layer;
Between adjacent two stack architectures, form a word line;
Remove this cap layer in this stack architecture respectively; And
Form an one source pole district and a drain region in this substrate outside respectively this stack architecture of these word line both sides respectively.
2, the manufacture method of non-volatility memorizer as claimed in claim 1 wherein forms the method for this word line between adjacent two stack architectures, comprising:
In this substrate, form a conductor layer, cover those stack architectures and fill up space between adjacent two stack architectures;
Remove this conductor layer of part, to expose this cap layer in this stack architecture respectively;
In this substrate, form the photoresist layer of a patterning, be covered on this conductor layer between two stack architectures, make this cap layer of part expose out at least;
With this patterning photoresist layer is that mask removes this cap layer in this stack architecture respectively; And
Remove the photoresist layer of this patterning.
3, the manufacture method of non-volatility memorizer as claimed in claim 2, wherein remove this conductor layer of part, to expose the method for this cap layer in this stack architecture respectively, comprise that with this cap layer in this stack architecture respectively serve as to grind stop layer to carry out a chemical mechanical milling tech.
4, the manufacture method of non-volatility memorizer as claimed in claim 2, wherein remove this conductor layer of part, to expose the method for this cap layer in this stack architecture respectively, comprise that with this cap layer in this stack architecture respectively be that etch stop layer carries out an etch back process.
5, the manufacture method of non-volatility memorizer as claimed in claim 1 wherein forms the method for those clearance walls, comprising:
In substrate, form a spacer material layer and cover those stack architectures; And
This spacer material layer of etch-back is to form those clearance walls on the sidewall of those stack architectures.
6, the manufacture method of non-volatility memorizer as claimed in claim 1, the method that wherein forms this gate dielectric layer comprises thermal oxidation method.
7, the manufacture method of non-volatility memorizer as claimed in claim 1, the method that wherein removes this cap layer in this stack architecture respectively comprises wet etching.
8, the manufacture method of non-volatility memorizer as claimed in claim 1, the method that wherein forms those source areas and those drain regions comprises ion implantation.
9, the manufacture method of non-volatility memorizer as claimed in claim 1, wherein respectively the material of this cap layer in this stack architecture comprises silicon nitride.
10, the manufacture method of non-volatility memorizer as claimed in claim 1, wherein the material of those clearance walls for example is silicon nitride or silica.
11, a kind of non-volatility memorizer comprises:
One substrate;
A plurality of stack architectures are disposed in this substrate, and respectively this stack architecture comprises:
One end dielectric layer is disposed in this substrate;
One charge immersing layer is disposed on this bottom oxide;
One top dielectric layer is disposed on this charge immersing layer; And
One control grid is disposed on this top oxide layer;
A plurality of word lines, be disposed in this substrate and respectively this word line between adjacent two stack architectures;
A plurality of clearance walls are disposed at those stack architectures and pairing respectively between this word line;
One gate dielectric layer disposes between those word lines and this substrate; And
Plurality of source regions and a plurality of drain region, and respectively this source area and this drain region respectively are disposed in this outer substrate of respectively this stack architectures of pairing respectively these word line both sides.
12, non-volatility memorizer as claimed in claim 11, wherein those control grids comprise having a flat upper surfaces.
13, non-volatility memorizer as claimed in claim 11, wherein respectively this end dielectric layer in this stack architecture and the material of this top dielectric layer comprise a non-conductive material.
14, non-volatility memorizer as claimed in claim 13, wherein this non-conductive material comprises silica.
15, non-volatility memorizer as claimed in claim 11, wherein respectively the material of this charge immersing layer in this stack architecture comprises a non-conductive material.
16, non-volatility memorizer as claimed in claim 15, wherein this non-conductive material comprises silicon nitride.
17, non-volatility memorizer as claimed in claim 11, wherein the material of those clearance walls comprises a non-conductive material.
18, non-volatility memorizer as claimed in claim 17, wherein this non-conductive material comprises silicon nitride or silica.
19, non-volatility memorizer as claimed in claim 11, wherein the material of those word lines and those control grids comprises a conductor material.
20, non-volatility memorizer as claimed in claim 19, wherein this conductor material comprises doped polycrystalline silicon.
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| CNB2005100674664A CN100386864C (en) | 2005-04-25 | 2005-04-25 | Non-volatile memory and its production |
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| CNB2005100674664A CN100386864C (en) | 2005-04-25 | 2005-04-25 | Non-volatile memory and its production |
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| CN110854184A (en) * | 2018-08-03 | 2020-02-28 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
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| US6346725B1 (en) * | 1998-05-22 | 2002-02-12 | Winbond Electronics Corporation | Contact-less array of fully self-aligned, triple polysilicon, source-side injection, nonvolatile memory cells with metal-overlaid wordlines |
| CN1302555C (en) * | 2001-11-15 | 2007-02-28 | 力晶半导体股份有限公司 | Non-volatile semiconductor storage unit structure and mfg. method thereof |
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| CN110854184A (en) * | 2018-08-03 | 2020-02-28 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
| CN110854184B (en) * | 2018-08-03 | 2023-04-07 | 联华电子股份有限公司 | Semiconductor device and method for manufacturing the same |
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