CN1275320C - Process for preparing self-aligning mask-type ROM - Google Patents
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- CN1275320C CN1275320C CN 01129596 CN01129596A CN1275320C CN 1275320 C CN1275320 C CN 1275320C CN 01129596 CN01129596 CN 01129596 CN 01129596 A CN01129596 A CN 01129596A CN 1275320 C CN1275320 C CN 1275320C
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Abstract
The present invention relates to a method for manufacturing a self-aligning mask type read only memory. A grid stack which has a grid dielectric layer, a grid conductor layer and a grid top cover layer is formed on a substrate. A plurality of source/drain areas, which are not adjacent to the grid stack, are formed on the substrate between the stacks. A first dielectric layer and a patterned photoresistive layer with a plurality of openings are then formed on the substrate in sequence. The patterned photoresistive layer is used as a mask, part of the first dielectric layer is removed, and an ion implantation process is carried out so as to form a plurality of coded self-aligning ion implantation blocks. The patterned photoresistive layer is removed, and an etching back process is carried out again in order to expose the grid conductor layer so as to form a character line.
Description
Technical field
The present invention relates to the manufacture method of a kind of mask-type ROM (Mask ROM), and be particularly related to a kind of can be when sequencing (programming) in the manufacture method of aiming at mask-type ROM voluntarily of two of cell stores.
Background technology
Therefore read-only memory must possess this type of internal memory in many electric equipment products, to keep the normal running between the electric equipment products Push And Release owing to have non-volatile (Non-Volatile) characteristic of not losing data on file because of power interruptions.And mask-type ROM be in the read-only memory the most the basis a kind of, general mask-type ROM commonly used is to utilize channel transistor to be used as memory cell, and sequencing (Program) stage optionally implanting ions to the channel appointed zone, by changing the purpose that critical voltage (Threshold Voltage) reaches control store cell conduction (On) or closes (Off).Wherein the structure of mask-type ROM be the compound crystal silicon character line (Word Line, WL) across bit line (Bit Line, BL) on, the below that the channel of memory cell then is formed at character line and is covered, and the zone between the bit line.For part technology, whether read-only memory is promptly implanted with the channel intermediate ion, stores binary data " 0 " or " 1 ".Wherein, implanting ions is called coding cloth again to the process in channel appointed zone and plants (CodeImplantation) process.
Please refer to Fig. 1, is the plane schematic top plan view of known a kind of mask-type ROM.Character line 102 parallel among the figure is across parallel excessively bit line 104, in the substrate of ion implantation region piece 110, that is be implanting ions in the channel region of memory cell, so as to carrying out the sequencing step, change critical voltage, reach the purpose of control store unit switch.
Then please refer to Fig. 2, is the sequencing generalized section of known mask-type ROM.In substrate 200, have a plurality of stack structures of forming by gate dielectric 202 and gate conductor layer 204 206, be arranged in the source/drain regions 208 of the substrate 200 of 206 on stack structure, the dielectric layer 210 of cover gate stack architecture 206.When the cloth of encoding is planted process, utilize light shield to form a patterned light blockage layer 212 earlier, to expose the zone of desire coding.Then, carrying out admixture implantation process 214, serves as the cover curtain with photoresist layer 212, the boron ion is implanted in the substrate 200 of bottom grid stack architecture 206 belows of desiring coding region, and so as to carrying out sequencing, the program code that institute's desire is formed enrolls in the read-only memory.
Because when carrying out the ion implantation step of sequencing, it is to implant in the substrate 200 by stack structure 206 that the boron ion is implanted, therefore need bigger implantation energy.With the time, can make element produce bigger heat budget (Thermal Budget), and can cause ion scattering or make ion in substrate, diffuse near zone, and then produce the control of interference effect element than macro-energy boron implant ion.Especially,, enter into deep-sub-micrometer technology, under the more and more littler situation of size of component, cause element influence rambunctious bigger in the production of mask-type ROM when the integrated level of integrated circuit is more and more higher.
Summary of the invention
The objective of the invention is to be to provide a kind of manufacture method of mask-type ROM, can in a memory cell, store two data, increase the integrated level of element,, produce more highdensity mask-type ROM simultaneously with the identical light shield number of plies.
Another object of the present invention provides a kind of manufacture method of mask-type ROM, can reduce ion and implant energy, and avoid the interference problem that produces because ion scattering and ion spread in substrate.
According to above-mentioned purpose, the invention provides a kind of manufacture method of mask-type ROM, the method is included in and forms a plurality of gate dielectrics that have in the substrate, one gate conductor layer, and after the stack structure of a grid cap layer, form and the non-conterminous plurality of source/drain of grid structure district in the substrate between the stack structure, and the zone between source/drain regions and the stack structure is a plurality of desire coding regions.Then, forming first dielectric layer in the substrate filling up the gap between the stack structure successively, and the patterned light blockage layer with plurality of openings is to expose first dielectric layer of desiring the coding region top.It then is the cover curtain with the photoresist layer, remove part of first dielectric layer, expose a plurality of ion implantation region piece openings of desiring coding region to form, and carry out an ion implantation process, with the desire coding region that exposes at ion implantation region piece opening, form the ion implantation region piece of a plurality of codings.Afterwards, remove photoresist layer, form one second dielectric layer and fill up ion implantation region piece opening.Carry out an etch-back technics again, expose gate conductor layer, and on gate conductor layer, form a character line.
The manufacture method of mask-type ROM disclosed in this invention, has following feature: form clearance wall in stack structure side walls, utilize this gap wall to make gate conductor layer and source/drain regions form one section little channel, connect little channel or block little channel with multi-form admixture again with loading data, therefore, can in a memory cell, store two data, and then raising element integrated level, with the identical light shield number of plies, produce more highdensity mask-type ROM simultaneously.
In addition, the invention also discloses and on source/drain regions, form one deck conductor layer, can reduce the resistance of source/drain regions, and then improve element efficiency.
In addition, plant in the process, admixture is implanted in the substrate in gate conductor layer and source/drain interval, can reduce ion and implant energy, and avoid the interference problem that produces because ion scattering and ion spread in substrate at coding cloth.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. elaborate:
Description of drawings:
Fig. 1 is the vertical view of known a kind of mask-type ROM;
Fig. 2 is the sequencing generalized section of known a kind of mask-type ROM;
Fig. 3 A to Fig. 3 F is a first embodiment of the invention, the technology generalized section of I-I profile position in Fig. 1.
Fig. 4 A to Fig. 4 F is a second embodiment of the invention, the technology generalized section of I-I profile position in Fig. 1.
Description of reference numerals:
100,200,300,400: substrate
102: character line
104: bit line
110: the ion implantation region piece
202,302,402: gate dielectric
204,304,404: gate conductor layer
206,310,408: the stack structure
208,316,414: source/drain regions
210,318,328,418,428,430: dielectric layer
212,320,420: photoresist layer
214,314,324,412,424: the admixture implantation process
306,406: the grid cap layer
308: sacrifice layer
312,410: clearance wall
317,415: desire coding region
416: material layer
322,424: opening
322a, 424a: ion implantation region piece opening
326,426: doped region
330,432: character line
Embodiment
Embodiment one:
The invention provides a kind of manufacture method of aiming at mask-type ROM voluntarily, its plan structure is similar to Fig. 1.Fig. 3 A to Fig. 3 F is a first embodiment of the invention, about the technology generalized section of I-I hatching among Fig. 1.
At first, please refer to Fig. 3 A, a substrate 300 is provided, in this substrate 300, form gate dielectric 302, gate conductor layer 304, grid cap layer 306 and sacrifice layer 308 successively.Wherein, the material of gate dielectric 302 can be a silica, and the method that forms gate dielectric 302 can be thermal oxidation method (Thermal Oxidation); The material of gate conductor layer 304 can be a compound crystal silicon, the method that forms gate conductor layer 304 can be chemical vapour deposition technique (Chemical Vapor Deposition, CVD); The material of grid cap layer 306 can be silica or silicon oxynitride, and the method that forms grid cap layer 306 can be a chemical vapour deposition technique; The material of sacrifice layer 308 better is to have different etching selectivities with the material of grid cap layer 306, for example is silicon nitride, and the method that forms sacrifice layer 308 can be a chemical vapour deposition technique.
Then, definition sacrifice layer 308, grid cap layer 306, gate conductor layer 304 and gate dielectric 302 are to form a plurality of stack structures 310.The method that forms stack structure 310 can be little shadow and engraving method.
Then please refer to Fig. 3 B, on the sidewall of stack structure 310, form clearance wall 312.The material of this gap wall 312 is preferably with grid cap layer 306 has different etching selectivities.The material of clearance wall 312 can be a silicon nitride, the step that forms clearance wall 312 comprises the conformal insulating barrier (not marking among the figure) of deposition one deck in whole substrate 300 earlier, then remove partial insulative layer, only leaving gap wall 312 on the sidewall of stack structure 310.The method that removes insulating barrier can be the anisotropic etching method, comprises reactive ion-etching (Reactive IonEtching).Because the material of insulating barrier is identical with the material of sacrifice layer 308, therefore when removing insulating barrier, also can remove partial sacrifice layer 308.
Then, carry out an admixture implantation process 314, utilize clearance wall 312 and stack structure 310 to be the cover curtain, form source/drain regions 316 in the substrate 300 between stack structure 310.This source/drain regions 316 promptly is as bit line, and non-conterminous with stack structure 310.And these admixture implantation process 314 employed admixtures for example are the ions of N type or P type.Being preferably the admixture that is difficult for diffusion for example is arsenic ion.The step that forms source/drain regions 316 for example is that (RapidThermal Anneal RTA) is evenly distributed in the substrate 300 admixture to carry out a prompt tempering process after implanting admixture with ionic-implantation.Wherein, at the little channel between source/drain regions 316 and stack structure 310 below the clearance wall 312, be to desire coding region 317 as one.
Then please refer to Fig. 3 C, fill up space between the stack structure 310 forming one dielectric layer 318 in the substrate 300.When selecting the material of dielectric layer 318, be preferably selection clearance wall 312 is had the material of high etch-selectivity, so as to when the follow-up removal clearance wall 312, can not remove too many dielectric layer 318.So the material of dielectric layer 318 can be done suitable adjustment and selection according to clearance wall 312.Therefore, the material of dielectric layer 318 has different etching selectivities with the material of clearance wall 312, for example is silica.The method that forms dielectric layer 318 can be with four-ethyl-neighbour-esters of silicon acis (Tetra Ethyl Ortho Silicate, TEOS)/ozone (O
3) utilize chemical vapour deposition technique to form for reacting gas source.
Then, carry out planarization.Remove sacrifice layer 308, part clearance wall 312 and part dielectric layer 318 to expose the surface of grid cap layer 306 at least.The method that removes sacrifice layer 308, part clearance wall 312 and part dielectric layer 318 can be chemical mechanical milling method (Chemical Mechanical Polishing, CMP).Perhaps also can only remove part dielectric layer 318, make the surface of dielectric layer 318 be lower than the surface of stack structure 310.The method that removes dielectric layer 318 can be a wet etching, with hydrofluoric acid as etchant.
Please refer to Fig. 3 D, form one deck patterned light blockage layer 320 on dielectric layer 318 and grid cap layer 306, have an opening 322 in this patterned light blockage layer 320, opening 322 exposes the clearance wall 312 and part dielectric layer 318 of desiring coding region 317 tops.
Wherein, in the substrate 300 of desiring coding region 317, that is implanting ions in the little channel region between source/drain regions 316 and part of grid pole conductor layer 304, can be so as to carrying out the sequencing step.In addition, the pattern of photoresist layer 320 is the program code that institute's desire forms, and can whereby the preset program code be enrolled in the read-only memory.The method that forms opening 322 can be to carry out in traditional little shadow mode.
Then, utilize photoresist layer 320, remove the clearance wall 312 that opening 322 is exposed, to form the ion implantation region piece opening 322a that exposes the desire coding region 317 between source/drain regions 316 and the gate conductor layer 304 for the cover curtain.The method that removes clearance wall 312 for example is dry-etching method or wet etching.Because the material of clearance wall 312 has different etching selectivities with respect to grid cap layer 306 with dielectric layer 318.Therefore, can avoid removing too many dielectric layer 318 and grid cap layer 306.
Afterwards, serve as the cover curtain with photoresist layer 320, carry out an admixture implantation process 324, below ion implantation region piece opening 322a, form a doped region 326 in the substrate 300 between source/drain regions 316 and gate conductor layer 304.Admixture is implanted desired in the coding region 317, so as to carrying out sequencing, the program code that institute's desire is formed enrolls in the read-only memory.Therefore, doped region 326 is the ion implantation region piece of a coding.Implanting the admixture in the substrate 300 between source/drain regions 316 and the gate conductor layer 304, can be the ion of N type or P type, and the material that preferably is difficult for diffusion for example is an arsenic ion.The method of implanting comprises ionic-implantation, and energy is 5 to 15 kilo electron volts, and implant dosage is about 1 * 10
15/ square centimeter is to 3 * 10
15/ square centimeter.Because arsenic ion is difficult for diffusion, therefore the ion of implanting mainly is distributed in the substrate 300 between source/drain regions 316 and the gate conductor layer 304, and not can with the ion implantation region piece mutual interference mutually of periphery.In addition, because admixture is directly to implant in the substrate 300 of 316 of gate conductor layer 304 and source/drain regions, implant energy so can reduce ion.
Then please refer to Fig. 3 E, remove photoresist layer 320 after, form a dielectric layer 328 and fill up ion implantation region piece opening 322a.The material of dielectric layer 328 can be a silica.The method that forms dielectric layer 318 can be to be that reacting gas source utilizes chemical vapour deposition technique to form with four-ethyl-neighbour-esters of silicon acis/ozone.Then, carry out planarization.Remove the surface that part dielectric layer 328 exposes grid cap layer 306 at least.The method that removes part dielectric layer 328 can be chemical mechanical milling method (Chemical Mechanical Polishing, CMP) or wet etching, with hydrofluoric acid as etchant.
Then, please refer to Fig. 3 F, remove the surface that part dielectric layer 328, part dielectric layer 318 and grid cap layer 306 expose gate conductor layer 304 at least.The method that removes part dielectric layer 328, part dielectric layer 318 and grid cap layer 306 can be chemical mechanical milling method (Chemical Mechanical Polishing, CMP) or wet etching.
Then, in substrate 300, form one deck conductor layer 330, as character line.This conductor layer 330 for example is the compound crystal metal silicide layer.After the step of formation conductor layer 330 comprises that elder generation forms one deck compound crystal silicon layer, on this compound crystal silicon layer, form the layer of metal silicide layer again.And the material of metal silicide layer can be nickle silicide, tungsten silicide, cobalt silicide, titanium silicide, platinum silicide, palladium silicide etc.
In the above-described embodiments, each stack structure 310 has two clearance walls 312 (with reference to Fig. 3 C),, connect little channel or block little channel with multi-form admixture again between gate conductor layer 304 and source/drain regions 316, to form a little channel by clearance wall 312 with loading data.Therefore, can in a memory cell, store two data.
Because the material of clearance wall 312 has different etching selectivities for dielectric layer 318 with the material of grid cap layer 306, therefore, in the etching process that forms ion implantation region piece opening 322a, can remove clearance wall 312 easily, expose out so that desire coding region 317, and can not produce the problem of mis-alignment.
In addition, because after clearance wall 312 is removed, substrate 300 surfaces that exposed are exactly to desire coding region 317, therefore, after clearance wall 312 is removed, during the admixture implantation process 324 of encoding, can so that implanting voluntarily with aiming at, the admixture of being implanted desire coding region 317 and formation doped region 326 with grid cap layer 306 and dielectric layer 318 as implanting the cover curtain.
Embodiment two:
Fig. 4 A to Fig. 4 F is the manufacture method that second embodiment of the invention is aimed at mask-type ROM voluntarily, is the technology generalized section of I-I profile position among Fig. 1.
At first, please refer to Fig. 4 A, a substrate 400 is provided, in this substrate 400, form gate dielectric 402, gate conductor layer 404 and grid cap layer 406 successively.Wherein, the material of gate dielectric 402 can be a silica, and the method that forms gate dielectric 402 can be thermal oxidation method (Thermal Oxidation).The material of gate conductor layer 404 can be a compound crystal silicon, the method that forms gate conductor layer 404 can be chemical vapour deposition technique (Chemical VaporDeposition, CVD).The material of grid cap layer 406 can be silicon oxynitride or silicon nitride, and the method that forms grid cap layer 406 can be a chemical vapour deposition technique.
Then, definition grid cap layer 406, gate conductor layer 404 and gate dielectric 402 are to form a plurality of stack structures 408.The method that forms stack structure 408 can be little shadow and engraving method.
Then please refer to Fig. 4 B, on the sidewall of stack structure 408, form clearance wall 410.The material of this gap wall 410 is preferably with grid cap layer 406 has different etching selectivities.The material of clearance wall 410 can be a silica, the step that forms clearance wall 410 comprises the conformal insulating barrier (not marking among the figure) of deposition one deck in whole substrate 400 earlier, then remove partial insulative layer, only leaving gap wall 410 on the sidewall of stack structure 408.The method that forms insulating barrier can be with four-ethyl-neighbour-esters of silicon acis (Tetra Ethyl OrthoSilicate, TEOS)/ozone (O
3) form for reacting gas source utilizes chemical vapour deposition technique.The method that removes insulating barrier for example is the anisotropic etching method, comprises reactive ion-etching (Reactive Ion Etching).
Then, carry out an admixture implantation process 412, utilize clearance wall 410 and stack structure 408 to be the cover curtain, form source/drain regions 414 in the substrate 400 between stack structure 408.This source/drain regions 414 promptly is a bit line, and non-conterminous with stack structure 408.And these admixture implantation process 412 employed admixtures can be the ions of N type or P type.Being preferably the admixture that is difficult for diffusion for example is arsenic ion.The step that forms source/drain regions 414 can be that (Rapid ThermalAnneal RTA) is evenly distributed in the substrate 400 admixture to carry out a prompt tempering process after implanting admixture with ionic-implantation.Wherein, at the little channel between source/drain regions 414 and stack structure 408 below the clearance wall 410, be a desire coding region 415.
Then please refer to Fig. 4 C, forming the space that layer of material layer 416 fills up between the stack structure 408 in the substrate 400.Afterwards, carry out an etch-back technics, make the surface of material layer 416 be lower than the surface of gate conductor layer 404 at least.When selecting the material of material layer 416, must select that clearance wall 410 is had the material of high etch-selectivity, so as to when the follow-up removal clearance wall 410, can not remove this material layer 416.So the material of material layer 416 can be done suitable adjustment and selection according to clearance wall 410.Therefore, the material of material layer 416 has different etching selectivities with the material of clearance wall 410, is preferably conductive material, for example is compound crystal silicon.The method that forms material layer 416 can be a chemical vapour deposition technique.Because the material of material layer 416 is a conductor material, and contacts with source/drain regions 414, therefore can reduce the resistance of source/drain regions 414.
Then, fill up space between the stack structure 408 forming one dielectric layer 418 on the material layer 416.The material of dielectric layer 418 can be a silica.The method that forms dielectric layer 418 can be to be that reacting gas source utilizes chemical vapour deposition technique to form with four-ethyl-neighbour-esters of silicon acis/ozone.
Afterwards, carry out planarization.Remove the surface that part dielectric layer 418 exposes grid cap layer 406 at least.The method that removes part dielectric layer 418 can be chemical mechanical milling method (Chemical Mechanical Polishing, CMP), perhaps wet etching, with hydrofluoric acid as etchant.
Please refer to Fig. 4 D, form one deck patterned light blockage layer 420 on dielectric layer 418 and grid cap layer 406, have an opening 422 in this patterned light blockage layer 420, opening 422 exposes the clearance wall 410 and part dielectric layer 418 of desiring coding region 415 tops.In the substrate 400 of desiring coding region 415, implanting ions in the little channel region between source/drain regions 414 and part of grid pole conductor layer 404 just can be so as to carrying out the sequencing step.In addition, the pattern of photoresist layer 420 is the program code that institute's desire forms, and can whereby the preset program code be enrolled in the read-only memory.The method that forms opening 422 can be to carry out in traditional little shadow mode.
Then, with photoresist layer 420 is the cover curtain, remove institute's exposed portions dielectric layer 418 and clearance wall 410 from opening 422, to form the ion implantation region piece opening 422a of the desire coding region 415 between expose portion material layer 416 and source/drain regions 414 and the gate conductor layer 404.The method that removes part dielectric layer 418 and clearance wall 410 can be dry-etching method or wet etching.Because the material of material layer 416 has different etching selectivities for clearance wall 410 with dielectric layer 418.Therefore, when removing part dielectric layer 418 and clearance wall 410, etching can terminate on the material layer 416.
Afterwards, carry out an admixture implantation process 424, below ion implantation region piece opening 422a, form a doped region 426 in the substrate 400 between source/drain regions 414 and gate conductor layer 404.Even also admixture is implanted and desired in the coding region 415, so as to carrying out sequencing, the program code that desire is formed enrolls in the read-only memory.Therefore, doped region 426 promptly is the ion implantation region piece of a coding.Implanting the admixture in the substrate 400 between source/drain regions 414 and the gate conductor layer 404, can be the ion of N type or P type, and being preferably the material that is difficult for diffusion for example is arsenic ion.The method of implanting comprises ionic-implantation, and energy is 5 to 15 kilo electron volts, and implant dosage is 1 * 10
15/ square centimeter is to 3 * 10
15About/square centimeter.Because arsenic ion is difficult for diffusion, therefore the ion of implanting mainly is distributed in the substrate 400 between source/drain regions 414 and the gate conductor layer 404, and not can with the ion implantation region piece mutual interference mutually of periphery.In addition, because admixture is directly to implant in the substrate 400 of 414 of gate conductor layer 404 and source/drain regions, implant energy so can reduce ion.
Then please refer to Fig. 4 E, remove photoresist layer 420 after, form a dielectric layer 428 and fill up ion implantation region piece opening 422a.The material of dielectric layer 428 can be a silica.The method that forms dielectric layer 428 can be to be that reacting gas source utilizes chemical vapour deposition technique to form with four-ethyl-neighbour-esters of silicon acis/ozone.Then, carry out planarization.Remove part dielectric layer 428 to expose the surface of grid cap layer 406.The method that removes part dielectric layer 428 can be chemical mechanical milling method (Chemical Mechanical Polishing, CMP) or wet etching, with hydrofluoric acid as etchant.Wherein, dielectric layer 428, dielectric layer 418 are identical with the material of clearance wall 410, can be considered with one deck dielectric layer 430.
Then, please refer to Fig. 4 F, remove the surface that part dielectric layer 430 and grid cap layer 406 expose gate conductor layer 404 at least.The method that removes part dielectric layer 430 and grid cap layer 406 can be chemical mechanical milling method (Chemical Mechanical Polishing, CMP) or wet etching.
Then, in substrate 400, form one deck conductor layer 432, as character line.This conductor layer 432 for example is the compound crystal metal silicide layer.After the step of formation conductor layer 432 comprises that elder generation forms one deck compound crystal silicon layer, on this compound crystal silicon layer, form the layer of metal silicide layer again.And the material of metal silicide layer can be nickle silicide, tungsten silicide, cobalt silicide, titanium silicide, platinum silicide, palladium silicide etc.
In the above-described embodiments, each stack structure 408 has two clearance walls 410, between gate conductor layer 404 and source/drain regions 414, form one section little channel 426 by clearance wall 410, connect little channel or block little channel with multi-form admixture again with loading data.Therefore, can in a memory cell, store two data.And the formation material is a material layer 416 of conductor on source/drain regions 414, can reduce the resistance of source/drain regions 414.
Because the material of the material of clearance wall 410 and dielectric layer 418 has different etching selectivities for the material of material layer 416, therefore, in the etching process that forms ion implantation region piece opening 422a, can remove clearance wall 410 easily, expose out so that desire coding region 415, and can not produce the problem of mis-alignment.
In addition, because after clearance wall 410 is removed, substrate 400 surfaces that exposed promptly are to desire coding region 415, therefore, after clearance wall 410 is removed, during the admixture implantation process 424 of encoding, can so that being implanted in with aiming at voluntarily, the admixture of being implanted desiring coding region 415 and form doped region 426 with grid cap layer 406 and material layer 416 as implanting the cover curtain.
In sum, by preferred embodiment of the present invention as can be known, the present invention has following advantage.
The present invention forms clearance wall in stack structure side walls, utilize clearance wall to make gate conductor layer and source/drain regions form one section little channel, connect little channel or block little channel with multi-form admixture again with loading data, therefore, can in a memory cell, store two data, and then improve the element integrated level.
The present invention forms one deck conductor layer on source/drain regions, can reduce the resistance of source/drain regions, and then improves element efficiency.
The present invention plants in the process at the cloth of coding, and admixture is implanted in the substrate in gate conductor layer and source/drain interval, can reduce ion and implant energy, and avoid the interference problem that produces because ion scattering and ion spread in substrate.
The present invention utilizes the difference of clearance wall and other material etch-rate, can so that clearance wall remove at an easy rate, and because the zone that clearance wall covered promptly is the zone of predictive encoding, therefore after clearance wall is removed, cloth at coding is planted in the process, and the admixture of being implanted can be aimed at the zone of predictive encoding voluntarily.
Though the present invention with preferred embodiment openly as above; but it is not in order to qualification the present invention, any personnel that are familiar with this technology, without departing from the spirit and scope of the present invention; can be used for a variety of modifications and variations, but protection scope of the present invention should be with being as the criterion that claims were limited.
Claims (11)
1. manufacture method of aiming at mask-type ROM voluntarily, it is characterized in that: this method comprises:
One substrate is provided;
Form a plurality of stack structures in this substrate, those stack structures comprise a gate dielectric, a gate conductor layer and a grid cap layer;
On the sidewall of those stack structures, form a plurality of clearance walls;
With those clearance walls and those stack structures is the cover curtain, form the plurality of source/drain district in this substrate between those stack structures, and have a plurality of desire coding regions between those clearance wall belows and those source/drain regions and those stack structures;
In this substrate, form one first dielectric layer, to fill up the gap between those stack structures;
Form a patterned light blockage layer in this substrate, this patterned light blockage layer has plurality of openings, and those openings expose part at least, and those desire this clearance wall of coding region top;
With this photoresist layer is the cover curtain, removes those clearance walls that those openings expose, and those desire a plurality of ion implantation region piece openings of coding region to form expose portion;
With this photoresist layer is the cover curtain, carries out an ion implantation process, desires to form in the coding region ion implantation region of the aligning voluntarily piece of a plurality of codings with those that expose at those ion implantation region piece openings;
Remove this photoresist layer;
Form one second dielectric layer and fill up those ion implantation region piece openings;
Remove this second dielectric layer of part, this grid cap layer, expose this gate conductor layer at least;
On this gate conductor layer, form a character line.
2. manufacture method of aiming at mask-type ROM voluntarily according to claim 1 is characterized in that: the admixture that this ion implantation process is implanted comprises arsenic ion.
3. manufacture method of aiming at mask-type ROM voluntarily according to claim 2 is characterized in that: the implantation energy of this admixture is 5 to 15 kilo electron volts; The implant dosage of admixture is 1 * 10
15/ square centimeter is to 3 * 10
15/ square centimeter.
4. manufacture method of aiming at mask-type ROM voluntarily according to claim 1 is characterized in that: the material of this clearance wall has different etching selectivities for this grid cap layer.
5. manufacture method of aiming at mask-type ROM voluntarily according to claim 1 is characterized in that: the material of this clearance wall has different etching selectivities for this first dielectric layer with the material of this second dielectric layer.
6. manufacture method of aiming at mask-type ROM voluntarily according to claim 1, it is characterized in that: in substrate, form one first dielectric layer, comprise: on this substrate and those stack structures, form this first dielectric layer with the method for filling up the gap between those stack structures;
This first dielectric layer of planarization is up to exposing those stack structures at least.
7. manufacture method of aiming at mask-type ROM voluntarily according to claim 1 is characterized in that: also comprise a sacrifice layer on this grid cap layer.
8. manufacture method of aiming at mask-type ROM voluntarily according to claim 1 is characterized in that: those source/drain regions can be used as the usefulness of bit line.
9. manufacture method of aiming at mask-type ROM voluntarily according to claim 1, it is characterized in that: form after those source/drain regions, more be included in and form a material layer on those source/drain regions, and the surface of this material layer is lower than this gate conductor layer.
10. manufacture method of aiming at mask-type ROM voluntarily according to claim 9 is characterized in that: the material of this material layer has different etching selectivities for the material of this clearance wall.
11. manufacture method of aiming at mask-type ROM voluntarily according to claim 9 is characterized in that: the material of this material layer has different etching selectivities for this first dielectric layer with this second dielectric layer.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01129596 CN1275320C (en) | 2001-06-28 | 2001-06-28 | Process for preparing self-aligning mask-type ROM |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 01129596 CN1275320C (en) | 2001-06-28 | 2001-06-28 | Process for preparing self-aligning mask-type ROM |
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| CN1393926A CN1393926A (en) | 2003-01-29 |
| CN1275320C true CN1275320C (en) | 2006-09-13 |
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| CN 01129596 Expired - Fee Related CN1275320C (en) | 2001-06-28 | 2001-06-28 | Process for preparing self-aligning mask-type ROM |
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| US8502294B1 (en) * | 2012-05-15 | 2013-08-06 | Nanya Technology Corporation | Semiconductor process and semiconductor structure for memory array with buried digit lines (BDL) |
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2001
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