CN1153281C - Method for producing shaded read-only memory with self-aligning metal silicide component unit - Google Patents
Method for producing shaded read-only memory with self-aligning metal silicide component unit Download PDFInfo
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- CN1153281C CN1153281C CNB011095407A CN01109540A CN1153281C CN 1153281 C CN1153281 C CN 1153281C CN B011095407 A CNB011095407 A CN B011095407A CN 01109540 A CN01109540 A CN 01109540A CN 1153281 C CN1153281 C CN 1153281C
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Abstract
The present invention relates to a high-density mask read-only memory comment and method for producing the high-density mask read-only memory comment by a self-aligning metal silicide technology. The high-density mask read-only memory component comprises an embedded bit line N+, a thick oxide layer capable of forming a non-programmable memory unit, a thin gate oxide layer with the thick oxide layer removed and capable of forming a programmable memory unit, a polycrystalline silicon grid structure used as a character line, and a deposited single metal silicide layer. Because only one metal silicide layer needs to be deposited, the technology is simplified. The metal silicide layer is formed on the character line in the read-only memory component and a part of the embedded bit line, and the silicide metal layer can reduce the resistance between the bit line and the character line; thus, the operating speed of the memory unit of the read-only memory component can be increased.
Description
The invention relates to the manufacture method of a kind of semiconductor memory assembly and semiconductor memory assembly, and particularly aim at metal silicide technology voluntarily, to make the method for high-density mask type programmable read only memory relevant for a kind of high-density mask type programmable read only memory and utilization.
ROM module is a kind of semiconductor integrated circuit, and this semiconductor integrated circuit is widely used in the system based on microprocessor.This ROM module is the permanent storage data that is used for, even when power interruptions, data is also not deleted.ROM module is particularly suitable for the assembly of the identical data of many needs or stores needing reusable data.One of them exemplary applications is the basic input output system of personal computer.ROM module is that the array mode with active block stores two signals, and integrated circuit is made quotient system comes this active block of sequencing according to the specification of customer requirement array in manufacture process.
Traditional mask-type ROM comprises NOR gate formula and NAND gate formula.NOR gate formula read-only memory is with transistorized source electrode of a plurality of internal memories and drain electrode, connects in parallel respectively.Yet NAND gate formula read-only memory is with transistorized source electrode of a plurality of internal memories and drain electrode, connects in the mode of connecting.
Please refer to Fig. 1 to Fig. 3, its illustrate is the schematic diagram of the mask-type ROM of known a kind of flat memory cell (flat-cell).The one semiconductor silicon substrate with P type admixture at first is provided.Embedded type bit line 11 is to implant in the substrate with a plurality of elongate strip zones parallel to each other with N type admixture to form, and this embedded type bit line 11 constitutes regions and source.Secondly, in substrate 10, form one deck grid oxic horizon 12, and this grid oxic horizon 12 for example is the silicon oxide layer that forms with thermal oxidation method.Then grid 13 be with vertical direction across on embedded type bit line 11, and this grid 13 constitutes word lines, to be used for the memory array of mask-type ROM assembly.The technology of known coding ties up to and covers one deck patterned light blockage layer 14 in the substrate 10, and exposes a plurality of code areas opening (coding openings) 15.In the channel region of selecting that memory cell exposed, implant admixture then, so as to carrying out the sequencing step.
The channel region of memory cell transistor is between per two adjacent bit lines and be arranged in substrate under the word line.Memory cell transistor is to encode in the mode of blocking-up (blocking) or conducting (conducting)." 1 " or " 0 " data bits can be considered one of two kinds of states.If implant memory cell with P type admixture, then memory cell has high start voltage, and makes memory cell be in "off" state forever, for example for depositing binary digit " 0 " in.If admixture is not implanted memory cell, then memory cell has low start voltage, and makes memory cell be in "open" state, for example for depositing binary digit " 1 " in.
Therefore, when semiconductor subassembly manufacturer strives for improvement performance when reducing cost, the size of ROM module is more and more littler, and the density of ROM module is also along with more and more higher.Yet because size of components dwindles, live width is along with minimizing, makes the word line in the known ROM module and the resistance of bit line increase.Thereby be unfavorable for the service speed of ROM module.
Solution to the problems described above is to utilize resistant to elevated temperatures metal silicide film to reduce the resistance of word line and bit line.Compared to the non-metallic suicides structure, in the technology of aiming at metal silicide (SALICIDE) voluntarily, form source electrode contact, grid contact and the drain electrode contact of low resistance, thereby can reduce the resistance of bit line and word line.Yet the arts demand of aiming at metal silicide is voluntarily incorporated extra step in the technology into.
In No. 5633187 patent case of United States Patent (USP), Soviet Union discloses the technology of aiming at metal silicide voluntarily, with the bit line in the reduction read-only memory and the resistance of word line.Yet the disclosed arts demand of reviving forms two layers of metal silicide layer.Soviet Union discloses deposition one deck tungsten silicide layer on word line, deposits titanium silicide layer then on bit line.
In No. 5712203 patent case of United States Patent (USP), Soviet Union discloses another kind of technology of aiming at metal silicide voluntarily, to reduce the resistance of the bit line in the read-only memory.Though this technology only need form the layer of metal disilicide layer, also only reduced the resistance of bit line.
According to above-mentioned, the semiconductor dealer need provide a kind of technology of aiming at metal silicide voluntarily, makes this technology easily to incorporate in the technology of ROM module, and can reduce the resistance of bit line and word line simultaneously.
Therefore the invention provides a kind of manufacture method of mask-type programmable read only memory, be included in and form the oxide layer of a layer thickness at semiconductor-based the end greater than about 1000 dusts.Then on this oxide layer, form one deck first mask layer, and this first mask layer of patterning, to form bit line.Next removes the oxide layer in bit line zone, to expose the semiconductor-based end.The admixture that then will conduct electricity mixes the substrate that exposes with ionic-implantation, and forms the embedded type bit line zone.Remove first mask layer then, form second mask layer again, form coding pattern subsequently on second mask layer, with formation code area opening, and this code area opening exposes the base part between the bit line.The person of connecing removes second mask layer, and forms one deck grid oxic horizon in the opening of code area.Subsequently remaining oxide layer, embedded type bit line zone with grid oxic horizon on deposition one deck conductive layer, forming the plural conductive grid structure, and these conductive grid structures constitute the word line of mask-type ROMs.Deposition one deck refractory metal in substrate is subsequently aimed at metal silicide layer voluntarily with formation one deck on embedded type bit line and word line.
Another preferred embodiment the invention provides a kind of ROM module, and this ROM module comprises a plurality of bit lines parallel to each other, and it is arranged in substrate; A plurality of word lines, it is perpendicular on the above-mentioned plurality of bit lines; A plurality of internal storage locations are positioned at the confluce of two-phase ortho position line and part word line.One deck metal silicide layer is covered with the bit line portion between the two adjacent word lines.
Above-mentioned general description and detailed description subsequently only are illustrated as example, to provide further explanation to claim of the present invention.
For above and other objects of the present invention, feature and advantage can be become apparent, several preferred embodiments cited below particularly, and cooperate appended graphicly, be described in detail below:
Graphic simple declaration:
Fig. 1 is for looking schematic diagram on known a kind of read-only memory;
Fig. 2 is along the manufacturing process profile of II-II line among Fig. 1;
Fig. 3 is along the generalized section of III-III line among Fig. 1;
Fig. 4 is according to preferred embodiment of the present invention, looks schematic diagram on a kind of memory cell of mask-type ROM;
Fig. 5 A be among Fig. 4 along the generalized section of A-A line, its illustrate is into forming one deck thick oxide layer and the step that forms bit patterns on memory cell areas according to the present invention.
Fig. 5 B be among Fig. 4 along the generalized section of B-B line, this step can more be described;
Fig. 6 A be among Fig. 4 along the generalized section of A-A line, its illustrate is the oxide layer on the etching bitline regions, and implants N
+Admixture is to form the step of embedded type bit line.
Fig. 6 B to Fig. 6 D be among Fig. 4 respectively along the generalized section of B-B line, C-C line and D-D line, this step can more be described;
Fig. 7 A be among Fig. 4 along the generalized section of A-A line, its illustrate is the step that forms the oxide layer in code area pattern and the etching code area.
Fig. 7 B to Fig. 7 D be among Fig. 4 respectively along the generalized section of B-B line, C-C line and D-D line, this step can more be described;
Fig. 8 A be among Fig. 4 along the generalized section of A-A line, its illustrate is the step that forms grid oxic horizon.
Fig. 8 B to Fig. 8 D be among Fig. 4 respectively along the generalized section of B-B line, C-C line and D-D line, this step can more be described;
Fig. 9 A be among Fig. 4 along the generalized section of A-A line, its illustrate is the step of deposition and patterned polysilicon grid.
Fig. 9 B to Fig. 9 D be among Fig. 4 respectively along the generalized section of B-B line, C-C line and D-D line, this step can more be described;
Figure 10 A be among Fig. 4 along the generalized section of A-A line, its illustrate is the step that forms clearance wall.
Figure 10 B to Figure 10 D be among Fig. 4 respectively along the generalized section of B-B line, C-C line and D-D line, this step can more be described; And
Figure 11 A be among Fig. 4 along the generalized section of A-A line, its illustrate is for forming the step of aiming at metal silicide layer voluntarily.
Figure 11 B to Figure 11 D be among Fig. 4 respectively along the generalized section of B-B line, C-C line and D-D line, this step can more be described.
Description of reference numerals:
10: silicon base
11: embedded type bit line
12: grid oxic horizon
13: grid
14: photoresist layer
15: the code area opening
21: thick oxide layer:
The substrate of 23:P type Si semiconductor
25: the first photoresist layers
27: the elongated strip shaped opening
29: bit line
31: the second photoresist layers
33: grid oxic horizon
35: polysilicon
37: the thick oxide layer of patterning
39: the grid oxic horizon of code area
41: the code area opening
43: grid
45: memory cell
47: clearance wall
51: metal silicide layer
Embodiment
Please in detail with reference to embodiments of the invention, and cooperate appended graphic.
Please refer to Fig. 5 A and Fig. 5 B, the thick oxide layer (TOX) 21 of about at least 1000 dusts of deposition one layer thickness in P type Si semiconductor substrate 23.The thickness of thick oxide layer is about ten times of grid oxic horizon of about 100 dusts of thickness.If the thickness of thick oxide layer and the thickness of grid oxic horizon are more or less the same, then not being easily distinguishable is turned to by program " 1 " or " 0 " and data bits.Forming the method for thick oxide layer, for example is heat growth or known low pressure gas phase deposition method.Form thick oxide layer according to said method, can avoid the cross growth oxide layer with and subsequent the formation of " beak " outward appearance.For example, the oxide layer of on whole memory field, growing, therefore " beak " only is grown in the edge of internal memory.Therefore can avoid the outward appearance of " beak " at the memory field field oxide.Similarly, forming the method for continuous thick oxide layer, for example is Low Pressure Chemical Vapor Deposition, can avoid the formation of " beak " outward appearance fully.
The person of connecing, coating photoresistance 25 utilizes known lithographic process patterning photoresist layer 25 subsequently on thick oxide layer 21, and to form a plurality of elongated strip shaped openings 27 parallel to each other, with definition bit line 29, and this bit line can be used as the source/drain regions of memory cell transistor.
The person of connecing please refer to Fig. 6 A to Fig. 6 D and Fig. 7 A to Fig. 7 D, carries out etching step, removing the oxide layer in bitline regions, and exposes the substrate under the oxide layer.Its preferred methods comprises known anisotropic etching method, for example is reactive ion-etching.Be mask with the photoresist layer then, carry out N
+The ion implantation step of admixture, and this N
+The type admixture for example is arsenic or phosphorus.The implantation energy of arsenic admixture is approximately 60 to 120KeV, and employed dosage is about 5 * 10
14To 5 * 10
15Ions/cm
2The implantation energy of phosphorus admixture is approximately 30 to 70KeV, and employed dosage is about 5E14 to 5E15ions/cm
2Please refer to Fig. 6 A to Fig. 6 C, in the substrate that exposes, form N with ionic-implantation
+Zone 29 is with the embedded type bit line as ROM module.
After the step of removing first photoresist layer, form second photoresist layer 31 of patterning, and expose substrate, and the substrate that this exposes system is as the channel region of memory cell.When word line was high voltage, transistor was to be in "open" state.Utilize photoetching process, in photoresist layer, to define code area opening 41, shown in Fig. 7 A to Fig. 7 D.The code area opening optionally exposes the surface of substrate, and forms thin grid oxide layer 33 in subsequent technique in the substrate that exposes.Remove second photoresist layer then.Remove the method for first and second photoresist layer, for example for using known solvent to remove photoresist layer.Utilize technique known then, with the growth grid oxic horizon, and its thickness is decided by employed technology.Please refer to Fig. 8 A to Fig. 8 D, its illustrate is into forming the generalized section of grid oxic horizon.Please refer to Fig. 8 A,, and make silicon layer have higher admixture density because the silicon layer that mixes has oxidation rate faster.Therefore at bit line N
+The thickness of grid oxic horizon be higher than the thickness of the grid oxic horizon on channel.
Please refer to Fig. 9 A to Fig. 9 D, depositing one deck code-pattern polysilicon layer 35 on the remaining thick oxide layer with on the grid oxic horizon, to form word line structure.The method of deposit spathic silicon layer for example is Low Pressure Chemical Vapor Deposition or other known method, and the thickness of deposition is about 2000 dust to 4000 dusts.Utilize photoetching and etch process, forming a plurality of grids 43, and these a plurality of gate electrodes 43 constitute word lines, and wherein word line is used for the memory array of mask-type ROM assembly.
Please refer to Figure 10 A to Figure 10 D, form clearance wall 47,, avoid on gate lateral wall, forming metal silicide layer with the protection gate lateral wall.At first deposit a layer insulating (not shown), carry out the anisotropic etching step again, to form clearance wall 47.The material of insulating barrier for example is a silicon dioxide, and the thickness of its deposition is about 1000 dust to 2000 dusts.Then insulating barrier is carried out the etch-back step, and the etch-back method for example is a reactive ion-etching.
The person of connecing please refer to Figure 11 A to Figure 11 D, aims at metal silicide technology voluntarily, and the refractory metal layer that one deck is thin for example is a titanium, and the thickness of its deposition is about 300 dust to 400 dusts.Under the environment of nitrogen, between 900 degree, heat-treat technology subsequently at temperature 600 degree Celsius.Titanium and the part that bit line, polysilicon layer directly contact form metal silicide 51.With the titanium layer is example, forms titanium silicide (TiSi
2) layer.In remaining zone, titanium and its reaction generate titanium nitride (TiN) or titanium oxynitrides (TiO
xN
y).Carry out selective etch with hot sulfuric acid solution then, Titanium, titanium nitride (TiN) and the titanium oxynitrides (TiO of hot sulfuric acid solution to having neither part nor lot in reaction
xN
y) etch-rate faster than titanium silicide (TiSi
2) etch-rate.Utilize the above-mentioned metal silicide technology of aiming at voluntarily, forming metal silicide layer 51 on the word line of read-only memory with on the part embedded type bit line, and only need deposit the resistant to elevated temperatures metal level of one deck.
Please refer to Fig. 4 and Figure 11 D, the memory cell 45 in the ROM module is positioned at the confluce of word line and two adjacent bit lines.Owing on channel region, be formed with the thick oxide layer 37 of patterning, so the memory cell of closed condition has high start voltage.No matter word line voltage is high or low, memory cell maintains closed condition always.Yet memory cell with code area opening, because the grid oxic horizon 39 in the opening of code area has normal thickness (normal thickness), when word line was in high-voltage state, the memory cell with grid oxic horizon of normal thickness can be set in the state of conducting.According to principle of the present invention, ROM module is formed with metal silicide layer on word line and part bit line.Owing to only need one step to deposit metal silicide layer, therefore can easily this deposition step be incorporated in the technology.And metal silicide layer can reduce the resistance of word line and bit line, accelerates the service speed of memory cell with activation.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can making various improvement and modification in the manufacture method in ROM module, so protection scope of the present invention is when being as the criterion with claims.
Claims (5)
1. manufacture method with the mask-type programmable read only memory of aiming at metal silicide mask component units voluntarily, it is characterized in that: this method comprises the following steps:
Formation have thickness greater than an oxide layer of about 1000 dusts in the semiconductor substrate;
Form one first mask layer on this oxide layer, and this first mask layer of patterning, to form the plurality of bit lines zone;
Remove this oxide layer in those bit line zones, to expose this semiconductor-based end;
Carry out an ion implantation step, the admixture of plural conductive is implanted in this semiconductor-based end that exposes, to form a plurality of embedded type bit line;
Remove this first mask layer, and form one second mask layer;
Form a coding pattern, forming a plurality of code areas opening, and expose this semiconductor base part between adjacent two bit lines;
Remove this second mask layer;
Grow a grid oxic horizon in those code area openings;
Deposition one deck conductive layer is on this remaining oxide layer, this embedded type bit line and this grid oxic horizon;
Form the plural conductive grid structure, and those conductive grid structures are formed a plurality of word lines of this mask-type ROM;
Form insulating gap wall in the sidewall of those grid structures; And
Deposit a refractory metal layer, to form a metal silicide layer on those word lines and those bit lines of part.
2. the manufacture method with the mask-type programmable read only memory of aiming at metal silicide mask component units voluntarily as claimed in claim 1 is characterized in that: wherein form the step of clearance wall, more comprise:
Deposit the silicon dioxide layer of about 1000 dust to 2000 dusts of a thickness; And
Use reactive ion-etching, carry out the etch-back step, to form the sidewall of those grid structures.
3. the manufacture method with the mask-type programmable read only memory of aiming at metal silicide mask component units voluntarily as claimed in claim 1 is characterized in that: wherein form the step of this metal silicide layer, more comprise:
Deposit the titanium layer of about 300 dust to 400 dusts of a thickness;
To 900 degree Celsius, heat-treat technology from temperature 600 degree Celsius, so that the pasc reaction on the polysilicon on titanium and those word lines and those embedded type bit line of part, and form titanium silicide layer; And
Remove the titanium layer part that unreacted becomes titanium silicide layer.
4. the manufacture method with the mask-type programmable read only memory of aiming at the metal silicide component units voluntarily as claimed in claim 1 is characterized in that: wherein this oxidated layer thickness is about ten times of this thickness of grid oxide layer.
5. the manufacture method with the mask-type programmable read only memory of aiming at metal silicide mask component units voluntarily as claimed in claim 1, it is characterized in that: wherein carry out an ion implantation step, the admixture of those conductions was implanted in this semiconductor-based end that exposes, forming those embedded type bit line, and the admixture of those conductions is N
+Admixture.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011095407A CN1153281C (en) | 2001-03-30 | 2001-03-30 | Method for producing shaded read-only memory with self-aligning metal silicide component unit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011095407A CN1153281C (en) | 2001-03-30 | 2001-03-30 | Method for producing shaded read-only memory with self-aligning metal silicide component unit |
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| Publication Number | Publication Date |
|---|---|
| CN1378275A CN1378275A (en) | 2002-11-06 |
| CN1153281C true CN1153281C (en) | 2004-06-09 |
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|---|---|---|---|
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593754B (en) * | 2008-05-26 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Read only memory (ROM) cell array and manufacturing method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1300842C (en) * | 2003-09-18 | 2007-02-14 | 中芯国际集成电路制造(上海)有限公司 | Method for signal implant in making processing of mask type read-only memory |
| KR100880323B1 (en) * | 2007-05-11 | 2009-01-28 | 주식회사 하이닉스반도체 | Method for manufacturing of flash memory device |
| CN102810516B (en) * | 2011-06-02 | 2015-02-04 | 无锡华润上华半导体有限公司 | ROM (read only memory) device and manufacturing method thereof |
-
2001
- 2001-03-30 CN CNB011095407A patent/CN1153281C/en not_active Expired - Fee Related
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101593754B (en) * | 2008-05-26 | 2011-03-23 | 中芯国际集成电路制造(北京)有限公司 | Read only memory (ROM) cell array and manufacturing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1378275A (en) | 2002-11-06 |
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