CN1286178C - Structure of storage device and its manufacturing method - Google Patents
Structure of storage device and its manufacturing method Download PDFInfo
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- CN1286178C CN1286178C CN 02142260 CN02142260A CN1286178C CN 1286178 C CN1286178 C CN 1286178C CN 02142260 CN02142260 CN 02142260 CN 02142260 A CN02142260 A CN 02142260A CN 1286178 C CN1286178 C CN 1286178C
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Abstract
The present invention relates to a structure of a storage device and a manufacturing method thereof. The structure of a storage device comprises a substrate, a plurality of embedded bit lines, a plurality of word lines, a grid oxide layer, a top cover layer, a gap wall, a plurality of channel-shaped connecting wires, a dielectric layer and a plurality of self-aligning contact windows, wherein the embedded bit lines are arranged in the substrate; the word lines are arranged on part of the substrate; the grid oxide layer is arranged between the substrate and the word lines; the top cover layer is arranged on the tops of the word lines; the gap wall is arranged on the lateral walls of the word lines; the channel-shaped connecting wires are respectively arranged on the top cover layer above the embedded bit lines; the dielectric layer is arranged on between the two adjacent word lines and the two adjacent channel-shaped connecting wires; each self-aligning contact window is arranged between the two adjacent word lines under each channel-shaped connecting wire, so the channel-shaped connecting wires are mutually and electrically connected with the embedded bit lines.
Description
Technical field
The invention relates to a kind of structure and manufacture method thereof of memory device, and particularly have memory construction and the manufacture method thereof of double-embedded structure to improve the device reliability of aiming at contact hole voluntarily relevant for a kind of utilization.
Background technology
Memory is as the term suggests be in order to store data or the semiconductor device of data.In the storage of numerical data, our ordinary practice is represented the capacity of memory with position (Bit).Each unit in order to storage data then is called memory cell (Cell) in the memory.And memory cell is in ten hundreds of bank bits, and the ad-hoc location at place then is called address (Address).In other words, memory cell is in memory, and the mode that is able to array is arranged, and each row is represented a particular storage address with the combination of row.Wherein, list in colleague or several memory cell of same column are connected in series with common lead.
Shown in Figure 1, it illustrates the stereogram into known a kind of memory device.
Please refer to Fig. 1, the manufacture method of known memory devices at first forms a gate oxide 102 in substrate 100.Afterwards, in substrate 100, form an embedded type bit line 104.Then, on embedded type bit line 104, form a field oxide isolator 106, in order to isolate embedded type bit line 104 and follow-up formed word line.At last, with direction, on gate oxide 102 and field oxide isolator 106, form a word line 108 perpendicular to embedded type bit line 104.
After dwindling gradually, the width of the embedded type bit line in the memory device must dwindle thereupon along with the raising of integrated circuit integrated level when memory device.Yet the narrowed width of bit line can cause the rising of its resistance, makes the electric current of memory cell diminish and causes too high bit-line load (Bit Line Loading).If utilize the face that the connects degree of depth (Junction Depth) that increases bit line, to solve the problem that the embedded type bit line resistance improves, the short-channel effect (ShortChannel Effect) of not only can deriving also can produce the face electric leakage problems such as (Junction Leakage) that connects.If be to utilize the doping of high concentration to make the bit line of shallow junction, cross the short-channel effect that causes deeply and puncture problem such as electric leakage because of connecing face avoiding, then again can be because of the restriction of solid solubility, and can't overcome the too high problem of bit-line load.Moreover in known memory devices, per approximately 32 bit lines or per 64 bit lines just must have a bit line contacting window, in order to control memory device.Yet the formation of bit line contacting window can limit the integrated level of device.Therefore, the number that how to reduce bit line contacting window also is very important to improve the device integrated level.
Summary of the invention
Purpose of the present invention is exactly in structure that a kind of memory device is provided and manufacture method thereof, to reduce the resistance value of bit line.
Another object of the present invention provides a kind of structure and manufacture method thereof of memory device, and this structure and method can make the face that connects of embedded type bit line do shallow and can not produce problems such as short-channel effect and puncture leakage current.
Therefore, a further object of the present invention is exactly in structure that a kind of memory device is provided and manufacture method thereof, to reduce the number of bit line contacting window, whereby to improve the integrated level of device.
The present invention proposes a kind of structure of memory device, and it is made of the memory cell that several are the array arrangement.This structure comprises that a substrate, several embedded type bit line, several word lines, a gate oxide, a cap layer, a clearance wall, a dielectric layer, several ditching type leads and several aim at contact hole voluntarily.Wherein, embedded type bit line is configured in the substrate.And word line is configured in the part substrate with the direction perpendicular to embedded type bit line.Gate oxide is configured between substrate and the word line.And cap layer is configured in the top of word line.Clearance wall is configured in the sidewall of word line and cap layer.In addition, each ditching type lead is configured in respectively on the cap layer of embedded type bit line top.Dielectric layer then is to be configured between the two adjacent word lines, and between the two adjacent ditching type leads.In other words, the corresponding embedded type bit line of ditching type lead and being configured on cap layer and the dielectric layer, and pass through dielectric layer between the two adjacent ditching type leads and electrical isolation each other.In addition, each aim at voluntarily contact hole be configured under each ditching type lead wherein between the two adjacent word lines, with so that ditching type lead and embedded type bit line be electrically connected to each other.In the present invention, ditching type lead and embedded type bit line are jointly as the bit line of memory device.
The present invention proposes a kind of manufacture method of memory device, and the method at first forms an embedded type bit line in a substrate.Afterwards, form a gate oxide on the surface of substrate.And, on gate oxide, form a word line, wherein the top of word line more is formed with a cap layer.Then, the sidewall at word line and cap layer forms a clearance wall.Continue it, above substrate, form a dielectric layer, cover cap layer.In the present invention, the etching selectivity of cap layer and clearance wall and dielectric layer is less than 1, and in other words, cap layer and clearance wall can make word line avoid being corroded in subsequent step.Then, pattern dielectric layer, to form irrigation canals and ditches in the dielectric layer above embedded type bit line, wherein irrigation canals and ditches expose the cap layer at word line top.Form one afterwards in the dielectric layer under irrigation canals and ditches and aim at contact window voluntarily, expose embedded type bit line, wherein aim at contact window and the irrigation canals and ditches formation a pair of embedding opening of resetting voluntarily.In the present invention, also can form earlier to aim at voluntarily and form irrigation canals and ditches after the contact window again.Afterwards, in the dual-inlaid opening, insert a conductive layer, to form a double-embedded structure.Wherein the lead formula irrigation canals and ditches of double-embedded structure and embedded type bit line be jointly as the usefulness of the bit line of device, and electrically connect by aiming at contact hole voluntarily between the two.
The structure of memory device of the present invention and manufacture method thereof because its bit line is made of embedded type bit line and ditching type lead, therefore can reduce the resistance value of the bit line of memory device.
The structure of memory device of the present invention and manufacture method thereof because the resistance value of its bit line can effectively reduce, so the embedded type bit line in the device can do shallow, avoiding short-channel effect and the problem that connects the face electric leakage, and then the reliability of boost device.
The structure of memory device of the present invention and manufacture method thereof because the resistance value of bit line can effectively reduce, therefore can reduce the voltage drop of bit line, so can reduce the number of device neutrality line contact hole, and then improve the integrated level of device.
For above and other objects of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, elaborate.
Description of drawings
Fig. 1 is the stereogram of known a kind of memory device;
Fig. 2 is according to looking sketch on the memory device of a preferred embodiment of the present invention;
Fig. 3 A to Fig. 3 E is the manufacturing process generalized section according to the memory device of a preferred embodiment of the present invention;
Fig. 4 is the stereogram according to the memory device of a preferred embodiment of the present invention.
Label declaration:
100,200: substrate 102,204: gate oxide
104,202: embedded type bit line 106: field oxide isolator
108,206: word line 208: cap layer
210: clearance wall 212: dielectric layer
214: irrigation canals and ditches 216: aim at contact window voluntarily
218: ditching type lead 220: aim at contact hole voluntarily
Embodiment
Shown in Figure 2, it is according to looking sketch on the memory device of a preferred embodiment of the present invention; Shown in Fig. 3 A to Fig. 3 E, it is the manufacturing process generalized section according to the memory device of a preferred embodiment of the present invention.
Please refer to Fig. 2 and Fig. 3 A, Fig. 3 A is by the generalized section of X-X ' among Fig. 2.At first in a substrate 200, form an embedded type bit line 202.Wherein, the method that forms embedded type bit line 202 for example is to form a patterned light blockage layer (not illustrating) earlier in substrate 200, is that an injecting mask carries out an ion implantation step and forms with photoresist layer afterwards.
Afterwards, please refer to Fig. 2 and Fig. 3 B, Fig. 3 B is by the generalized section of Y-Y ' among Fig. 2.After forming embedded type bit line 202, in substrate 200, form a gate oxide 204, and on gate oxide 204, form a word line 206, wherein the top of word line 206 also comprises and is formed with a cap layer 208.In the present embodiment, form the method for word line 206, gate oxide 204 and cap layer 208, for example utilize a thermal-oxidative production process on the surface of substrate 200, to form a thin oxide layer (not illustrating) earlier, comprehensive formation one conductive material layer (not illustrating) on thin oxide layer afterwards, and on conductive material layer, form a material layer (not illustrating).Afterwards with directional patterns formed material layer and conductive material layer, to form the cap layer 208 at word line 206 and word line 206 tops perpendicular to embedded type bit line 202.Continue it, again the thin oxide layer that is not covered by word line 206 is removed, and the thin oxide layer that stays is gate oxide 204.Wherein, the material of word line 206 for example is a polysilicon, and the material of cap layer 208 for example is silicon nitride or silicon oxynitride.
Then, the sidewall at word line 206 and cap layer 208 forms a clearance wall 210.In the present embodiment, the method that forms clearance wall 210 for example forms a conformal material layer (not illustrating) earlier above substrate 200, afterwards this conformal layer of material of etch-back and form clearance wall 210.Wherein, the material of clearance wall 210 for example is silicon nitride or silicon oxynitride.
Then, please refer to Fig. 3 C, above substrate 200, form a dielectric layer 212, cover cap layer 208.Wherein, the etching selectivity of dielectric layer 212 and cap layer 208 is much larger than 1, and the etching selectivity of dielectric layer 212 and clearance wall 210 is also much larger than 1.Thus, the cap layer 208 that is configured in word line 206 tops just can be protected word line 206 with the clearance wall 210 that is configured in word line 206 both sides, is corroded in the subsequent etch manufacture craft to avoid it.In the present embodiment, the material of dielectric layer 212 for example is a silica, and the method for formation dielectric layer 212 for example is a chemical vapour deposition technique.
Continue it, please refer to Fig. 3 D, pattern dielectric layer 212 is to form irrigation canals and ditches 214 in the dielectric layer above embedded type bit line 202 212.Because the etching selectivity of dielectric layer 212 and cap layer 208 much larger than 1, therefore can be controlled in the dielectric layer 212 that irrigation canals and ditches 214 are formed on cap layer 208 tops easily, and makes irrigation canals and ditches 214 expose the cap layer 208 of word line 206 tops.Afterwards, between the two adjacent word lines 206 under the irrigation canals and ditches 214, form one and aim at contact window 216 voluntarily, and expose embedded type bit line 202.Wherein, irrigation canals and ditches 214 with aim at contact window 216 voluntarily and constitute a pair ofs embedding opening of resetting.
Because the top of word line 206 is formed with cap layer 208, and is formed with a clearance wall 210 at the sidewall of word line 206.Therefore the present invention can form between two adjacent word lines 206 and aim at contact window 216 voluntarily.
In addition, the present invention forms irrigation canals and ditches 214 after also can forming earlier and aiming at contact window 216 voluntarily again.In other words, the present invention can first pattern dielectric layer 212, aims at contact window 216 voluntarily and form one between two adjacent word lines 206, exposes embedded type bit line 202.Afterwards, in the dielectric layer 212 of embedded type bit line 202 tops, form irrigation canals and ditches 214 again, expose cap layer 208.
Afterwards, please refer to Fig. 3 E, in the dual-inlaid opening, insert a conductive layer, with form by ditching type lead 218 with aim at the double-embedded structure that contact hole 220 is constituted voluntarily.Wherein, in the dual-inlaid opening, insert conductive layer with for example first formation one conductive layer comprehensive above substrate 200 of the method that forms double-embedded structure, utilize an etch-back manufacture craft or a cmp manufacture craft to remove the partially conductive layer afterwards, come out up to dielectric layer 212.In the present embodiment, the conductive layer of being inserted in the dual-inlaid opening for example is a metal copper layer or a metal tungsten layer.
What is particularly worth mentioning is that the contact hole 220 of aiming at voluntarily of the present invention couples together ditching type lead 218 and embedded type bit line 202.Therefore, the bit line of memory device of the present invention is made of embedded type bit line 202 and ditching type lead 218.Thus, just can reduce the resistance value of bit line, with in response to having the problem that resistance raises after the device dimensions shrink.And, because method of the present invention can reduce the resistance value of bit line, thus the face that connects of its embedded type bit line 202 can do shallow, to avoid short-channel effect and to connect problem such as face electric leakage, whereby to improve the reliability of device.
Shown in Figure 4, it is the stereogram according to the memory device of a preferred embodiment of the present invention.
Please refer to Fig. 4, memory device of the present invention is made of a plurality of memory cell that are the array arrangement.It comprises a substrate 200, a plurality of embedded type bit line 202, a plurality of word lines 206, a gate oxide 204, a cap layer 208, a clearance wall 210, a dielectric layer 212, a plurality of ditching type lead 218 and a plurality of contact hole 220 of aiming at voluntarily.
Wherein, embedded type bit line 202 is configured in the substrate 200, and word line 206 is configured in part substrate 200 tops with the direction perpendicular to embedded type bit line 202.Gate oxide 204 then is to be configured between word line 206 and the substrate 200.Cap layer 208 is configured in the top of word line 206, and clearance wall 210 is configured in the sidewall of word line 206 and cap layer 208, in order to protection word line 206, is corroded in the subsequent etch manufacture craft to avoid it.
In addition, each ditching type lead 218 correspondence is configured on the cap layer 208 of each embedded type bit line 202 top.Dielectric layer 212 then is to be configured between the two adjacent ditching type leads 218, and between the two adjacent word lines 206, with so that adjacent ditching type lead 218 and adjacent word line 206 electrical isolation each other.In other words, each ditching type lead 218 corresponding each embedded type bit line 202 and being configured on cap layer 208 and the dielectric layer 212, and electrical isolation by dielectric layer 212 and each other between the two adjacent ditching type leads 218.In addition, aim at 220 of contact holes voluntarily and be configured under the ditching type lead 218, in order to ditching type lead 218 and embedded type bit line 202 are coupled together.In other words, aim at voluntarily contact hole 220 be configured under the ditching type lead 218 wherein between the two adjacent word lines 206, with so that ditching type lead 218 and embedded type bit line 202 be electrically connected to each other.Therefore, the bit line of memory device of the present invention is made of embedded type bit line 202 and ditching type lead 218.
Because the bit line of memory device of the present invention is made of embedded type bit line 202 and ditching type lead 218, therefore can reduce the resistance value of bit line, with in response to having the problem that resistance raises after the device dimensions shrink.And it is shallow that the present invention can make the face that connects of embedded type bit line 202 do, to avoid short-channel effect and to connect problem such as face electric leakage, whereby to improve the reliability of device.In addition,, therefore can reduce the voltage drop of bit line, so can reduce the number of device neutrality line contact hole, and then improve the integrated level of device because the resistance value of memory device bit line of the present invention can effectively reduce.
Comprehensive the above, the present invention has following advantage:
1. the structure of memory device of the present invention and manufacture method thereof can reduce the resistance value of the bit line of memory device.
2. the structure of memory device of the present invention and manufacture method thereof, its embedded type bit line can be done shallow, avoiding short-channel effect and the problem that connects the face electric leakage, and then the reliability of boost device.
3. the structure of memory device of the present invention and manufacture method thereof can reduce the number of device neutrality line contact hole, and then improve the integrated level of device.
Though the present invention with preferred embodiment openly as above; right its is not in order to limiting the present invention, anyly is familiar with this operator, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking claims person of defining.
Claims (18)
1, a kind of structure of memory device, this memory device is made of the memory cell that several are the array arrangement, and it is characterized in that: this structure comprises:
One substrate;
Several embedded type bit line are configured in this substrate;
Several word lines are configured in this substrate of part with the direction perpendicular to above-mentioned embedded type bit line;
One gate oxide is configured between this substrate and the above-mentioned word line;
One cap layer is configured in the top of above-mentioned word line;
One clearance wall is configured in the sidewall of above-mentioned word line;
Several ditching type leads are configured in respectively on this cap layer corresponding to above-mentioned embedded type bit line top;
One dielectric layer is configured between the two adjacent above-mentioned word lines, and between the two adjacent above-mentioned ditching type leads;
Several aim at contact hole voluntarily, each is above-mentioned aim at voluntarily contact hole be configured under each above-mentioned ditching type lead wherein between the two adjacent above-mentioned word lines, each above-mentioned ditching type lead and each above-mentioned embedded type bit line are electrically connected to each other.
2, the structure of memory device as claimed in claim 1 is characterized in that: wherein the material of this cap layer comprises silicon nitride or silicon oxynitride.
3, the structure of memory device as claimed in claim 1 is characterized in that: wherein the material of this clearance wall comprises silicon nitride or silicon oxynitride.
4, the structure of memory device as claimed in claim 1 is characterized in that: wherein the material of this dielectric layer comprises silica.
5, the structure of memory device as claimed in claim 1 is characterized in that: wherein this ditching type lead comprises metallic copper or tungsten with this material of aiming at contact hole voluntarily.
6, the structure of memory device as claimed in claim 1 is characterized in that: wherein the material of this word line comprises polysilicon.
7, a kind of manufacture method of memory device is characterized in that: comprising:
In a substrate, form an embedded type bit line;
Form a gate oxide on the surface of this substrate;
Form a word line on this gate oxide, wherein the top of this word line is formed with a cap layer;
Sidewall at this word line and this cap layer forms a clearance wall;
Above this substrate, form a dielectric layer, cover this cap layer;
Form irrigation canals and ditches in this dielectric layer above this embedded type bit line, expose this cap layer;
Form one in this dielectric layer under these irrigation canals and ditches and aim at contact window voluntarily, expose this embedded type bit line, wherein this aims at contact window and this irrigation canals and ditches formation a pair of embedding opening of resetting voluntarily;
In this dual-inlaid opening, insert a conductive layer.
8, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein an etching selectivity of this cap layer and this dielectric layer is less than 1.
9, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein an etching selectivity of this clearance wall and this dielectric layer is less than 1.
10, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein the material of this cap layer comprises silicon nitride or silicon oxynitride.
11, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein the material of this clearance wall comprises silicon nitride or silicon oxynitride.
12, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein the material of this dielectric layer comprises silica.
13, the manufacture method of memory device as claimed in claim 7 is characterized in that: the method for wherein inserting this conductive layer in this dual-inlaid opening comprises:
Above this substrate, form a conductive layer, cover this dielectric layer;
Remove this conductive layer of part, come out up to this dielectric layer.
14, the manufacture method of memory device as claimed in claim 13 is characterized in that: the method that wherein removes this conductive layer of part comprises an etch-back method or a chemical mechanical milling method.
15, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein the material of this conductive layer comprises metallic copper or tungsten.
16, the manufacture method of memory device as claimed in claim 7 is characterized in that: the method that wherein forms this word line and this cap layer comprises:
On this gate oxide, form a conductive material layer;
On this conductive material layer, form a material layer;
With the direction perpendicular to this embedded type bit line, this conductive material layer of patterning and this material layer are to form this word line and this cap layer.
17, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein the material of this word line comprises polysilicon.
18, the manufacture method of memory device as claimed in claim 7 is characterized in that: wherein form these irrigation canals and ditches and this method of aiming at contact window voluntarily and comprise that also forming this earlier aims at after the contact window voluntarily, forms these irrigation canals and ditches again.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02142260 CN1286178C (en) | 2002-08-28 | 2002-08-28 | Structure of storage device and its manufacturing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02142260 CN1286178C (en) | 2002-08-28 | 2002-08-28 | Structure of storage device and its manufacturing method |
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| Publication Number | Publication Date |
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| CN1479376A CN1479376A (en) | 2004-03-03 |
| CN1286178C true CN1286178C (en) | 2006-11-22 |
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| CN 02142260 Expired - Fee Related CN1286178C (en) | 2002-08-28 | 2002-08-28 | Structure of storage device and its manufacturing method |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100378959C (en) * | 2005-07-07 | 2008-04-02 | 旺宏电子股份有限公司 | Non-volatile memory body and mfg. method |
| CN100378952C (en) * | 2005-08-16 | 2008-04-02 | 力晶半导体股份有限公司 | Method of manufacturing semiconductor component, and connecting wire with metal silicides |
| CN100418209C (en) * | 2005-08-16 | 2008-09-10 | 力晶半导体股份有限公司 | Method of manufacturing nonvolatile memory |
| CN101496173B (en) * | 2006-07-27 | 2010-12-22 | 松下电器产业株式会社 | Nonvolatile semiconductor storage device and method for manufacturing same |
| US9653401B2 (en) | 2012-04-11 | 2017-05-16 | Nanya Technology Corporation | Method for forming buried conductive line and structure of buried conductive line |
| WO2022077167A1 (en) * | 2020-10-12 | 2022-04-21 | Yangtze Advanced Memory Industrial Innovation Center Co., Ltd | Novel self-aligned half damascene contact scheme to reduce cost for 3d pcm |
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2002
- 2002-08-28 CN CN 02142260 patent/CN1286178C/en not_active Expired - Fee Related
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