WO2022077167A1

WO2022077167A1 - Novel self-aligned half damascene contact scheme to reduce cost for 3d pcm

Info

Publication number: WO2022077167A1
Application number: PCT/CN2020/120435
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-10-12
Filing date: 2020-10-12
Publication date: 2022-04-21
Also published as: CN112449724A

Abstract

A self aligned half damascene contact scheme to reduce cost for 3D PCM is disclosed. In the proposed contact scheme, contact holes are formed first followed by low resistivity metal deposition to fill the holes and form blanket metal films. Subsequently bit line and word line can be formed by photolithography and dry etch of metal films. Metals can be of low resistivity, such as W, Co, Rh, Ru, Ir, Mo, or a mixture with graphene. As such for 2 stack, three metal CMPs can be eliminated. For 4 stacks, five metal CMPS can be eliminated. WL and BL formed with Co, Rh, Ru are friendly to scaling. There is no interface contact resistance between WL/BL and contacts with the disclosed scheme. Multiple metal CMPs are eliminated to lower cost. Self alignment prevents adjacent metal shorts.

Description

[Title established by the ISA under Rule 37.2] NOVEL SELF-ALIGNED HALF DAMASCENE CONTACT SCHEME TO REDUCE COST FOR 3D PCM

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to reducing multiple metal chemical-mechanical planarizations to reduce costs for 3D X-Point memory manufacturing.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.

Phase-change memory (PCM) is a non-volatile solid-state memory technology that exploits reversible, thermally-assisted switching of phase-change materials like chalcogenide compounds such as GST (Germanium-Antimony-Tellurium) , between states with different electrical resistance. The fundamental storage unit (the “cell” ) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. Programmable cell-states can be used to represent different data values, permitting storage of information.

PCM cells are programmed or erased by thermal self heating to induce an amorphous or crystalline state to denote 1 and 0. Programming current is directly proportional to the size and cross-sectional area of the PCM cell. In single-level PCM devices, each cell can be set to one of two states, a “SET” state and a “RESET” state, permitting storage of one bit per cell. In the RESET state, which corresponds to a wholly amorphous state of the phase-change material, the electrical resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state on rapid cooling.

In addition, large programming current requirements also lend to large program voltage requirements. Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase- change material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell.

This current is dependent on resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing the resistance metric with predefined reference levels. Programming current (I) is typically in the order of 100-200μA. The voltage drop may be significant if the write or word line (WL) and bit line (BL) in the cell encounters large resistance.

In commercial 3D X-point memory, word lines and bit lines are formed of 20nm/20nm L/Spattern. The memory chip is composed of many small memory arrays (tile) , and is at risk from large voltage drops across word lines and bit lines during program operation. Typically 3D X-point memory, bit lines and word lines are formed of tungsten (W) that has an electrical property of relatively high resistivity. Separate contacts are formed for each bit line and word line individually, which requires one contact etch and one contact chemical-mechanical planarization (CMP) . In addition, bit lines and word lines have to align with contacts in order to make good electrical contacts. As such, alignment marks are very tight, and tolerances are such that cost is increased.

Thus there is a need in the art for a self-aligned half damascene contact scheme that will minimize the interface contact resistance between write or word line and bit line and the contacts, eliminate multiple metal CMPs to lower costs, and self-align to prevent adjacent metal shorts.

SUMMARY

The following summary is included in order to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and as such it is not intended to particularly identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a summarized format.

In one aspect, a new self-aligned damascene contact scheme for 3D X-Point Memory is presented allowing a reduced programming current and reduced write line and bit line resistance as compared to current state of the art 3D X-Point Memory cell structures. In the present new cell structure, each stack is composed of a perpendicular word line and a bit line. The memory cell stack is self-aligned to the word line and the bit line. The word lines and the bit lines are formed using material that contains tungsten (W) or cobalt (Co) or rhodium (Rh) or ruthenium (Ru) or iridium (Ir) or molybdenum (Mo) , or a mixture of one or more of these metals with graphene. These materials are good candidates to reduce resistance for several purposes including scaling of the memory array. Compared with tungsten, cobalt, for example, shows less resistivity increase with scaling and has an estimated 40%lower resistivity than tungsten for 20nm wide interconnects. The word line or bit line contact holes are formed individually and filled by word line or bit line metals.

In another aspect, a method for forming a new self-aligned half damascene contact for 3D X-Point Memory is disclosed. The method includes forming a cross-point memory array with parallel bit lines and perpendicular word lines. Word line and bit line contact holes are formed. The word line and bit line contact holes are filled by word line or bit line metals.

In another aspect, a 3D X-Point Memory Die architecture is disclosed. Quantities of memory arrays (tiles) are separated by small space, typically 20nm in an X-direction and a Y-direction of the array. Tungsten (W) or cobalt (Co) or rhodium (Rh) or ruthenium (Ru) or iridium (Ir) or molybdenum (Mo) , or a mixture of one or more of these metals with graphene, write lines and bit lines electrically access each memory cell.

In accordance with an aspect, a three-dimensional memory cell structure includes at least one memory cell stack. The memory cell stack has a selector, a phase change memory cell, and a first electrode, a second electrode and a third electrode. The phase change memory cell is disposed between the first and the second electrode, and the selector is disposed between the second and the third electrode. A word line and a bit line are perpendicular to each other and coupled to the memory cell stack. The memory cell stack is self-aligned or overlay controlled with respect to the word line and the bit line. The word line is formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. The bit line formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. At least one word line contact hole or bit line contact hole are formed, wherein the word line contact hole or the bit line contact hole is filled by a word line metal or bit line metal.

In some arrangements, the word line contact hole or the bit line contact hole is filled by the word line metal or bit line metal and forms a blanket metal film above the word line hole or bit line contact hole.

In some arrangements, the word line or the bit line is formed with a half-damascene process.

In some arrangements, the blanket metal film forms the word line or the bit line.

In some arrangements, the three-dimensional memory includes a substrate, wherein the word line contact hole or the bit line contact hole is first formed in the substrate.

In another aspect, a three-dimensional X-Point Memory Die architecture includes a plurality of top memory arrays or tiles containing a first set of phase change memory cells, and a plurality of bottom memory arrays or tiles containing a second set of phase change memory cells. A plurality of bit lines are coupled to the top array and coupled to the bottom array. A plurality of word lines are perpendicular to the bit lines, and comprise a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array. The top array of memory cells are each separated by a first space defined by adjacent phase change memory cell in the top array, and the bottom array of memory cells are each separated by a second space defined by adjacent phase change memory cell in the bottom array. The word lines are formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene, and the bit lines are formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene to electrically access each memory cell.

In accordance with in aspect, a method of forming a three-dimensional memory comprises forming first a cross point memory array with a parallel bit line and a perpendicular word line, and forming a memory cell stack at a cross point of the word line and the bit line. The memory cell stack is self-aligned. The bit line and word line are formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. The word line and the bit line have reduced resistance and also use reduced voltage to improve programming and increase array size as compared to the bit line and the word line being formed from material containing tungsten (W) .

In some arrangements, the method includes forming the word line and the bit line by a half-damascene process.

In another aspect, a self-aligned half-damascene contact scheme forms contact holes first followed by low resistivity metal deposition to fill the holes and form blanket metal films for the 3D X-Point PCM memory cell. Subsequently bit line and word line can be formed by photolithography and dry etch of metal films. Again, metals used, depending on the embodiment, may be of low resistivity, including but not limited to W, Co, Rh, Ru, Ir, Mo, or a mixture with graphene. As such for 2 stack, three metal CMPs can be eliminated. For 4 stacks, five metal CMPS can be eliminated. WL and BL formed with Co, Rh, Ru are friendly to scaling. There is no interface contact resistance between WL/BL and contacts with the disclosed scheme. Multiple metal CMPs are eliminated to lower cost. Self alignment prevents adjacent metal shorts.

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity.

However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Fig. 1 is an isometric view of a prior three-dimensional cross point memory.

Figs. 2A and 2B are plan views of a section of a three-dimensional cross point memory showing a bottom cell stack deposition, and Fig. 2C is a diagram showing abbreviations for layers in the cell stack.

Figs. 3A and 3B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 2A-2D with bottom cell double patterning and encapsulation layer deposition, respectively.

Figs. 4A and 4B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 3A and 3B showing a gap fill layer and chemical mechanical planarization (CMP) , respectively.

Figs. 5A and 5B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 4A and 4B showing word line contact hole etching and word line metal deposition to fill the contact hole and form a blanket metal film.

Figs. 6A and 6B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 5A and 5B in the Y-direction of the memory, showing word line double patterning and a first partial etching to form parallel lines.

Figs. 7A and 7B are plan views of the three-dimensional cross point memory, in the Y-direction of the memory in accordance with the embodiment of Figs. 6A and 6B showing encapsulation, gap filling and polishing the cell stack.

Figs. 8A and 8B are plan views of the three-dimensional cross point memory in the Y-direction of the memory in accordance with the embodiment of Fig. 7 showing a second stack memory cell deposition and patterning with top bit line contact hold formation.

Figs. 9A and 9B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 8A and 8B showing top bit line metal deposition and patterning to form the top cell.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” and the like, merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer there between, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer there between (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Non-limiting examples include silicon, germanium, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glasses, combinations or alloys thereof, and other solid materials. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpattern. Furthermore, the substrate can include a wide array of semiconductor materials, including but not limited to silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above” , “below” , “bottom” , “top” , “side” (e.g. sidewall) , “higher” , “lower” , “upper” , “over” , and “under” , are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements.

As used herein, a material (e.g. a dielectric material or an electrode material) will be considered to be “crystalline” if it exhibits greater than or equal to 30%crystallinity as measured by a technique such as x-ray diffraction (XRD) . Amorphous material is considered non-crystalline.

As used herein, the terms “first, ” “second, ” and other ordinals will be understood to provide differentiation only, rather than imposing any specific spatial or temporal order.

As used herein, the term “oxide” (of an element) will be understood to include additional components besides the element and oxygen, including but not limited to a dopant or alloy. As used herein, the term “nitride” (of an element) will be understood to include additional components besides the element and nitrogen, including but not limited to a dopant or alloy.

As used herein, the term “Damascene” will be understood to mean a Damascene Process. In this process, the underlying silicon oxide insulating layer is patterned with open trenches or channels that the conductor should be located. A thick coating of copper that significantly overfills the trenches is deposited on the insulator, and chemical-mechanical planarization (CMP) is used to remove the copper (known as overburden) that extends above the top of the insulating layer. Copper sunken within the trenches or channels of the insulating layer is not removed and becomes the patterned conductor. Damascene processes generally form and fill a single feature with copper per Damascene stage. Dual-Damascene processes generally form and fill two features with copper at once. So generally, the damascene method involves etching line and via features in the dielectric, a silica-based material, then filling those features with barrier and Cu metal. The excess metal is removed by CMP and the wafer is then processed by an aqueous post-CMP cleaning step.

A modification of this process, known as “half damascene” fabrication, is used to decrease the overlap of the source and drain with an island by fabricating the island inlaid in the substrate dielectric. Process steps in fabricating the “half‐damascene” are shown in the following diagram and may be used to form various components in a semiconductor including cross‐tie single electron transistors (SET) . The following steps are a general explanation of the half-damascene process: (a) Si substrate (dark grey) is oxidized (SiO2 in blue) ; (b) a trench for the island is etched through an Electron-beam lithography (EBL) defined polymethylglutarimide (PMGI) mask (yellow) ; (c) metal (light grey, e.g. Ni) is deposited; EBL is the practice of scanning a focused beam of electrons to draw custom shapes on a surface covered with an electron-sensitive film called a resist (also known as “exposing” ) (d) the chemical mechanical planarization or polishing (CMP) step is performed and metal island is formed; (e) ALD dielectric (green) is deposited; (f) metal source and drain electrodes (light grey) are deposited; and (g) micrograph of half‐damascene SET (gate not shown) . The nearly vertical line is the inlaid island and the slightly wider, nearly horizontal lines are the source and drain.

The present technology is applied to a new self-aligned half-damascene contact scheme to reduce costs for 3D X-Point Memory. In the proposed new contact scheme, contact holes are formed first, followed by low resistivity metal deposition to fill the holes and form blanket metal films. Subsequently, the bit line and word line can be formed by photolithography and dry etch of metal films. Metals can be made of low resistivity, such as at least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. As such, for a two (2) stack, for example, three (3) metal chemical- physical planarizations (CMP) can be eliminated. For a four (4) stack, five metal CMPs can be eliminated. Word lines and bit lines formed with cobalt, rhodium, and ruthenium were found to be more acceptable to scaling than materials like tungsten or copper. Cell stack height and aspect ratio is effectively reduced due to thinner metal used or elimination of a metal etching altogether for the word line and bit line formation. Voltage drop is reduced compared to prior art word lines and bit lines using tungsten (W) . Subarray or tile size is increased accordingly to improve array efficiency. Compared with tungsten, cobalt shows less resistivity increase with scaling and has an estimated 40%lower resistivity than tungsten for 20-nm-wide interconnects. Thus the use of Co, Rh, Ru, for example, are good candidates to reduce resistance in word lines and bit lines in 3D X-Point Memory for scaling purposes. No interface contact resistance is present between the write line/bit line and contacts. Multiple metal chemical-physical planarizations are eliminated, thus lowering manufacturing costs. Bit lines and word lines are self-aligned with the contacts to prevent adjacent metal shorts.

The present technology is applied in the field of three-dimensional memory. A generalized prior example of a three-dimensional (3D) memory is shown in FIG. 1A. In particular, Fig. 1 is an isometric view of a section of three-dimensional cross-point memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in the X direction. Above the first layer of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction. Further, as can be seen from the figure, the sequential structure of bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration. In any event, an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell. Reference will be made to X and Y directions utilizing the directional model shown in FIG. 1.

FIG. 1 illustrates the general structure of a 3D X-Point Memory cell, and that terminology is used herein to describe the improvement. The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern, and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

As stated above, there is an issue of separate contacts are formed for each bit line and word line individually, which requires one contact etch and one contact chemical-mechanical planarization (CMP) . Bit lines and word lines have to align with contacts in order to make good electrical contacts. Moreover, alignment marks are very tight. The present disclosure addresses this issue and provides reducing costs for the manufacture of a 3D X-Point Memory by eliminating multiple CMPs. Adverting to FIG. 2A is a plan view of a structure showing forming bit line contact holes 200 in a substrate 201. FIG. 2B illustrates bottom cell stack deposition. The substrate 201 with bit line contact holes 200 have the following layers deposited thereon. Starting from the bottom of the cell stack deposition, deposited in the bit line contact holes 200 of FIG. 2A is the bit line metal 202 and a bit line layer also labeled as 202, a first carbon electrode 209, a selector or an ovonic threshold switch (OTC) 208, a second carbon electrode 207, a phase change memory cell 206, a third carbon electrode 205, and a nitride layer 204. Examples of such materials include metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials. Typically, deposition may be accomplished by chemical vapor deposition (CVD) . In this process, a vacuum deposition method is used to produce high quality, high performance, and solid materials. In typical CVD, the water (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit.

Layer 202 may be a tungsten based compound and functions as a conductor among other things. Depending on the embodiment, the conductor may be made of other materials that have conductive properties. Accordingly, depending upon the implementation, the bit line metal 202 and bit line layer 202 may be formed from material containing at least one of cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene.

Layer 204 referred herein as a nitride layer is shown in FIG. 2C. Examples of such nitride materials include, but are not limited to, metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials.

Again, as previously stated the use of the terms first, second and third is to provide differentiation only, rather than imposing any specific spatial or temporal order. The

carbon electrodes

205, 207 and 209 may be interchangeable and the reference to the terms first, second and third are merely used as a reference to describe adjacent elements. The electrodes can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Depending on the embodiment, the electrode may be a carbon electrode or any other electrode known to one skilled in the art.

The layers shown in FIG. 2C are abbreviated as: W/C/OTS/C/PCM/C/Nit stack as shown in FIG. 2C. These abbreviations refer to tungsten layer, a first carbon electrode, a selector or ovonic threshold switch, a second carbon electrode, a phase change memory cell, a third carbon electrode, and a nitride layer, respectively. Reference numeral 201 refers to the substrate or an oxide layer. Oxide is also denoted as reference numerals 312 and 812 herein as shown in FIG. 2C.

FIG. 3A shows

exemplary cell stacks

1, 2, and 3. Each stack is made of several layers as previously described in FIGS. 2A-2C. The cell stacks 1, 2, and 3 are similar in function and composition. For the description of materials disclosed herein, similar reference numerals to common elements in various figures denote similar material and functions of the elements shown and described. Tungsten 202 is within the substrate 201 and in the cell stack as shown in FIG. 3A.

Also shown in FIG. 3A is a bottom cell double patterning to form a parallel bottom cell in electrical contacts with bottom bit lines. A first partial etch occurs to etch through the top electrode 205 and PCM cell 206 and stops on electrode 207 to form parallel lines. Bottom cell double patterning with first etching or partial etching, depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide or other methods known by those skilled in the art. FIG. 3B also illustrates deposition of nitride and

oxide encapsulation

310, 312 to cover

stacks

1, 2, and 3 to protect the exposed electrode 205 and PCM cell 206 in each stack. Encapsulation layer 310 may be composed of silicon nitride or other suitable materials.

Stacks

1, 2, and 3 may be further encapsulated with oxide layer 312 including a substrate.

FIG. 4A illustrates the second etching to etch through the remaining

electrodes

207, 209, ovonic thermal switch (OTC) 208 and conductor 202 to form parallel bottom cell bit lines. Encapsulation layer 410 deposition covers

stacks

1, 2, and 3 to protect the now exposed ovonic thermal switch (OTC) 208 in each stack. After encapsulation, gap fill 402 covers the

stacks

1, 2, and 3. Gap fill 402 may be obtained through atomic layer deposition (ALD) oxide, Spin on Dielectric (SOD) , or flowable chemical vapor deposition (CVD) oxide and is synonymous with

gap fill

211, 402, and 802 as shown herein. Examples of gap fill materials, include, but are not limited to, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) and lead selenide (PbSe) and cobalt based compounds and any combination thereof. FIG. 4B illustrates oxide/nitride chemical mechanical planarization (CMP) treatment to the

stacks

1, 2, and 3. The CMP treatment stops on the carbon electrode 205 as shown in FIG. 4B.

FIGS. 5A and 5B illustrate a word line contact hole etching step and word line metal deposition step. In a preferred embodiment, the word line is formed by a half-damascene process. FIG. 5A shows the gap fill etching, which is stopped at the tungsten 202 filled substrate 201. Wet etching is used to remove a portion of gap fill 402 to fill with word line metal 502. Depending on the implementation, ammonium hydroxide or hydrogen peroxide may be utilized in the etching process. FIG. 5B illustrates the word line metal deposition step, which fills the contact hole 500 and then forms a blanket metal layer 502. The metal layer 502 may be tungsten or any other conductor metal, such as at least one of cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. Typically deposition may be accomplished by chemical vapor deposition (CVD) . In this process a vacuum deposition method is used to produce high quality, high-performance, solid materials. In typical CVD, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Depending upon the embodiment, layer 202 may be filled before or during the formation of the blanket metal layer 502.

FIGS. 6A and 6B illustrate bottom cell word line double patterning of the embodiment shown in FIGS. 5A and 5B to form parallel bottom cell write lines perpendicular to bit lines that are in contact with the bottom cell top carbon electrode 205. FIG. 6A is a cross-section taken from stack 1 of FIG. 5B along line 6A-6A showing the various layers described in FIG. 5B shown in the Y-direction. As shown in FIG. 6B, a first partial etch occurs to etch through the top electrode 205, PCM 206, and stops on electrode 207 to form parallel lines. Etching, depending on the embodiment, may be accomplished for example using hydrogen peroxide or ammonium hydroxide, or by other methods known by those skilled in the art.

FIGS. 7A and 7B illustrate deposition of nitride and

oxide encapsulation

710, 712 to cover

stacks

1, 2, and 3 to protect the exposed electrode and nitride-recess liner confined phase change memory cell in each stack. Encapsulation layer 710 may be composed of silicon nitride or other suitable materials.

Stacks

1, 2, and 3 may be further encapsulated with oxide layer 712 including a substrate. Bottom cell write line etching then occurs with a second etching to etch through the remaining

electrodes

207, 209, ovonic thermal switch 208, and conductor 202 to form parallel bottom cell word lines. Encapsulation layer 714

deposition covering stacks

1, 2, and 3 to protect the now exposed ovonic thermal switch 208 in each stack. After encapsulation, gap fill 702 covers the

stacks

1, 2, and 3. Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) or flowable chemical vapor deposition (CVD) oxide. Oxide chemical mechanical polishing (CMP) is done and stopped on conductor 502, as shown in FIG. 7B. Again depending on the embodiment conductor 502 may be tungsten (W) or another conductive material.

FIGS. 8A and 8B illustrate a top cell stack of memory cell deposition and double patterning with the new cell structure described herein. As shown in the X direction in FIG. 8A, top section 810 is formed by depositing on bottom section 830 write line metal 202, carbon electrode 209, OTS 208, carbon electrode 207, PCM 206, carbon electrode 205, and nitride layer 204 (not shown) . Top cell and bottom cell write lines 820 separate the two stacks. Oxide/nitride chemical mechanical polishing (CMP) treatment to the

stacks

801, 802, and 803. The CMP treatment stops on carbon electrode 205. Again, depending on the implementation, the word line may be formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. As shown in the Y direction in FIG. 8B, gap fill 840 is etched to form top bit line contact hole 850. In an embodiment, top bit line contact hole 850 is formed utilizing a half-damascene process.

FIGS. 9A and 9B illustrate top bit line metal deposition to fill contact hole 850 and double patterning to form the top cell. Shown is top section 810 and bottom section 830. Top cell and bottom cell write lines 820 separate the two stacks. Bit line metal 902 is deposited to fill bit line contact hole 850 from FIG. 8B and double patterning is performed to form the top cell 810. Depending upon the implementation, the top bit line may be formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of graphene. In an embodiment, the top bit line 902 is formed by a half-damascene process.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory cell structure, comprising:

at least one memory cell stack, the memory cell stack having a selector, a phase change memory cell, and a first electrode, a second electrode and a third electrode; the phase change memory cell disposed between the first and the second electrode, and the selector disposed between the second and the third electrode;

a word line and a bit line perpendicular to each other and coupled to the memory cell stack, wherein the memory cell stack is self-aligned with respect to the word line and the bit line;

the word line formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of one or more of these metals with graphene;

the bit line formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of one or more of these metals with graphene;

at least one word line contact hole or bit line contact hole; and

wherein, the word line contact hole or the bit line contact hole is filled by a word line metal or bit line metal.
The three-dimensional memory according to claim 1, wherein the word line contact hole or the bit line contact hole is filled by the word line metal or bit line metal and forms a blanket metal film above the word line hole or bit line contact hole.
The three-dimensional memory according to claim 2, wherein the word line or the bit line is formed with a half-damascene process.
The three-dimensional memory according to claim 2, wherein the blanket metal film forms the word line or the bit line.
The three-dimensional memory according to claim 1, further comprising a substrate and wherein the word line contact hole or bit line contact hole is first formed in the substrate.
A three-dimensional Memory Die architecture, comprising:

a plurality of top memory arrays or tiles containing a first set of phase change memory cells;

a plurality of bottom memory arrays or tiles containing a second set of phase change memory cells;

a plurality of bit lines coupled to the top array and coupled to the bottom array;

a plurality of word lines perpendicular to the bit lines, and comprising a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array;

the top array of memory cells are each separated by a first space defined by adjacent phase change memory cell in the top array, and the bottom array of memory cells are each separated by a second space defined by adjacent phase change memory cell in the bottom array, and

wherein, the word lines are formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of one or more of these metals with graphene, and the bit lines are formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of one or more of these metals with graphene, to electrically access each memory cell.
The three-dimensional architecture according to claim 8, wherein the top and the bottom word lines are coupled thereto.
The three-dimensional architecture, wherein the first space and second space are about 20nm in an X-direction and about 20nm in a Y-direction.
A method of forming a three-dimensional memory comprising:

forming first a word line contact hole and bit line contact hole in a substrate;

depositing word line metal in the word line contact hole and bit line metal in the bit line contact hole to fill the contact holes and form a blanket word line metal film and a blanket bit line metal film;

forming a cross point memory array with a parallel bit line and a perpendicular word line; and

forming a memory cell stack at a cross point of the word line and the bit line, wherein the memory cell stack is self-aligned;

wherein the bit line and word line metals are formed from material containing a least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture of one or more of these metals with graphene, for the word line and the bit line to have reduced resistance and use reduced voltage and to improve programming and increase array size as compared to the bit line and the word line being formed.
The method according to claim 9, wherein the blanket word line metal film and a blanket bit line metal film are formed with a half-damascene process.
The method according to claim 9, further comprising forming the bit line and word line from the bit line blanket film and word line blanket film.
The method according to claim 9, wherein the word line and the bit line are formed by etching the cell stack with phase vapor deposition with material containing the least one of tungsten (W) , cobalt (Co) , rhodium (Rh) , ruthenium (Ru) , iridium (Ir) , molybdenum (Mo) , or a mixture with graphene.