WO2022032490A1

WO2022032490A1 - New cell stack with reduced wl and bl resistance for 3d x-point memory to improve program and increase array size

Info

Publication number: WO2022032490A1
Application number: PCT/CN2020/108487
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-08-11
Filing date: 2020-08-11
Publication date: 2022-02-17
Also published as: CN112106202A

Abstract

A cell stack with reduced write line (WL) and bit line (BL) resistance for 3D X-Point Memory improves programming and increases array size. BL and WL are formed by damascene process with Cobalt (Co), Rhodium (Rh), Ruthenium (Ru) self-aligned or with an overlay control requirement. In one embodiment, a Co BL is first formed in the substrate. A Co/C/OTS/C/PCM/C/Nit stack is then deposited. Subsequently, Co WL is etched through stack forming a cross-point memory cell, or a Co replacement gate is formed in a single damascene. WL and BL formed with Co, Rh, Ru were found friendlier to scaling than using current materials like tungsten (W) or copper (Cu). Cell stack height and aspect ratio is effectively reduced due to thinner metal, or metal etching elimination. Thus, WL and BL use reduced voltage as compared to using W. Subarray or tile size is increased accordingly to improve array efficiency.

Description

A NEW CELL STACK WITH REDUCED WL AND BL RESISTANCE FOR 3D X-POINT MEMORY TO IMPROVE PROGRAM AND INCREASE ARRAY SIZE

TECHNICAL FIELD

The present disclosure generally relates to three-dimensional electronic memories, and more particularly, to reducing voltage drop in write or word lines and bit lines, and increasing subarray or tile size to improve array efficiency.

BACKGROUND

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As such, memory density for planar memory cells approaches an upper limit. A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells.

Phase-change memory (PCM) is a non-volatile solid-state memory technology that exploits reversible, thermally-assisted switching of phase-change materials like chalcogenide compounds such as GST (Germanium-Antimony-Tellurium) , between states with different electrical resistance. The fundamental storage unit (the “cell” ) can be programmed into a number of different states, or levels, which exhibit different resistance characteristics. Programmable cell-states can be used to represent different data values, permitting storage of information.

PCM cells are programmed or erased by thermal self heating to induce an amorphous or crystalline state to denote 1 and 0. Programming current is directly proportional to the size and cross-sectional area of the PCM cell. In single-level PCM devices, each cell can be set to one of two states, a “SET” state and a “RESET” state, permitting storage of one bit per cell. In the RESET state, which corresponds to a wholly amorphous state of the phase-change material, the electrical resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase-change material can be transformed into a low-resistance, fully-crystalline state. This low-resistance state provides the SET state of the cell. If the cell is then heated to a high temperature, above the melting point of the phase-change material, the material reverts to the fully-amorphous RESET state on rapid cooling.

In addition, large programming current requirements also lend to large program voltage requirements. Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase-change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes Joule heating of the phase-change material to an appropriate temperature to induce the desired cell-state on cooling. Reading of PCM cells is performed using cell resistance as a metric for cell-state. An applied read voltage causes current to flow through the cell.

This current is dependent on resistance of the cell. Measurement of the cell current therefore provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that application of the read voltage does not disturb the programmed cell state. Cell state detection can then be performed by comparing the resistance metric with predefined reference levels. Programming current (I) is typically in the order of 100-200μA. The voltage drop may be significant if the write or word line (WL) and bit line (BL) in the cell encounters large resistance.

In commercial 3D X-point memory, word lines and bit lines are formed of 20nm/20nm L/Spattern. The memory chip is composed of many small memory arrays (tile) , and is at risk from large voltage drops across word lines and bit lines during program operation. Typically 3D X-point memory, bit lines and word lines are formed of tungsten (W) that has an electrical property of relatively high resistivity. Voltage drops due to word line and bit line resistances will cause memory cells to experience different program currents that may lead to over programming or under programming along the write line and bit line. In addition, tungsten resistivity rapidly increases with smaller critical dimensions or CD due to electron scattering at surfaces and grain boundaries.

Thus there is a need in the art for a memory cell stack that will minimize the write or word line and bit line resistance, and their impact to programing operation to improve the programming window and increase tile size.

SUMMARY

The following summary is included in order to provide a basic understanding of aspects and features of the disclosure. This summary is not an extensive overview and as such it is not intended to particularly identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a summarized format.

In one aspect, a new cell structure for 3D X-Point Memory is presented allowing a reduced programming current and reduced write line and bit line resistance as compared to current state of the art 3D X-Point Memory cell structures. In the present new cell structure, each stack is composed of a perpendicular word line and a bit line. The memory cell stack is self-aligned to the word line and the bit line, or is overlaid with controlled requirements. The word lines and the bit lines are formed using material that contains cobalt (Co) or rhodium (Rh) or ruthenium (Ru) . These materials are good candidates to reduce resistance for several purposes including scaling of the memory array. Compared with tungsten, cobalt, for example, shows less resistivity increase with scaling and has an estimated 40%lower resistivity than tungsten for 20nm wide interconnects.

In another aspect, a method for forming a new cell stack with reduced write lines and bit lines resistance as compared to current state of the art for 3D X-point memory is disclosed. The method includes forming a cross-point memory array with parallel bit lines and perpendicular word lines. The word line and bit line may be formed in two different way depending on the embodiment. In one method embodiment, the word line and the bit line are formed by removing a sacrificial nitride layer that creates a channel and filling the channel with cobalt (Co) or rhodium (Rh) or ruthenium (Ru) . In another method embodiment, the word line and the bit line are formed by etching the cell stack with phase vapor deposition (PVD) cobalt (Co) or rhodium (Rh) or ruthenium (Ru) .

In another aspect, a 3D X-Point Memory Die architecture is disclosed. Quantities of memory arrays (tiles) are separated by small space, typically 20nm in an X-direction and a Y-direction of the array. Cobalt (Co) or rhodium (Rh) or ruthenium (Ru) write lines and bit lines electrically access each memory cell with less resistance as compared to write lines and bit lines made of current state of the art tungsten material.

In yet another aspect, a three-dimensional memory cell structure includes at least one memory cell stack. The memory cell stack has a selector, a phase change memory cell, and a first electrode, a second electrode and a third electrode. The phase change memory cell is disposed between the first and the second electrode, and the selector is disposed between the second and the third electrode. A word line and a bit line are perpendicular to each other and coupled to the memory cell stack. The memory cell stack is self-aligned or overlay controlled with respect to the word line and the bit line. The word line is formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) . The bit line formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) . The word line and the bit line have reduced resistance and use reduced voltage, as compared to being formed from material containing tungsten (W) , to improve programming and increase array size.

In another aspect, a three-dimensional X-Point Memory Die architecture includes a plurality of top memory arrays or tiles containing a first set of phase change memory cells, and a plurality of bottom memory arrays or tiles containing a second set of phase change memory cells. A plurality of bit lines are coupled to the top array and coupled to the bottom array. A plurality of word lines are perpendicular to the bit lines, and comprise a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array. The top array of memory cells are each separated by a first space defined by adjacent phase change memory cell in the top array, and the bottom array of memory cells are each separated by a second space defined by adjacent phase change memory cell in the bottom array. The word lines are formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) , and the bit lines are formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) to electrically access each memory cell.

In accordance with in aspect, a method of forming a three-dimensional memory comprises forming a cross point memory array with a parallel bit line and a perpendicular word line, and forming a memory cell stack at a cross point of the word line and the bit line. The memory cell stack is self-aligned. The bit line and word line are formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) . The word line and the bit line have reduced resistance and also use reduced voltage to improve programming and increase array size as compared to the bit line and the word line being formed from material containing tungsten (W) .

Depending on the embodiment, the method includes forming the word line and the bit line by removing a sacrificial nitride layer to form a channel, and filling the channel with material containing the least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) .

In another embodiment, the method includes forming the word line and the bit line by etching the cell stack with phase vapor deposition with material containing the least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) .

BRIEF DESCRIPTION OF THE DRAWINGS

The foregoing aspects, features and advantages of the present disclosure will be further appreciated when considered with reference to the following description of exemplary embodiments and accompanying drawings, wherein like reference numerals represent like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity.

However, the aspects of the present disclosure are not intended to be limited to the specific terms used.

Fig. 1 is an isometric view of a prior three-dimensional cross point memory.

Figs. 2A, 2B, and 2C are plan views of a section of a three-dimensional cross point memory showing a bottom cell stack deposition, and Fig. 2D is a diagram showing abbreviations for layers in the cell stack.

Figs. 3A and 3B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 2A-2D with bottom cell double patterning and encapsulation layer deposition, respectively.

Figs. 4A and 4B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 3A and 3B showing a gap fill layer and chemical mechanical planarization (CMP) , respectively.

Figs. 5A and 5B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 4A and 4B showing nitride hard mask deposition.

Figs. 6A and 6B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 5A and 5B showing bottom cell word line double patterning to form parallel bottom cell word lines perpendicular to bit lines.

Figs. 7A and 7B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 6A and 6B showing deposition of nitride and oxide encapsulation deposition followed by gap fill.

Figs. 8A and 8B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 7A and 7B showing chemical mechanical planarization (CMP) and wet etching to remove nitride to fill with cobalt to form cobalt replacement word lines.

Fig. 9 is a plan view of the three-dimensional cross point memory in accordance with the embodiment of Figs. 8A and 8B showing a second stack of memory cell deposition and patterning with replacement top cell cobalt bit lines.

Fig. 10 is a plan view of a section of a three-dimensional cross point memory of another embodiment showing a bottom cell stack deposition.

Figs. 11A and 11B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Fig. 10 with bottom cell double patterning and encapsulation layer deposition, respectively.

Figs. 12A and 12B are plan views of the three-dimensional cross point memory in accordance with the embodiment of Figs. 11A and 11B showing a gap fill layer and chemical mechanical planarization (CMP) , respectively.

Figs. 13A and 13B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 12A and 12B showing bottom word line cobalt deposition and double patterning to form parallel bottom cell word lines perpendicular to bit lines.

Figs. 14A and 14B are plan views of the three-dimensional cross point memory in the X-direction and the Y-direction of the memory, respectively, in accordance with the embodiment of Figs. 13A and 13B showing chemical mechanical planarization (CMP) and wet etching to remove nitride to fill with cobalt to form cobalt replacement word lines.

Fig. 15 is a plan view of the three-dimensional cross point memory in accordance with the embodiment of Figs. 14A and 14B showing a second stack of memory cell deposition and patterning with replacement top cell cobalt bit lines.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” and the like, merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer there between, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer there between (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature's relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

The term “substrate” as used herein may refer to any workpiece on which formation or treatment of material layers is desired. Non-limiting examples include silicon, germanium, silica, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, Spinel, silicon on oxide, silicon carbide on oxide, glass, gallium nitride, indium nitride, aluminum nitride, glasses, combinations or alloys thereof, and other solid materials. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpattern. Furthermore, the substrate can include a wide array of semiconductor materials, including but not limited to silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure, or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term “horizontal” as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term “vertical” will refer to a direction perpendicular to the horizontal as previously defined. Terms such as “above” , “below” , “bottom” , “top” , “side” (e.g. sidewall) , “higher” , “lower” , “upper” , “over” , and “under” , are defined with respect to the horizontal plane. The term “on” means there is direct contact between the elements. The term “above” will allow for intervening elements.

As used herein, a material (e.g. a dielectric material or an electrode material) will be considered to be “crystalline” if it exhibits greater than or equal to 30%crystallinity as measured by a technique such as x-ray diffraction (XRD) . Amorphous material is considered non-crystalline.

As used herein, the terms “first, ” “second, ” and other ordinals will be understood to provide differentiation only, rather than imposing any specific spatial or temporal order.

As used herein, the term “oxide” (of an element) will be understood to include additional components besides the element and oxygen, including but not limited to a dopant or alloy. As used herein, the term “nitride” (of an element) will be understood to include additional components besides the element and nitrogen, including but not limited to a dopant or alloy.

As used herein, the term “Damascene” will be understood to mean a Damascene Process. In this process, the underlying silicon oxide insulating layer is patterned with open trenches or channels that the conductor should be located. A thick coating of copper that significantly overfills the trenches is deposited on the insulator, and chemical-mechanical planarization (CMP) is used to remove the copper (known as overburden) that extends above the top of the insulating layer. Copper sunken within the trenches or channels of the insulating layer is not removed and becomes the patterned conductor. Damascene processes generally form and fill a single feature with copper per Damascene stage. Dual-Damascene processes generally form and fill two features with copper at once. So generally, the damascene method involves etching line and via features in the dielectric, a silica-based material, then filling those features with barrier and Cu metal. The excess metal is removed by CMP and the wafer is then processed by an aqueous post-CMP cleaning step.

The present technology is applied to a new cell stack with reduced WL and BL resistance for 3D X-Point Memory to improve program and increase array size, especially for future generation when critical dimensions or CD is scaled further down. In the proposed new cell stack, bit line and word line can be formed by damascene cobalt (Co) , rhodium (Rh) , and ruthenium (Ru) self-alignedly or with tight tolerance overlay control. In one embodiment, cobalt (Co) bit lines are formed in the substrate first. The cell stack is then deposited with a cobalt layer, a first carbon electrode, a selector or ovonic threshold switch, a second carbon electrode, a phase change memory cell, a third carbon electrode, and a nitride layer. The sequence is abbreviated herein as Co/C/OTS/C/PCM/C/Nit stack. Subsequently, a cobalt word line is etched through the stack to form cross point memory cell, or a cobalt replacement gate is formed in single damascene. Word lines and bit lines formed with cobalt, rhodium, and ruthenium where found to be more acceptable to scaling than materials like tungsten or copper. Cell stack height and aspect ratio is effectively reduced due to thinner metal used or elimination of a metal etching altogether for the word line and bit line formation. This feature assists in increase array size. Voltage drop is reduced compared to prior art word lines and bit lines using tungsten (W) . Subarray or tile size is increased accordingly to improve array efficiency. Compared with tungsten, cobalt shows less resistivity increase with scaling and has an estimated 40%lower resistivity than tungsten for 20-nm-wide interconnects. Thus the use of Co, Rh, Ru are good candidates to reduce resistance in word lines and bit lines in 3D X-Point Memory for scaling purposes .

The present technology is applied in the field of three-dimensional memory. A generalized prior example of a three-dimensional (3D) memory is shown in FIG. 1A. In particular, Fig. 1 is an isometric view of a section of three-dimensional cross-point memory. The memory includes a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer of memory cells 5 and second layer of memory cells is a number of word lines 15 extending in the X direction. Above the first layer of memory cells 5 is a number of first bit lines 20 extending along the Y direction, and below the second layer of memory cells is a number of second bit lines 25 extending along the Y direction. Further, as can be seen from the figure, the sequential structure of bit lines -memory cells -word lines -memory cells may be repeated along the Z direction to realize a stacked configuration. In any event, an individual memory cell may be accessed by selectively activating the word line and bit line corresponding to the cell. Reference will be made to X and Y directions utilizing the directional model shown in FIG. 1.

FIG. 1 illustrates the general structure of a 3D X-Point Memory cell, and that terminology is used herein to describe the improvement. The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20 nm /20 nm Line /Space (L/S) pattern, and are formed on a silicon substrate. Moreover, the memory may employ complementary metal-oxide semiconductor (CMOS) technology.

As stated above, issue of voltage drop due to word line and bit line resistance may occur with the memory cells. The present disclosure addresses this issue and provides reducing current and voltage required for the memory cell. Adverting to FIG. 2A is a plane top view of a structure showing forming a cobalt bit line 202 on a substrate 201. A cross-sectional view of FIG. 2A is taken along line A-A and shown in FIG. 2B. FIG. 2C illustrates bottom cell stack deposition. The substrate 201 with the cobalt bit lines 202 has the following layers deposited thereon. Starting from the bottom of the cell stack deposition, deposited on the structure in FIG. 2B is the cobalt bit lines 202 and a cobalt layer also labeled as 202, a first carbon electrode 209, a selector or an ovonic threshold switch 208, a second carbon electrode 207, a phase change memory cell 206, a third carbon electrode 205, and a nitride layer 204.

Layers

204, 304, 501, and 701 referred herein as a nitride layer are shown in FIG. 2D. Examples of such nitride materials include, but are not limited to, metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials. The electrodes can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Moreover, while the features described are particularly advantageous for multi-level cells, these features can also be applied to advantage in single-level cells in some embodiments.

Again, as previously stated the use of the terms first, second and third is to provide differentiation only, rather than imposing any specific spatial or temporal order. The

carbon electrodes

205, 207 and 209 may be interchangeable and the reference to the terms first, second and third are merely used as a reference to describe adjacent elements. The layers shown in FIG. 2C are abbreviated as: Co/C/OTS/C/PCM/C/Nit stack as shown in FIG. 2D. These abbreviations refer to cobalt layer, a first carbon electrode, a selector or ovonic threshold switch, a second carbon electrode, a phase change memory cell, a third carbon electrode, and a nitride layer, respectively. Reference numeral 201 refers to the substrate or an oxide layer. Oxide is also denoted as

reference numerals

401, and 702 herein as shown in FIG. 2D. Reference number 211 refers to a Spin on Dielectric (SOD) process and is synonymous with

gap fill

402, and 703 as shown herein.

FIG. 3A shows

exemplary cell stacks

1, 2, and 3. Each stack is made of several layers as previously described in FIGS. 2A-2D. The cell stacks 1, 2, and 3 are similar in function and composition. For the description of materials disclosed herein, similar reference numerals to common elements in various figures denote similar material and functions of the elements shown and described. Cobalt 202 is within the substrate 201 and in the cell stack as shown in FIG. 3A.

Also shown in FIG. 3A is a bottom cell double patterning to form a parallel bottom cell in electrical contacts with bottom bit lines. In FIG. 3B, shown is an encapsulation layer 304

deposition covering stacks

1, 2, and 3 to protect the exposed phase change memory cell 206 and ovonic threshold switch 208 in each stack. Depending on the implementation the encapsulation may be a nitride encapsulation.

FIG. 4A illustrates a gap fill 402 over the

stacks

1, 2, and 3. Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) 211 or flowable chemical vapor deposition (CVD) oxide. Examples of gap fill materials, include, but are not limited to, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) and lead selenide (PbSe) and Cobalt based compounds and any combination thereof. FIG. 4B illustrates oxide/nitride chemical mechanical planarization (CMP) treatment producing oxide layer 401 to the

stacks

1, 2, and 3. Layer 401 is placed over the encapsulation layer 304. The CMP treatment stops on the carbon electrode 205 as shown in FIG. 4B. Depending on the orientation, carbon electrode 205 may be referred to as the third carbon electrode, or referred to as the first carbon electrode.

FIG. 5A illustrates a nitride hard mask deposition as shown in a X-direction. FIG. 5B illustrates the nitride hard mask in a Y-direction. Again, X and Y directions are given using Figure 1 as a base reference. A nitride hard mask deposition layer 501 is produced. The layer may be nitride based compound as described herein, or any other nitride based compound. The layer 501 is disposed on top of carbon electrode 205. Typically deposition may be accomplished by Chemical vapor deposition (CVD) . In this process a vacuum deposition method is used to produce high quality, high-performance, solid materials. In typical CVD, the wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit.

FIGS. 6A and 6B illustrate bottom cell word line double patterning to form parallel bottom cell write lines perpendicular to bit lines that are in contact with the bottom cell top carbon electrode 205. FIG. 6A shows the bottom word line double patterning in the X-direction and FIG. 6B shows it in the Y-direction. As shown in FIG. 6A phase change memory (PCM) cell 206 and ovonic threshold switch 208 are between carbon electrodes.

Carbon electrodes

205, 207 surround the phase change memory cell 206, and

carbon electrodes

207 and 209 surround the ovonic threshold switch 208.

FIGS. 7A and 7B illustrate deposition of nitride and

oxide encapsulation

701, 702, respectively, followed by gap fill 703 shown in both the x and y directions. Again the nitride is applied to a top referenced carbon electrode, and shown in these figures are denoted as the third carbon electrode 205. The deposition is on top of the nitride hard mask 501.

FIGS. 8A and 8B illustrate oxide chemical mechanical planarization (CMP) is done and stopped on cobalt layer 202 above carbon electrode 205. Wet etching is used to remove nitride to fill with a cobalt compound to form a replacement cobalt word line 801. Depending on the implementation, ammonium hydroxide or hydrogen peroxide may be utilized in the etching process. FIG. 8A illustrates this replacement cobalt word line 801 arrangement in the x-direction. FIG. 8B illustrates the same cobalt word line 801 arrangement in the y-direction. The x and y directions are based on and referred to in FIG. 1.

FIG. 9 illustrates a second stack of memory cell deposition and patterning with the new cell structure described herein with a replacement top cell cobalt (Co) bit lines. Shown is top section 901 and bottom section 903 that relate to embodiments shown in FIGS. 8B and 8A, respectively. Top cell and bottom cell replacement word or write lines separate the two stacks in FIG. 9 as denoted by section 902. The word lines in section 902 are made of the cobalt material 202. Again, depending on the implementation, the word lines may be formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) , and the bit lines may be formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) .

In a second embodiment shown in FIGS. 10-15, three steps that were previously described are eliminated and modifications are made. First, there is no cobalt bit lines formed within the substrate. Second, there is no nitride hard mask deposition required. Third, since there is no nitride hard mask deposition, the step of nitride and oxide encapsulation followed by a gap fill on top of the nitride hard mask deposition is also eliminated. Other than these three exceptions, the previous descriptions also apply to this second embodiment.

The second embodiment also addresses the same issues as the first embodiment and provides reducing current and voltage required for the memory cell. Adverting to FIG. 10 is a plane top view of a structure showing a bottom cell stack deposition. The oxide substrate 201 has the following layers deposited thereon. Starting from the bottom of the cell stack deposition, deposited on the structure in FIG. 10 is a cobalt layer 202, a first carbon electrode 209, a selector or an ovonic threshold switch 208, a second carbon electrode 207, a phase change memory cell 206, a third carbon electrode 205, and a nitride layer 204.

Again, layer 204 is a nitride layer. Examples of such materials include, but are not limited to, metal nitrides such as TiN, TiAlN, TaN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (with and without doping) , reduced metal oxides such as TiOx (x<2 indicates reduction) , metals such as W, Ni, Co, or carbon based materials. The electrodes can be formed of any convenient electrically-conductive material, typically a metallic material (e.g. a pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material such as silicon. Moreover, while the features described are particularly advantageous for multi-level cells, these features can also be applied to advantage in single-level cells in some embodiments.

carbon electrodes

205, 207 and 209 may be interchangeable and the reference to the terms first, second and third are merely used as a reference to describe adjacent elements. The layers shown in FIG. 10 are abbreviated as: Co/C/OTS/C/PCM/C/Nit stack as shown in FIG. 2D. These abbreviations refer to cobalt layer, a first carbon electrode, a selector or ovonic threshold switch, a second carbon electrode, a phase change memory cell, a third carbon electrode, and a nitride layer, respectively. Reference numeral 201 refers to the substrate or an oxide layer. Oxide is also denoted as

reference numerals

gap fill

402, and 703 as shown herein.

FIG. 11A shows

exemplary cell stacks

1, 2, and 3. Each stack is made of several layers as previously described. The cell stacks 1, 2, and 3 are similar in function and composition. For the description of materials disclosed herein, similar reference numerals to common elements in various figures denote similar material and functions of the elements shown and described. Cobalt 202 is not within the substrate 201 and is in the cell stack as shown in FIG. 11A.

Also shown in FIG. 1A is a bottom cell double patterning to form a parallel bottom cell in electrical contacts with bottom bit lines. In FIG. 11B, shown is an encapsulation layer 304

deposition covering stacks

FIG. 12A illustrates a gap fill 402 over the

stacks

1, 2, and 3. Gap fill may be obtained through atomic layer deposition oxide, Spin on Dielectric (SOD) 211 or flowable chemical vapor deposition (CVD) oxide. Again, examples of gap fill materials, include, but are not limited to, gallium arsenide (GaAs) , indium gallium arsenide (InGaAs) , gallium nitride (GaN) , aluminum nitride (AlN) , cadmium sulfide (CdS) , cadmium selenide (CdSe) , cadmium tellurite (CdTe) , zinc sulfide (ZnS) , lead sulfide (PbS) and lead selenide (PbSe) and Cobalt based compounds and any combination thereof. FIG. 12B illustrates oxide/nitride chemical mechanical planarization (CMP) treatment producing oxide layer 401 to the

stacks

1, 2, and 3. Layer 401 is placed over the encapsulation layer 304. The CMP treatment stops on the carbon electrode 205 as shown in FIG. 12B. Depending on the orientation, carbon electrode 205 may be referred to as the third carbon electrode, or referred to as the first carbon electrode.

FIGS. 13A and 13B illustrate bottom cell word line cobalt deposition and double patterning to form parallel bottom cell write lines perpendicular to bit lines that are in contact with the bottom cell top carbon electrode 205. Again, there is no nitride hard mask deposition in this second embodiment. FIG. 13A shows the bottom word line double patterning in the X-direction and FIG. 13B shows it in the Y-direction. As shown in FIG. 13A and 13B phase change memory (PCM) cell 206 and ovonic threshold switch 208 are between carbon electrodes.

Carbon electrodes

205, 207 surround the phase change memory cell 206, and

carbon electrodes

207 and 209 surround the ovonic threshold switch 208.

FIGS. 14A and 14B illustrate oxide chemical mechanical planarization (CMP) is done and stopped on cobalt layer 202 above carbon electrode 205. Wet etching is used to remove nitride to fill with a cobalt compound to form a replacement cobalt word line 801. Depending on the implementation, ammonium hydroxide or hydrogen peroxide may be utilized in the etching process. FIG. 14A illustrates this replacement cobalt word line 801 arrangement in the x-direction. FIG. 14B illustrates the same cobalt word line 801 arrangement in the y-direction. The x and y directions are based on and referred to in FIG. 1.

FIG. 15 illustrates a second stack of memory cell deposition and patterning with the new cell structure described herein with a replacement top cell cobalt (Co) bit lines. Shown is top section 1501 and bottom section 1503 that relate to embodiments shown in FIGS. 14B and 14A, respectively. Top cell and bottom cell replacement word or write lines separate the two stacks in FIG. 15 as denoted by section 1502. The word lines in section 1502 are made of the cobalt material 202. Again, depending on the implementation, the word lines may be formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) , and the bit lines may also be formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) .

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. As an example, the preceding operations do not have to be performed in the precise order described above. Rather, various steps can be handled in a different order, such as reversed, or simultaneously. Steps can also be omitted unless otherwise stated. In addition, the provision of the examples described herein, as well as clauses phrased as "such as, " "including" and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, the examples are intended to illustrate only one of many possible embodiments. Further, the same reference numbers in different drawings may identify the same or similar elements.

Although the present disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

A three-dimensional memory cell structure, comprising:

at least one memory cell stack, the memory cell stack having a selector, a phase change memory cell, and a first electrode, a second electrode and a third electrode; the phase change memory cell disposed between the first and the second electrode, and the selector disposed between the second and the third electrode;

a word line and a bit line perpendicular to each other and coupled to the memory cell stack, wherein the memory cell stack is self-aligned with respect to the word line and the bit line;

the word line formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) ;

the bit line formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) ; and

wherein, the word line and the bit line have reduced resistance and use reduced voltage, as compared to being formed from material containing tungsten (W) , to improve programming and increase array size.
The three-dimensional memory according to claim 1, wherein the selector is an ovonic threshold switch (OTS) , and the first, the second, and the third electrodes are all carbon electrodes forming a first, a second, and a third carbon electrodes.
The three-dimensional memory according to claim 2, further comprising a substrate and wherein a cobalt (Co) bit line is first formed in the substrate.
The three-dimensional memory according to claim 3, wherein the cell stack is deposited on the substrate with the cobalt (Co) bit line, and the cell stack contains layers in a sequence of a cobalt material layer/the third carbon electrode/the ovonic threshold switch/the second carbon electrode/the phase change memory cell/the first carbon electrode/anitride material layer or the sequence of Co/C/OTS/C/PCM/C/Nit.
The three-dimension memory according to claim 4, wherein a cobalt (Co) write line is etched through the stack to form a cross point memory cell, or a cobalt (Co) replacement gate in a single damascene.
The three-dimensional memory according to claim 1, wherein the selector is an ovonic threshold switch (OTS) , and the first, the second, and the third electrodes are all carbon electrodes forming a first, a second, and a third carbon electrodes, and the cell stack contains layers in a sequence of a cobalt material layer/the third carbon electrode/the ovonic threshold switch/the second carbon electrode/the phase change memory cell/the first carbon electrode/anitride material layer or the sequence of Co/C/OTS/C/PCM/C/Nit.
The three-dimensional memory according to claim 1, wherein the cell stack further includes a nitride layer, an oxide layer, a gap fill layer, and in an absence of a tungsten layer.
A three-dimensional X-Point Memory Die architecture, comprising:

a plurality of top memory arrays or tiles containing a first set of phase change memory cells;

a plurality of bottom memory arrays or tiles containing a second set of phase change memory cells;

a plurality of bit lines coupled to the top array and coupled to the bottom array;

a plurality of word lines perpendicular to the bit lines, and comprising a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array;

the top array of memory cells are each separated by a first space defined by adjacent phase change memory cell in the top array, and the bottom array of memory cells are each separated by a second space defined by adjacent phase change memory cell in the bottom array, and

wherein, the word lines are formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) , and the bit lines are formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) to electrically access each memory cell.
The three-dimensional architecture according to claim 8, wherein the top and the bottom word lines are coupled thereto.
The three-dimensional architecture, wherein the first space and second space are about 20nm in an X-direction and about 20nm in a Y-direction.
A method of forming a three-dimensional memory comprising:

forming a cross point memory array with a parallel bit line and a perpendicular word line;

forming a memory cell stack at a cross point of the word line and the bit line, wherein the memory cell stack is self-aligned; and

wherein the bit line and word line are formed from material containing a least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) for the word line and the bit line to have reduced resistance and use reduced voltage and to improve programming and increase array size as compared to the bit line and the word line being formed from material containing tungsten (W) .
The method according to claim 11, wherein the word line and the bit line are formed by removing a sacrificial nitride layer to form a channel, and filling the channel with material containing the least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) .
The method according to claim 11, wherein the word line and the bit line are formed by etching the cell stack with phase vapor deposition with material containing the least one of cobalt (Co) , rhodium (Rh) , or ruthenium (Ru) .
The method according to claim 12, further comprising,

forming a cobalt bottom bit line on a substrate;

forming a bottom cell stack deposition having layers of a cobalt material, a first carbon electrode, an ovonic threshold switch, a second carbon electrode, a phase change memory, a third carbon electrode and a nitride layer;

using bottom cell double patterning to form a parallel bottom cell in electrical contact with the cobalt bottom bit line;

applying a nitride encapsulation layer deposition to overlay the cell stack;

applying a gap fill to the cell stack with an atomic layer deposition oxide, a spin on dielectric or a flowable chemical vapor deposition oxide;

applying chemical mechanical planarization with an oxide and/or nitride compound to the cell stack stopping on the third carbon electrode next to the nitride layer;

applying a nitride hard mask deposition to the nitride layer;

using bottom word line double patterning to form a parallel bottom cell word line perpendicular to the bit line in contact with the bottom cell’s top carbon electrode that is the third carbon electrode;

applying to the bottom cell stack deposition of a nitride layer and an oxide layer encapsulation followed by applying a gap fill to the encapsulation;

applying chemical mechanical planarization with an oxide compound to the cell stack stopping on the nitride layer to fill with cobalt to form a replacement cobalt word line; and

applying a second stack of memory cell deposition and patterning with a replacement top cell cobalt bit line.
The method according to claim 13, further comprising,

forming a bottom cell stack deposition having layers of a cobalt material, a first carbon electrode, an ovonic threshold switch, a second carbon electrode, a phase change memory, a third carbon electrode and a nitride layer;

using bottom cell double patterning to form a parallel bottom cell in electrical contact with the cobalt bottom bit line;

applying a nitride encapsulation layer deposition to overlay the cell stack;

applying a gap fill to the cell stack with an atomic layer deposition oxide, a spin on dielectric or a flowable chemical vapor deposition oxide;

applying chemical mechanical planarization with an oxide and/or nitride compound to the cell stack stopping on the third carbon electrode next to the nitride layer;

using bottom word line cobalt deposition and double patterning to form a parallel bottom cell word line perpendicular to the bit line in contact with the bottom cell’s top carbon electrode that is the third carbon electrode;

applying chemical mechanical planarization with an oxide compound to the cell stack stopping on the nitride layer and wet etching to remove the nitride layer to fill with cobalt to form a replacement cobalt word line; and

applying a second stack of memory cell deposition and patterning with a replacement top cell cobalt bit line.