CN112470283B

CN112470283B - Method for reducing thermal cross-talk in a 3D cross-point memory array

Info

Publication number: CN112470283B
Application number: CN202080002909.4A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2024-01-16
Anticipated expiration: 2040-10-10
Also published as: CN112470283A; WO2022073222A1

Abstract

Systems, methods, and apparatus are described that are capable of reducing the amount of thermal crosstalk between cells in a three-dimensional array of memory cells through the use of laminates, which in turn allow for smaller scale fabrication of the memory cells. In the disclosed methods, systems, and devices, a sacrificial material is used to fill the gaps between adjacent memory cells, and is later removed to form the air gaps. These air gaps are very efficient for reducing thermal cross-talk between adjacent cells. It allows scaling to smaller memory cells and pitches with less impact from thermal effects of adjacent cell programming. In addition, it reduces thermal cross-talk between adjacent 3D cross-point memory cells, has good mechanical support during cell fabrication, and improves the scalability of the 3D cross-point memory.

Description

Method for reducing thermal cross-talk in a 3D cross-point memory array

Technical Field

The present disclosure relates generally to three-dimensional electronic memories. More particularly, the present disclosure relates to the use of lamination, wet etching, oxide, and the formation of air pockets in the geometry of a three-dimensional memory array to increase certain characteristics or attributes of the memory array or to reduce undesirable characteristics in the memory array.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and expensive. Thus, the memory density of the planar memory cell approaches the upper limit. A three-dimensional (3D) memory architecture may address density limitations of planar memory cells.

Phase Change Memory (PCM) cells are a non-volatile solid state memory technology that utilizes reversible thermally assisted switching of phase change materials, such as chalcogenide compounds, e.g., GST (germanium antimony tellurium), between states having different resistances. The basic memory unit ("cell") can be programmed to a plurality of different states or levels exhibiting different resistance characteristics. The programmable cell states may be used to represent different data values, allowing storage of information.

PCM cells are programmed or erased by self-heating to induce an amorphous or crystalline state to represent 1 and 0. The programming current is directly proportional to the size and cross-sectional area of the PCM cell. In a single-stage PCM device, each cell may be SET to one of two states, a "SET" state and a "RESET" state, allowing one bit to be stored per cell. In the RESET state (which corresponds to the fully amorphous state of the phase change material), the resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase change material can be transformed to a low resistance, fully crystalline state. This low resistance state provides the SET state of the cell. If the cell is subsequently heated to a high temperature above the melting point of the phase change material, the material reverts to a fully amorphous RESET state upon rapid cooling.

Due to the nature of self-heating, cross-talk occurs when programming adjacent cells. Crosstalk is the interference between signals. As process technology scales, the spacing between adjacent interconnects shrinks. Switching on one signal affects the other signal. In the worst case, this can cause a change in the value of another cell, or it can delay the signal transition, affecting timing. This is classified as a signal integrity problem.

In addition, large programming current requirements also cause large programming voltage requirements due to IR drop (ir=voltage=current x resistance). Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes the phase change material to joule heat to an appropriate temperature to induce the desired cell state upon cooling. Reading of PCM cells is performed using cell resistance as a measure of the cell state. The applied read voltage causes a current to flow through the cell, which depends on the resistance of the cell. The measurement of the cell current thus provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that the application of the read voltage does not disturb the programmed cell state. Cell state detection may then be performed by comparing the resistance metric to a predefined reference level. The programming current (I) is typically on the order of 100-200 μA. The voltage drop can be significant if the Word Line (WL) and bit line (class B) in the cell encounter large resistances.

Thus, a need exists to reduce the thermal cross-talk between programming current and Phase Change Memory (PCM) cells.

Disclosure of Invention

In creating the techniques of the present invention, it has been recognized that while three-dimensional (3D or 3-D) memory architectures can address the density limitations of planar memory cells, 3D configuration presents new technical challenges. Other technical problems may arise as the pursuit of the desired features of 3D memory architecture (e.g., increased density of 3D cells, or reduced manufacturing size of cells).

One example of such a problem is thermal cross-talk between cells. Thermal cross-talk may occur when heat generated from one point or cell within a 3D cell array is transferred to an adjacent cell at another point or cell. During operation of the 3D memory architecture, heat generated from one cell can disrupt the normal or desired operation of the cell. The problem due to thermal cross-talk between cells becomes more and more pronounced as the size of the cells decreases. Due to the smaller intra-cell distance, smaller spacing or scaling when creating a 3D memory architecture increases the amount or speed of heat transfer between one cell and another. The ability to scale to smaller sizes while still having a functional 3D memory array is compromised due to thermal cross-talk.

Thus, there is a need for methods, systems, and apparatus that overcome the conventional methods of creating 3D memory arrays and allow for scaling of 3D memory arrays while making them operational despite thermal crosstalk.

Methods, systems, and apparatus are shown and described for filling gaps between adjacent memory cells using sacrificial materials. The sacrificial material is later removed to form the air gap. These air gaps are very efficient for reducing thermal cross-talk between adjacent cells. It allows scaling to smaller memory cells and pitches with less impact from thermal effects of adjacent cell programming. In addition, it reduces thermal cross-talk between adjacent 3D cross-point memory cells, provides good mechanical support during cell fabrication, and improves the scalability of the 3D cross-point memory.

In some exemplary embodiments, the electrodes and/or memory cells may be arranged vertically, while in other exemplary embodiments, the electrodes and/or memory cells may be arranged horizontally. In some examples, a combination of orientations is possible.

In one aspect, the pillar memory cells are separated from each other by an air gap in both the X and Y directions. In another aspect, a method for forming a 3D cross point memory cell array includes: forming parallel memory cell lines, protecting the memory cell lines with an encapsulation layer, filling gaps between the memory cell lines with a sacrificial film material, performing vertical line patterning to form isolated memory cell pillars, removing the sacrificial material to form air gaps, and forming air gaps in both the X and Y directions with a non-conformal gap filler. Yet another further aspect includes a method for forming a 3D cross-point memory cell array, comprising: forming parallel memory cell lines, protecting the memory cell lines with an encapsulation layer, forming air gaps in one direction with non-conformal gap filler, performing vertical line patterning to form isolated memory cell pillars, and removing sacrificial material to form the air gaps; and forming an air gap in both the X and Y directions with a non-conformal gap filler.

In one embodiment of the present technology, a three-dimensional memory includes: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer three-dimensionally and at least partially encapsulating the first memory cell, the second memory cell, and the electrode such that the first memory cell and the second memory cell are exposed on at least one surface; and an air gap residing between the first storage unit and the second storage unit.

Other embodiments of the present technology may include, for example, any combination of the following: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer three-dimensionally and at least partially encapsulating the first memory cell, the second memory cell, and the electrode; configuring the first and second memory cells to be exposed on at least one surface; depositing a first layer using a chemical vapor deposition method; depositing a first layer using an atomic deposition method; a second layer at least partially and three-dimensionally surrounding the first layer; a plurality of additional layers, wherein the plurality of layers fully occupy the intra-cell space; constructing the first layer, the second layer, or the additional layer from a dielectric material; selecting the dielectric material includes, but is not limited to, selecting the dielectric material from: a nitride layer (NIT), an aC or electrode layer, a phase change material, an ovonic threshold switch material (OTS), or tungsten (W), and a group comprising oxynitride, a phase change material, an ovonic threshold material, tungsten, nanoporous silicon, hydrosilicates (HSQ), teflon-AF (polytetrafluoroethylene or PTFE), silicon oxyfluoride (FSG), lead zirconate titanate (PZT), silicon nitride, tantalum pentoxide, aluminum oxide, zirconium dioxide, hafnium dioxide, and any combination thereof; constructing the first layer and the second layer from different materials; the first layer and the second layer are comprised of a material selected to minimize the heat reflection value.

For example, other embodiments of the invention may include methods that may include, for example, any combination of the following: providing a first storage unit; providing a second storage unit; providing an electrode electrically connecting the first memory cell and the second memory cell; creating a first layer that encapsulates the first memory cell, the second memory cell, and the electrode in three dimensions; exposing the first and second memory cells on at least one surface; creating a second layer that at least partially and three-dimensionally surrounds the first layer; creating a plurality of layers such that the plurality of layers partially occupy the intra-cell space; creating an air gap encapsulated by at least one layer; creating an air gap residing in the intra-cell space; removing material between the intra-cell spaces beyond the top of the first storage cell or the second storage cell; an electrode is added substantially on the surface exposed by removing material above the top of the first or second memory cell.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considered with reference to the following description of exemplary embodiments and the accompanying drawings in which like reference numerals denote like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

Fig. 1 is an isometric view of a portion of a prior art three-dimensional cross-point memory.

Fig. 2 is a plan view of a portion of a prior art three-dimensional cross-point memory.

Fig. 3A, 3B, and 3C are cross-sectional views of portions of a three-dimensional cross-point memory and an energy grid created by the memory of an embodiment.

Fig. 4 is a graph showing a relationship between a disturb current and a resistance of a memory cell.

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sections of a three-dimensional cross-point memory according to an embodiment of the present invention.

Fig. 6 depicts a method according to an exemplary embodiment of the present disclosure.

Fig. 7A, 7B, 7C-1, 7C-2, 7D, 7E-1, 7E-2, 7E-3, and 7F are cross-sections of a three-dimensional cross-point memory according to an embodiment of the invention.

Fig. 8 depicts a method according to an exemplary embodiment of the present disclosure.

Detailed Description

The present disclosure addresses the challenges and problems associated with existing and current methods, systems, and devices. Among other things, the use of lamination, wet etching, oxide, and changing the shape of specific layers in the geometry of a three-dimensional memory array (i.e., current sensitive layers in a programmable current storage cell) to increase certain characteristics or properties of the memory cell or to reduce undesirable characteristics in the memory array is disclosed. Embodiments and examples illustrating the principles of the present disclosure are shown herein. The present disclosure is not limited in any way to these embodiments and examples, which are presented merely to explain the underlying principles. Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be used in a variety of other applications.

Note that reference in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., merely indicate that the described embodiment may include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, terms may be understood, at least in part, through use of context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending at least in part on the context. Similarly, terms such as "a," "an," or "the" may again be understood as conveying singular uses or conveying plural uses, depending at least in part on the context.

It should be readily understood that the meanings of "on," "above," and "above" in this disclosure are to be interpreted in the broadest manner so that "on" not only means "directly on" but also includes the meaning of "on (with intermediate features or layers between) something, and" over "or" above "not only means" over or above "something, but also includes the meaning of" over or above (without intermediate features or layers between) "that is, directly on" something.

Furthermore, spatially relative terms (e.g., "below," "under," "lower," "over," "upper," and the like) may be used herein to simplify the description so as to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "substrate" as used herein may refer to any workpiece upon which it is desired to form or process a layer of material. Non-limiting examples include silicon, germanium, silicon dioxide, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, spinel, silicon oxide, silicon carbide oxide, glass, gallium nitride, indium nitride, aluminum nitride, glass, combinations or alloys thereof, and other solid materials. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials including, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layer may extend over the entire base layer or superstructure, or may have a smaller extent than the base layer or superstructure. Furthermore, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layers may be located between any pair of horizontal planes between or at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, may include one or more layers in the substrate, and/or may have one or more layers on, above, and/or below the substrate. The layers may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term "horizontal" as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term "vertical" will refer to a direction perpendicular to the horizontal as previously defined. Terms such as "above," "below," "bottom," "top," "side" (e.g., sidewall), "upper," "lower," "upper," "above," and "below" are defined with respect to a horizontal plane. The term "on …" indicates that there is direct contact between the elements. The term "above …" will allow for intermediate elements.

As used herein, a material (e.g., a dielectric material or an electrode material) will be considered "crystalline" if the material exhibits greater than or equal to 30% crystallinity as measured by techniques such as x-ray diffraction (XRD). Amorphous materials are considered amorphous.

As used herein, the terms "first," "second," and other ordinal terms will be understood to provide just a distinction, not to impose any particular spatial or temporal order.

As used herein, the term "oxide" of an element will be understood to include additional components in addition to the element and oxygen, including but not limited to dopants or alloys. As used herein, the term "nitride" of an element will be understood to include additional components in addition to the element and nitrogen, including but not limited to dopants or alloys.

Heat transfer occurs through three main physical phenomena of convection, conduction and radiation. Radiation is a method of energy transfer that does not rely on any contact between the heat source and the heated object. Conduction, on the other hand, is the transfer of heat between substances in direct contact with each other. The conductivity between objects in contact with each other depends on the specific physical characteristics of these objects. For example, conduction through an object depends on the thermal resistance of the material from which the object is made. In an electrical circuit, heat transfer may occur through any such phenomenon.

Conduction can also be conceptualized as occurring through phonons (phonons). Phonons are collective excitations in a periodic elastic arrangement of matter. Phonons are quasi-particles that can represent the vibrational characteristics of a material or various vibrational modes of an elastic material, and also describe interactions between interacting particles of an elastic material. The heat in the dielectric material and the semiconductor is transferred mainly by phonons. Depending on the embodiment, the dielectric material may include, but is not limited to, oxynitride, phase change material, ovonic threshold material, tungsten, nanoporous silicon, hydrosilicates (HSQ), teflon-AF (polytetrafluoroethylene or PTFE), silicon oxyfluoride (FSG), lead zirconate titanate (PZT), silicon nitride, tantalum pentoxide, aluminum oxide, zirconium dioxide, hafnium dioxide, and any combination thereof

When the object is composed of more than one material, the overall thermal resistance of the material may be considered to be composed of the thermal resistances of the constituent materials. However, the presence of more than one material in the system or object creates a thermal boundary resistance between these materials. Phonons may also undergo scattering in the material by interaction with defects, other phonons, grain boundaries, different isotopes in the material, and various other physical reasons. A temperature discontinuity may occur in the region of the interface between two materials as heat passes through the interface between the two materials (i.e., as phonons move from one material to the other). Thermal resistance boundaries are also known as interfacial thermal resistance or Kapitza resistance, which is a measure of the resistance of an interface to heat flow. Thermal resistance boundaries are also defined as the ratio of the temperature discontinuity at an interface to the heat flux flowing through the interface and are caused by strong phonon reflection as phonons attempt to pass through the interface of one material with another. When phonons move from one material to another (such as, for example, from material a to material B), a portion of the phonon energy is reflected back to material a (i.e., reflected) and some of the energy is conducted to material B (i.e., conducted).

By selecting the materials that make up the object, or by creating additional boundaries through which phonons must pass, a higher thermal resistance boundary can be designed. The higher thermal resistance boundary may slow the rate at which heat is transferred by conduction. In addition, by having several materials in the proper configuration, many boundaries can be created through which phonons must pass.

In addition to increasing the thermal boundary between the surfaces, the closed air gap between the two cells may also increase thermal resistance. This is because energy must be emitted from the layer and radiated into the air layer and then re-radiated from the air layer to the second boundary in order to be transferred from one cell to another. In addition, the air itself (which occupies a volume) has a specific heat value, which allows the air to absorb heat before starting to re-transmit it to the second boundary. Properties such as attenuation of thermal resistance due to an increase in air thickness can be observed. In addition, the emissivity of the arrangement can also be designed by varying the thickness of the air gap.

The technology of the present invention relates to solving the problems associated with heat transfer in three-dimensional memories. A general example of a three-dimensional (3D) memory is shown in fig. 1. Specifically, FIG. 1 is an isometric view of a portion of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first-layer memory cells 5 and the second-layer memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. Above the first-layer memory cells 5 in the depth (Z) direction are a plurality of first bit lines 20 extending in the vertical (Y) direction, and below the second-layer memory cells 10 are a plurality of second bit lines 25 extending in the Y direction.

As also shown in fig. 1, the sequential structure of the bit lines, memory cells, word lines, memory cells may be repeated in the Z-direction to create a stacked configuration. In the example of fig. 1, the first layer stack may include the first layer memory cells 5, the bit lines 20, and the word lines 15, and the second layer stack may include the second layer memory cells 10, the bit lines 25, and the word lines 15. Thus, although the first tier memory cells 5 and the second tier memory cells 10 each have their respective set of bit lines 20 and 25, the first tier memory cells 5 and the second tier memory cells 10 may share the same set of word lines 15. Although the example of fig. 1 shows a 4-layer stacked configuration, in other examples, the stacked configuration may include any number of memory layers and other elements. In any event, the individual memory cells in the structure can be accessed by selectively activating the word line and bit line corresponding to the cell.

To selectively activate the word lines and bit lines, the memory includes a word line decoder and a bit line decoder (not shown). A word line decoder is coupled to the word lines through word line contacts (not shown) and is used to decode word line addresses so that a particular word line is activated when addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts (not shown) and is used to decode the bit line addresses so that a particular bit line is activated when addressed. Thus, the stacked configuration of the memory may also include bit line contacts and decoders, and word line contacts and decoders for selectively activating the bit lines and word lines in the stack. For example, the stacked configuration may be arranged as an array of elements, where each array includes a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders. The positioning of the word line decoders and contacts, and the bit line decoders and contacts, is shown and further discussed with reference to fig. 2.

Fig. 2 is a plan view of a portion of a three-dimensional cross-point memory of a prior configuration. The figure depicts the portion as viewed in the Z (depth) direction. In this example, the stacked configuration is a 2-layer stack. The stacked configuration includes multiple arrays of memory cells, including two top cell arrays 60 and 61 and two bottom cell arrays 65 and 66. Although individual memory cells are not shown in fig. 2, they are shown by fig. 1, for example, in a top array, the memory cells may be arranged as the first tier memory cells 5 shown in fig. 1, and in a bottom array, the memory cells may be arranged as the second tier memory cells 10 shown in fig. 1.

The portion includes word lines and bit lines corresponding to the top and bottom cells, word line and bit line contacts, and word line and bit line decoders. As shown, a plurality of word lines (e.g., word line 30) extend in the X (horizontal) direction and correspond to both the top and bottom cells. The portion also includes a plurality of top cell bit lines (e.g., bit lines 35) extending in the Y (vertical) direction and corresponding to the top cell array 60 of memory cells, and a plurality of bottom cell bit lines (e.g., bit lines 40) extending in the vertical direction and corresponding to the bottom cell array 65 of memory cells. The word lines, top cell bit lines, and bottom cell bit lines are typically formed of a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. In addition, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

The word lines in fig. 2 are horizontally aligned for a given cell array. For example, as shown, the word lines of the cell arrays 60, 61, 65, and 66 are all horizontally aligned with each other in the X direction. Each of these word lines is shown extending across the entire width of the respective cell array. The top cell bit line of a given top cell array or the bottom cell bit line of a given bottom cell array is vertically aligned. For example, top cell bit line 35 is vertically aligned in the Y-direction and bottom cell bit line 40 is vertically aligned in the Y-direction. The top cell bit lines of the top cell array and the bottom cell bit lines of the overlapping bottom cell array (e.g., top cell bit line 35 and bottom cell bit line 40) are also horizontally aligned with each other, although they are shown slightly offset in fig. 2 to clearly show the two layers. Each of these bit lines is shown as extending across the entire length of the respective cell array.

The memory portion of fig. 2 includes a word line contact region 45, a top cell bit line contact region 50, and a bottom cell bit line contact region 55. Word line contact region 45 is elongated in a vertical direction, while top cell bit line contact region 50 and bottom cell contact region 55 are elongated in a horizontal direction. The word line contact region 45 includes a plurality of word line contacts (e.g., contact 45 a), which are shown as points surrounded by the word line contact region 45. The top bitline contact region 50 includes a plurality of wordline contacts (e.g., contacts 50 a) that are shown as points surrounded by the top cell bitline contact region 50. The bottom cell bit line contact region 55 includes a plurality of bottom cell bit line contacts (e.g., contacts 55 a) that are considered points surrounded by the bottom cell bit line contact region 55.

The word line contacts and the bit line contacts are connected to the middle portions of the respective word lines and bit lines. Thus, as shown, word line contact region 45 is located in the horizontal middle of word line 40, bottom cell bit line contact region 55 is located in the vertical middle of bottom cell bit line 40, and top cell bit line contact region 50 is located in the vertical middle of top cell bit line 35. Since the word lines of a given cell array are aligned horizontally, the word line contacts of the given cell array are also substantially aligned in the horizontal direction. Similarly, because the bit lines of a given cell array are vertically aligned, the bit line contacts of a given cell array are also substantially aligned in the vertical direction.

The word line contact region 45 also includes a plurality of word line decoders (not shown). The word line decoder generally conforms to the word line contact area and extends generally in a vertical direction. The word line decoder is coupled to the word line through a word line contact. The top cell bit line contact area 50 also includes a plurality of top cell bit line decoders (not shown). The top cell bit line decoder generally conforms to the top cell bit line contact area 50 and extends generally in a horizontal direction. The top cell bit line decoder is coupled to the top cell bit line through a top cell bit line contact. The bottom cell bit line contact area 55 also includes a plurality of bottom cell bit line decoders (not shown). The bottom cell bit line decoder generally conforms to the bottom cell bit line contact area 55 and extends generally in a horizontal direction. The bottom cell bit line decoder is coupled to the bottom cell bit line through a bottom cell bit line contact.

As can be seen from fig. 1, the prior art memory does not contain any material for preventing heat transfer between one cell and the next. Methods and systems are described below that can prevent heat transfer between memory cells without interfering with memory operation.

Referring to fig. 3A, 3B, and 3C, thermal crosstalk can be observed between active or disturbing cells through which current is transferred and inactive or disturbed cells. Although fig. 3A, 3B, and 3C are shown in two dimensions, they represent physical phenomena occurring in three dimensions.

Fig. 3A shows an active unit 305 (also referred to as a jammer unit 305) and an inactive or victim unit 310, wherein the distance between the 3D units is approximately 90 nanometers depending on the implementation. During normal operation of the memory cell, the disrupting unit 305 generates heat when current passes through the disrupting unit 305. The heat generated by the disrupting unit 305 is represented by field 315. The field 315 may represent a gradient or distribution of temperature. That is, the field 315 may represent a particular temperature at a particular physical space by mapping the space to a color that represents the temperature of the space. Alternatively, the field 315 may also be depicted by the proximity or density of lines to represent higher or lower temperatures at a particular region. Although field 315 is viewed in two dimensions in fig. 3A, field 315 may be three-dimensional and extend outward from within disturbing cell 305 to the space surrounding cell 305. As can be seen in fig. 3A, heat generated from the scrambling of scrambling unit 305 is conducted across intra-cell gap 320 to disturbed unit 310.

Fig. 3B is 45 nm anisotropic visualization of heat transfer and temperature gradients generated by the disrupting elements. Fig. 3B shows the 3D cell structure scaled to a smaller pitch than fig. 3A. The intra-cell distance between the scrambling unit and the victim unit is reduced compared to fig. 3A, and in turn, both the heat transferred to the victim unit and the temperature of the victim unit are increased. Thus, the reduced cell pitch and the increase in thermal effects on the victim cell (e.g., victim cell 330) affect the operational properties of the victim cell 340. The field 350 may represent a particular temperature at a particular physical space if the particular physical space is mapped to a color gradient. As shown in fig. 3B, scrambling unit 330 affects victim unit 340 differently at different locations of victim unit 340. In fig. 3B, the victim unit 340 has a higher heat at one end of the unit than the other. Such unequal distribution of temperature may affect the normal operation of the disturbed cell 340. For example, the expected resistance of the victim unit 340 may not be equal throughout the victim unit due to the heat.

Fig. 3C is a 45 nm isotropic visualization of heat transfer and temperature gradient generated by the disrupting elements. An isotropic view is a view that treats all directions equally. Isotropic heat transfer occurs when heat is transferred in all directions at the same rate.

As can be seen from fig. 3A-3C, as the intra-cell distance decreases, more heat is transferred between cells. Further complicating this problem in three-dimensional memories, because the memory is stacked one on top of the other, the surface area and space from which heat is dissipated is reduced compared to conventional generally two-dimensional memories, in which heat can be dissipated to the surrounding environment at a faster rate. For example, compared to a planar memory configuration, heat will not be quickly and efficiently removed from the intermediate memory layer of the three-dimensional memory. In addition, heat moving from one cell in the three-dimensional memory will propagate in all directions, heating all nearby cells.

Fig. 4 is a visual representation between the amount of current passing through a scrambling unit (e.g., scrambling unit 405) and the resistance of a victim unit (e.g., victim unit 410). Fig. 4 also shows a first word line 415, a second word line 420, a first bit line 425, and a second bit line 430. The current may pass through the word line and bit line, such as reset pulse 435. As can be seen from fig. 4, the disturbed cell resistance varies as a function of the current in the disturbed cell. The varying resistance of the victim unit may prevent the normal operation of the victim unit. Fig. 4 shows that the resistance of the victim cell can change by an order of magnitude of 10 based on the increased current within the victim cell. The change in resistance of the victim unit (e.g., victim unit 410) occurs at least in part due to thermal energy generated by the jammer unit (e.g., jammer unit 405).

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sectional views of a three-dimensional cross-point memory according to an embodiment of the present invention.

Fig. 5A illustrates a memory cell formed by deposition or stacking of materials. As can be seen in fig. 5A, cells 510 and 520 are formed of similar materials and thus form parallel lines within the cell stack when viewed in two dimensions. Although not shown in fig. 5A, other components (e.g., those described above or known in the art) or in combination with the cells may be included in various configurations to implement an operable 3D cross-point memory. The cells 510 and 520 may be created or stacked on an electrode (e.g., electrode 501). The units 510 and 520 may be made of various materials or elements, such as W, a-C, ovonic Threshold Switches (OTS) or PCM. For example, the units 510 and 520 may be composed of several layers, such as layers 502, 503, 504, 505, and 506, for example, which in turn may be made of elements such as W, a-C, ovonic Threshold Switches (OTS), or PCM. Fig. 5A illustrates the formation of a first thin NiTi (NIT) (or oxynitride) encapsulation layer around the memory stack illustrated in fig. 5A. NIT is a commercially available alloy such as, for example, NIT135. Any suitable material may be used to form the first layer 530. The first layer 530 may also be made of any suitable dielectric material. The dielectric material is selected to ensure that current in the memory (e.g., cells 510 and 520) is not carried to undesired paths outside those cells. Forming the first layer around the memory stack may be achieved by a conformal coating technique. Conformal coating techniques provide technical advantages such as uniformity of the material being coated. However, the first layer may be formed around the memory stack using any suitable technique. In an exemplary embodiment, a technique such as Atomic Layer Deposition (ALD) may be used. Atomic layer deposition is a thin film deposition technique based on the sequential use of vapor deposition processes. Other variations of ALD techniques may be used to deposit the first thin layer.

Fig. 5B illustrates forming a second layer 540 around the first layer 530. The second thin layer 540 may be deposited by any suitable method, such as by using atomic layer deposition. However, any suitable deposition technique may be used. Layer 540 may be created from any suitable material, such as, but not limited to, silicon dioxide. In some examples, the layers may be made of different materials, while in other examples, some layers may be made of the same material.

Fig. 5C illustrates the formation of additional material, gap material 550, surrounding layer 540. The gap material 550 may be deposited by any suitable method, such as by using atomic layer deposition. However, any suitable deposition technique may be used. The gap material 540 may be created from any suitable material such as, but not limited to, aluminum oxide or high etch rate oxide. The gap material 550 may surround the layer 540 in three dimensions, including but not limited to, intra-cell spaces (e.g., spaces between the cells 510 and 520).

Fig. 5D shows that metal (metal 590) is deposited at one end of cell 510 and cell 520 to form the word line. Any suitable metal may be selected as metal 590. For example, metal 590 may be deposited on top of the a-C electrodes of cells 510 and 520. To expose the a-C electrode such that metal 590 may be deposited on the a-C electrode, any suitable process may be used to remove any material located beyond the a-C electrode. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar fashion is suitable for removing excess material (e.g., a portion or all of layer 530, layer 540, and material 550). However, other suitable processes may be used to remove excess material, such as shallow trench isolation, for example. Thus, the materials must be selected for both processes to achieve planarization of cell 510 and cell 520, thereby exposing the a-C electrodes therein without damaging or otherwise modifying either cell 510 or cell 520. Metal 590 may be deposited substantially perpendicular to the length of cells 510 and 520. The shape of the metal 590 may be planar (e.g., rectangular sheet metal), and may extend beyond the cells 510 and 520 and attach to a plurality of similar cells.

Fig. 5E is a top view of the layers of the cell. Fig. 5E illustrates the formation of an air gap. Fig. 5E also shows a plurality of units, such as unit 510, unit 520 and unit 521, unit 522, unit 523, unit 524, unit 525, unit 526, and unit 527. Word lines may be added to a group of cells, such as, for example, to cell 522, cell 523, and cell 524. Word lines may also be added to cell 510, cell 522, and cell 525. Sacrificial material (e.g., a portion or all of layer 520, layer 540, and gap material 550) located within the cells (i.e., for example, between cells 510 and 520, between cell 510 and 522, between cell 525 and 526) may be selectively removed by an appropriate process. One such process is wet etching. Wet etching is a microfabrication technique. Wet etching is a material removal process by which liquid chemicals or etchants can be used to remove material. Wet etching may be isotropic (orientation independent) or anisotropic (orientation dependent). By using wet etching, the sacrificial material (e.g., gap material 550) may thus be removed, creating air gaps in the intra-cell space, such as, for example, air gaps 551, 552, 553, 554, and 555. Wet etching may create trenches or other geometries in the sacrificial material (e.g., gap material 550).

Fig. 5F is a top view of the layers of the cell. Fig. 5F shows the formation of buried air gaps by oxide deposition. The oxide deposition process may partially fill the trenches, or other geometries created in the air gaps. In this way, a plurality of air gaps may be created in the intra-cell space that contains or encapsulates the air gaps. In other words, the air gap may be closed and an air pocket may be created between the sacrificial material and the material deposited by the oxide deposition. In this way, a plurality of air gaps, such as, for example, air gap 556, may be created.

The process described in fig. 5A-5F may be repeated again to create a stacked memory cell containing material layers within the cell. By stacking the electrodes, isolated memory cell pillars can be formed. By repeating the process described in fig. 5A-5F, each memory cell formed is thermally isolated from other memory cells within the stack of memory cells. Thus, each cell may be surrounded by a plurality of air gaps.

One advantage of the memory cells created as described above is reduced thermal cross-talk between cells. By increasing the thermal boundary resistance and creating multiple layers, thermal cross-talk is reduced. Furthermore, by filling the gaps, additional mechanical support is provided to the overall three-dimensional memory structure, which is beneficial for reducing the size of the fabrication to smaller pitches and for subsequent processing of the memory.

Fig. 6 depicts a method (method 600) according to an exemplary embodiment of the present disclosure. The method starts in step 605. In step 605, a memory cell may be formed by stacked deposition on a substrate. The substrate may be a conductive material, such as an electrode. The memory cells may be formed by any suitable method, such as, for example, by atomic layer deposition. The memory cell may be formed with an intra-cell gap. In step 610, a first layer may be formed on a memory cell. The first layer may be formed in three dimensions to surround and encapsulate the memory cells. The first layer may be formed from any suitable material, such as, for example, a dielectric material. In step 615, a second layer is deposited atop the first layer and encapsulates the first layer. The second layer may be composed of any suitable material or combination of materials and deposited by any suitable method. In step 620, a gap material (e.g., gap material 550) may be deposited to encapsulate the second layer. The gap material may encapsulate the second layer in three dimensions. In step 625, the material located beyond the intra-cell gap and atop the cell may be removed by any suitable technique. The material may be removed in a manner that allows a substantially flat and continuous surface to be created between the cells and the layers added in steps 605-620. In step 630, a substrate may be added at the location where the material is removed. The substrate may be added between memory cells (e.g., memory cell 510 and memory cell 520). In step 635, the sacrificial material added in the previous step may be removed by a suitable method. One example of such a method is wet etching. In step 640, oxide may be deposited to surround the air pocket created by the wet etch. In this method, the air pocket may be enclosed and surround the storage unit. In step 645, steps 605-640 may be repeated as needed. The method ends at step 650.

Fig. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, and 7I are cross-sections of a three-dimensional cross-point memory according to an embodiment of the invention.

Fig. 7A illustrates a memory cell formed by deposition or stacking of materials. As can be seen in fig. 7A, the cells 710 and 720 are formed of similar materials and thus form parallel lines within the cell stack when viewed in two dimensions. Although not shown in fig. 7A, other components (e.g., those described above or known in the art) or in combination with the cells may be included in various configurations to implement an operable 3D cross-point memory. The cells 710 and 720 may be created or stacked on an electrode (e.g., electrode 701). The units 710 and 720 may be made of various materials or elements, such as W, a-C, ovonic Threshold Switches (OTS) or PCM. For example, units 710 and 720 may be made up of several layers, such as layers 702, 703, 704, 707, and 706, for example, which in turn may be made up of elements such as W, a-C, ovonic Threshold Switches (OTS), or PCM. Figure 7A illustrates the formation of a first thin NIT encapsulation layer around the memory stack illustrated in figure 7A. NIT is a commercially available alloy such as, for example, NIT135. Any suitable material may be used to form the first layer 730. The first layer 730 may also be made of any suitable dielectric material. The dielectric material is selected to ensure that current in the memory (e.g., cells 710 and 720) is not carried to undesired paths outside those cells. Forming the first layer around the memory stack may be achieved by a conformal coating technique. Conformal coating techniques provide technical advantages such as uniformity of the material being coated. However, the first layer may be formed around the memory stack using any suitable technique. In an exemplary embodiment, a technique such as Atomic Layer Deposition (ALD) may be used. Atomic layer deposition is a thin film deposition technique based on the sequential use of vapor deposition processes. Other variations of ALD techniques may be used to deposit the first thin layer.

Fig. 7B illustrates forming a second layer 740 around the first thin layer 730. The second layer 740 may be a non-conformal oxide gap filler. Depending on the embodiment, the gap material 623 may be obtained by Atomic Layer Deposition (ALD) oxide, spin-on dielectric (SOD), or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap fillers include, but are not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), lead sulfide (PbS), and lead selenide (PbSe), as well as cobalt-based compounds and any combination thereof. The second layer 740 may be formed in a manner known as bread loaf (break-loaf), i.e., the non-conformal gap may be thicker toward one end of the cells 710 and 720 (e.g., the deposition may be thicker closer to the layer 706). Thus, the second layer may be formed in three dimensions around layer 730, and the thickness of the layer may be non-uniform. The second layer 740 may be deposited using any suitable method.

Fig. 7C-1 illustrates the deposition of additional non-conformal oxide material 750 and partially surrounding the second layer 740. Material 750 may extend between layers 740 so as to substantially bridge the gaps between layers 740 and form a continuous surface. Material 750 may be made of any suitable material. Once the material 750 is deposited, the material 750 also causes an intra-cell air gap (e.g., air gap 751) between the cells 710 and 720, as well as an air gap 752 adjacent to the cells 720. Fig. 7C-2 shows another view of depositing additional non-conformal oxide. Once the material 750 is deposited, the material 750 also causes an intra-cell air gap (e.g., air gap 751) between the cells 710 and 720, as well as an air gap 752 adjacent to the cells 720.

Fig. 7D shows the exposed a-C electrode 705. Any suitable process may be used to remove any material beyond the electrode. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar fashion is suitable for removing excess material (e.g., a portion or all of layer 730, layer 740, and material 750). Thus, the chemical mechanical process may create a substantially planar surface by removing material while preserving the intra-cell air gaps, such as air gap 751 and air gap 752.

Fig. 7E-1 shows that metal 790 is deposited on top of one end of the cells (e.g., cell 710 and cell 720) to form a word line. For example, metal 790 may be deposited atop the a-C electrodes of cells 710 and 720. To expose the a-C electrode such that metal 790 may be deposited on the a-C electrode, any suitable process may be used to remove any material located beyond the a-C electrode. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar fashion is suitable for removing excess material (e.g., a portion or all of layer 730, layer 740, and material 750). However, other suitable processes may be used to remove excess material, such as, for example, shallow trench isolation. Thus, the materials must be selected for both processes to achieve planarization of cell 510 and cell 520, thereby exposing the a-C electrodes therein without damaging or otherwise modifying either cell 510 or cell 520. Metal 590 may be deposited substantially perpendicular to the length of cells 510 and 520. The shape of the metal 590 may be planar (e.g., rectangular sheet metal), and may extend beyond the cells 510 and 520 and attach to a plurality of similar cells.

Fig. 7E-2 shows a three-dimensional view of the technique. As shown in fig. 7E-2, it can be seen that the air gap extends in three dimensions. For example, the air gap 751 may extend in the x-direction.

Fig. 7E-3 is a top view of this technique. As shown in fig. 7E-3, it can be observed that there is an air gap 751 between cells 710 and 720. Similarly, an air gap 752 adjacent to the cell 720 may be observed.

Fig. 7F shows a top view of this technique. Cell 7F shows several cells (e.g., cell 722, cell 723, cell 724, cell 725, cell 726, cell 727) and air gaps (e.g., air gap 756, air gap 755, and air gap 753). Additional individual cell pillars (e.g., cell 722, cell 723, and cell 724) can be formed by vertical word line patterning, which forms parallel word lines. Accordingly, the stack of materials (e.g., cells 710 and 720) may be further modified by any suitable technique to create additional individual column cells.

Fig. 8 depicts a method (method 800) according to an exemplary embodiment of the present disclosure. The method starts in step 805. In step 805, a memory cell may be formed by stacked deposition on a substrate. The substrate may be a conductive material, such as an electrode. The memory cells may be formed by any suitable method, such as, for example, by atomic layer deposition. The memory cell may be formed with an intra-cell gap. A first layer may be formed on the memory cell. In this step a first layer may be formed in three dimensions to surround and encapsulate the memory cells. The first layer may be formed from any suitable material, such as, for example, a dielectric material. In step 810, a second layer is deposited atop the first layer and encapsulates the first layer. The second layer may be composed of any suitable material or combination of materials and deposited by any suitable method. The first layer may be a non-conformal oxide gap filler layer. The second layer may be deposited in a non-conformal manner, i.e., the deposition of material may have a non-conformal thickness. In this way, the deposited material may be thicker on one side than on the other, resulting in a smaller gap between the materials on one side. In step 815, a non-conformal oxide may be deposited atop the existing layer, which may create a continuous layer of material at one end of the memory cell. Such non-conformal oxide deposition may leave air gaps surrounded by the material deposited in steps 805-815. The air gap may be an intra-cell gap. This process may occur such that the material also creates a continuous bridge of material between the cells that extends at least along the length of the cells. For example, since the memory cells may be formed of different materials of different thicknesses, the materials may connect the various layers of the cell. In step 820, the material located beyond the cell may be removed using techniques such as chemical mechanical polishing or planarization. This step may also remove a portion of the electrode (e.g., the NIT layer of the electrode) such that the carbon electrode portion (a-C) of the cell is exposed. Since the material deposited in step 815 extends along the length of the electrode, a portion of the material remains continuously connected after the process and an intra-cell air gap remains formed after the material is removed. In step 820, a surface may be created that is suitable for adding word lines and may expose the carbon portion of the cell. In step 825, a word line may be deposited atop the surface created in step 820. The word line may be made of a metal material. The word line may allow electrical connectivity in the cell. Step 825 reserves the previously created air gap. In step 830, vertical wordline patterning may be performed to create individual pillar cells. Any suitable method may be used to create the vertical line pattern. Parallel word lines are formed by vertical line patterning. In addition, because of the non-conformal filler as described in the above steps, an air gap may be formed around the cells in both directions (i.e., the air gap may exist between two cells, as well as in a direction perpendicular to the direction). In this way, a closed air gap can be created without affecting the usability of the memory cell. In step 835, steps 805-830 may be repeated as necessary to stack or layer upon layer the storage units to create a 3D memory. The method ends at step 840.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. For example, the foregoing operations need not be performed in the exact order described above. Rather, the various steps may be processed in a different order, such as in reverse order or simultaneously. Unless otherwise stated, steps may also be omitted. In addition, the provision of examples described herein and phrases such as "such as," "including," and the like should not be construed to limit the subject matter of the claims to particular examples; rather, these examples are intended to be illustrative of only one of many possible embodiments. Furthermore, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional memory, comprising:

a first storage unit;

a second memory cell, wherein the first memory cell and the second memory cell each comprise a bottom electrode, a top electrode, and an ovonic threshold switch material between the bottom electrode and the top electrode;

an electrode electrically connecting the first memory cell and the second memory cell;

an intra-cell space between the first storage unit and the second storage unit;

a first layer three-dimensionally at least partially encapsulating the first memory cell, the second memory cell, and the electrode formed earlier, wherein the first layer contacts the bottom electrode, the top electrode, and the ovonic threshold switch material of the first memory cell and the second memory cell;

a second layer at least partially and three-dimensionally surrounding the first layer;

a first air gap three-dimensionally surrounded by at least the second layer; and

the first memory cell and the second memory cell are configured to be exposed on at least one surface, and the top electrodes of the first memory cell and the second memory cell are configured to be coupled to a same word line,

Wherein the first layer and the second layer are composed of different materials.

2. The three-dimensional memory of claim 1, wherein the first layer is deposited using a chemical vapor deposition method.

3. The three-dimensional memory of claim 1, wherein the first layer is deposited using an atomic deposition method.

4. The three-dimensional memory of claim 1, further comprising at least one additional layer.

5. The three-dimensional memory of claim 4, wherein the air gap is a vacuum.

6. The three-dimensional memory of claim 4, wherein the first layer, the second layer, and the at least one additional layer are comprised of a dielectric material.

7. The three-dimensional memory of claim 6, wherein the dielectric material is selected from the group consisting of: a nitride layer (NIT), amorphous carbon (aC) or electrode layer, phase change material, ovonic threshold switch material (OTS), or tungsten (W) nanoporous silicon, hydrosilicates (HSQ), polytetrafluoroethylene (Teflon-AF or PTFE), silicon oxyfluoride (FSG), lead zirconate titanate (PZT), tantalum pentoxide, aluminum oxide, zirconium dioxide, hafnium dioxide, and any combination thereof.

8. The three-dimensional memory of claim 7, wherein the nitride layer comprises silicon nitride.

9. The three-dimensional memory of claim 1, wherein the first layer and the second layer are comprised of a dielectric material.

10. A three-dimensional memory, comprising:

a top cell array of memory cells;

a bottom cell array of memory cells;

at least one electrode electrically connected to at least one of the top cell array of memory cells or the bottom cell array of memory cells; and

an in-memory space between the memory cells, wherein the in-memory space is filled with a first layer and a second layer, the first layer and the second layer creating an in-material interface; and

an air gap, said air gap being surrounded in three dimensions by said second layer,

wherein a first memory cell and a second memory cell of the memory cells are configured to be exposed on at least one surface, each of the first memory cell and the second memory cell includes a bottom electrode, a top electrode, and an ovonic threshold switch material between the bottom electrode and the top electrode, the first layer contacts the bottom electrode, the top electrode, and the ovonic threshold switch material of the first memory cell and the second memory cell that were previously formed, and the top electrodes of the first memory cell and the second memory cell are configured to be coupled to a same word line, and

11. The three-dimensional memory of claim 10, wherein the air gap is created and the in-memory space is partially filled.

12. A method of forming a three-dimensional memory, comprising:

providing a first storage unit;

providing a second memory cell, wherein the first memory cell and the second memory cell each comprise a bottom electrode, a top electrode, and an ovonic threshold switch material between the bottom electrode and the top electrode;

providing an electrode electrically connecting the first memory cell and the second memory cell;

creating a first layer that three-dimensionally encapsulates the first memory cell, the second memory cell, and the electrode that were formed first, wherein the first layer contacts the bottom electrode, the top electrode, and the ovonic threshold switch material of the first memory cell and the second memory cell;

creating a second layer that at least partially and three-dimensionally surrounds the first layer; and

creating an air gap, wherein the air gap is surrounded three-dimensionally by at least the second layer; and

Exposing the first memory cell and the second memory cell on at least one surface,

wherein the top electrodes of the first and second memory cells are configured to be coupled to the same word line, an

13. The method of claim 12, further comprising the step of: the word lines are patterned to create a plurality of pillar cells.

14. The method of claim 13, further wherein patterning the word line creates a plurality of air gaps around each of the plurality of pillar cells.

15. The method of claim 14, further comprising: an encapsulation layer is provided.

16. The method of claim 13, further comprising the step of:

at least one additional layer is created such that the at least one additional layer partially occupies the intra-cell space.

17. The method of claim 16, further comprising the step of:

and removing the material between the intra-cell spaces beyond the top of the first storage unit or the second storage unit.

18. The method of claim 17, further comprising the step of:

The same word line is added substantially on the surface exposed by removing material above the top of the first memory cell or the second memory cell.