WO2022095007A1

WO2022095007A1 - Memory devices having memory cells with multiple threshold voltages and methods for forming and operating the same

Info

Publication number: WO2022095007A1
Application number: PCT/CN2020/127420
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2020-11-09
Filing date: 2020-11-09
Publication date: 2022-05-12
Also published as: CN112602152A

Abstract

Memory devices and methods are disclosed. In an example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a cell element without a selector. The cell element is configured to have a plurality of threshold voltages.

Description

MEMORY DEVICES HAVING MEMORY CELLS WITH MULTIPLE THRESHOLD VOLTAGES AND METHODS FOR FORMING AND OPERATING THE SAME

BACKGROUND

Embodiments of the present disclosure relate to memory devices and fabrication and operation methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, phase-change memory (PCM) can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. PCM array cells can be vertically stacked in 3D to form a 3D PCM.

SUMMARY

Embodiments of memory devices and methods for forming and operating the same are disclosed herein.

In an example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a cell element without a selector. The cell element is configured to have a plurality of threshold voltages.

In another example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes stacked a metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.

In still another example, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes doped arsenic selenide.

In yet another example, a method for forming a memory device is disclosed. A cell element layer is formed. A plurality of gaps are formed through the cell element layer to separate the cell element layer into a plurality of cell elements each configured to have a plurality of threshold voltages. A plurality of insulating structures are formed in the plurality of gaps between the plurality of cell elements.

In yet another example, a method for operating a memory device is disclosed. The 3D memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. One of the memory cells is programmed to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines. The memory cell is programmed to a second threshold voltage by applying a second voltage pulse between the bit line and the word line. The memory cell is sensed at a sensing voltage between the first and second threshold voltages.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate embodiments of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a perspective view of an exemplary 3D cross-point (XPoint) memory device, according to some embodiments of the present disclosure.

FIG. 2 illustrates a side view of a cross-section of a 3D XPoint memory device having ovonic threshold switch (OTS) selectors.

FIGs. 3A–3C illustrate side views of cross-sections of an exemplary memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure.

FIG. 4 illustrates a side view of a cross-section of another exemplary memory cell with multiple threshold voltages, according to some embodiments of the present disclosure.

FIGs. 5A and 5B illustrate schematic diagrams of the operation of an exemplary array of memory cells with multiple threshold voltages, according to some embodiments of the present disclosure.

FIGs. 6A–6H illustrate an exemplary fabrication process for forming a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure.

FIG. 7 illustrates a flowchart of an exemplary method for forming a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure.

FIG. 8 illustrates a flowchart of an exemplary method for operating a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure.

FIG. 9 illustrates exemplary first and second threshold voltages of a memory cell, according to some embodiments of the present disclosure.

Embodiments of the present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some embodiments, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other embodiments whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10–30%of the value (e.g., ±10%, ±20%, or ±30%of the value) .

As used herein, the term “3D memory device” refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

A PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. PCM cells can be vertically stacked in 3D to form a 3D PCM. At the reset state, a short high current/voltage is applied to heat up the PCM cell material to melt and quench molten the material into an amorphous high resistance state, which shows electronic threshold switching above a threshold voltage Vt before crystallization steps in. At the set state, a long and medium current/voltage is applied to heat up the PCM cell material to crystallize the amorphous material into a crystalline low resistance state, which is more like a resistor.

3D PCMs include 3D XPoint memory, which stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable. For example, FIG. 1 illustrates a perspective view of an exemplary 3D XPoint memory device 100, according to some embodiments of the present disclosure. 3D XPoint memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some embodiments. 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above lower bit lines 102. 3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally along the word line direction in the plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is noted that z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D XPoint memory device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108 each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. Memory cells 108 in 3D XPoint memory device 100 are arranged in a memory array.

In existing 3D XPoint memory, the materials of selector 112 are ovonic threshold switch (OTS) materials, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (V _a) higher than the threshold voltage is applied (V _th) . For example, FIG. 2 illustrates a side view of a cross-section of a 3D XPoint memory device 200 having OTS selectors. 3D XPoint memory device 200 includes a plurality of parallel bit lines 204 above a substrate 202 and a plurality of parallel word lines 216 above bit lines 204.3D XPoint memory device 200 also includes a plurality of memory cells 201 each disposed at an intersection of a respective pair of bit line 204 and word line 216. Adjacent memory cells 201 are separated by an insulating structure 203. Each memory cell 201 includes an OTS selector 208 and a PCM element 212 (e.g., an example of a cell element) above OTS selector 208. Each memory cell 201 further includes three

electrodes

206, 210, and 214 vertically between a respective bit line 204, OTS selector 208, PCM element 212, and a respective word line 216, respectively.

OTS selector 208 includes an OTS material, such as ZnTe. At lower voltage ( |V _a| < V _th) , the high resistance of OTS selector 208 in its off-state keeps the off-state current (I _off) low. At higher voltage (|V _a| > V _th) , OTS selector 208 undergoes OTS phenomenon and switches to the on-state with low resistance; thus, the current through OTS selector 208 in the on-state (I _on) increases. The volatile on-state is maintained as long as high voltage is supplied. At the reset operation, the threshold voltage Vt of memory cell 201 is the summation of the threshold voltage Vt (OTS) of OTS selector 208 and the threshold voltage Vt (PCM) of PCM element 212. At the set state, the threshold voltage Vt of memory cell 201 is the threshold voltage Vt (OTS) of OTS selector 208 alone. In other words, OTS selector 208 and PCM element 212 together are needed to set the different threshold voltages of memory cell 201 at different cell states (e.g., reset state or set state) . In other examples, selector 112 may be replaced with switching devices other than OTS selector 208, such as transistors or diodes.

However, as the cell element (e.g., PCM element 212) and selector (e.g., OTS selector 208) are stacked vertically and each includes a stack of films patterned in high aspect ratio lines, the fabrication process is challenging, thereby affecting the product yield. The multi-film stack structure also leads to thinner word line and bit line films and higher sheet resistance that limit the device size and electric performance of 3D XPoint memory device 200.

Various embodiments in accordance with the present disclosure provide memory devices, e.g., 3D XPoint memory device, having selector-less memory cells with multiple threshold voltages, and fabrication and operation method thereof. The selector-less memory cell can remain in threshold switching state, but with threshold voltage Vt tunable to store data. That is, without any selector, the cell element of the memory cell itself can have two or more threshold voltages (e.g., threshold switching voltages) that can be programmed, for example, by applying a positive or negative program pulse with different amplitudes and/or widths, even. Thus, compared with traditional PCM devices with selectors (e.g., OTS selectors) , the selector-less memory cells disclosed herein can be greatly simplified, and the height of the memory cell can be reduced as well to lower the aspect ratio the memory cell structure, thereby enabling larger array size and reducing the sheet resistance by increasing the thickness of the word line and bit line films. In some embodiments, the selector-less memory cells with multiple threshold voltages disclosed herein are formed in a self-aligned manner at the intersection of a pair of a word line and a bit line. Moreover, cross-contamination between selectors and cell elements during the fabrication process can be avoided as well. As a result, the fabrication process can be simplified, and the product yield can be increased.

FIGs. 3A–3C illustrate side views of cross-sections of an exemplary memory device 300 having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. Memory device 300, such as a 3D XPoint memory device, can include a plurality of bit lines 304 above a substrate 302, which can include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. Bit lines 304 can be parallel to one another and in the same plane. In some embodiments, a plurality of parallel bit lines 304 each extends laterally in the y-direction (e.g., the bit line direction) in FIG. 3A. Memory device 300 can further include a plurality of word lines 318 above bit lines 304. Word lines 318 can be parallel to one another and in the same plane. In some embodiments, a plurality of parallel word lines 318 each extends laterally in the x-direction (e.g., the word line direction) in FIG. 3A. Word lines 318 and bit lines 304 of memory device 300, such as a 3D XPoint memory device, can be perpendicularly arranged conductors in a cross-point architecture. Bit lines 304 and word lines 318 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each of bit lines 304 and word lines 318 includes a metal, such as tungsten.

In some embodiments, memory device 300 includes a plurality of memory cells 301 each disposed at an intersection of a respective one of bit lines 304 and a respective one of word lines 318. Each memory cell 301 can be accessed individually by a current applied through a respective word line 318 and a respective bit line 304 in contact with memory cell 301. As shown in FIG. 3A, memory device 300 can further include insulating structures 303 laterally between adjacent memory cells 301. In some embodiments, each memory cell 301 has a vertical pillar shape (e.g., similar to memory cell 108 in FIG. 1) , and insulating structures 303 can extend laterally in both x-direction and y-direction to separate the pillar-shaped memory cells 301. In some embodiments, insulating structure 303 includes one or more dielectric layers, such as an encapsulation layer 322 formed along the sidewalls of memory cells 301 and bit lines 304 and a capping layer 323 filling the remaining space between memory cells 301. The dielectric layers of insulating structures 303 can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some embodiments, encapsulation layer 322 and capping layer 323 include silicon nitride and silicon oxide, respectively.

Each memory cell 301 can include a cell element without a selector. That is, memory cell 301 can be a selector-less memory cell. Different from known memory cells each including a cell element and a selector connected in series, the cell element of memory cell 301 can perform dual functions of storing data and switching as it can be configured to have multiple threshold voltages without the presence of a separate selector. A single bit of data can be stored in each memory cell 301 and can be written or read by varying the voltage applied to a respective cell element, which eliminates the need for selectors (e.g., OTS selectors, transistors, or diodes) .

As shown in FIG. 3A, the cell element of each memory cell 301 can include stacked a metal ion reservoir 306, a solid electrolyte 308, and a separator 310. In some embodiments, metal ion reservoir 306 is below and in contact with a respective word line 318, solid electrolyte 308 is above in contact with a respective bit line 304, and separator 310 is vertically between, i.e., sandwiched between, metal ion reservoir 306 and solid electrolyte 308. For example, separator 310 may be in contact with metal ion reservoir 306 and solid electrolyte 308 at opposite sides thereof. In some embodiments, the thickness of metal ion reservoir 306 is between about 5 nm and about 50 nm, such as between 5 nm and 50 nm (e.g., 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some embodiments, the thickness of solid electrolyte is between about 10 nm and about 100 nm, such as between 10 nm and 100 nm (e.g., 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, 55 nm, 60 nm, 65 nm, 70 nm, 75 nm, 80 nm, 85 nm, 90 nm, 95 nm, 100 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some embodiments, the thickness of separator 310 is between about 1 nm and about 10 nm, such as between 1 nm and 10 nm (e.g., 1 nm, 1.5 nm, 2 nm, 2.5 nm, 3 nm, 3.5 nm, 4 nm, 4.5 nm, 5 nm, 5.5 nm, 6 nm, 6.5 nm, 7 nm, 7.5 nm, 8 nm, 8.5 nm, 9 nm, 9.5 nm, 10 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) .

Metal ion reservoir 306 can contain metal ions, such as Ag ions or Cu ions. In some embodiments, metal ion reservoir 306 includes Ag, Cu, silver sulfide (AgS) , copper sulfide (CuS) , silver selenide (AgSe) , copper selenide (CuSe) , or any combinations thereof. In some embodiments, solid electrolyte 308 includes germanium selenide (GeSe) , germanium sulfide (GeS) , silver selenide (AgSe) , silver sulfide (AgS) , copper telluride (CuTe) , or any combination thereof. It is understood that AgSe and AgS may be used as the materials of metal ion reservoir 306 and/or solid electrolyte 308, for example, depending on the concentration of AgSe or AgS in metal ion reservoir 306 and/or solid electrolyte 308. For example, the concentration of AgSe or AgS in metal ion reservoir 306 may be greater than the concentration of AgSe or AgS in solid electrolyte 308. Separator 310 can facilitate the maintenance of multiple threshold voltages programmed to the cell element of memory cell 301. In some embodiments, separator 310 includes a dielectric, for example, silicon oxide (SiO) , aluminum oxide (AlO) , gadolinium oxide (GdO) , or any combinations thereof.

Referring to FIG. 3B, memory device 300 can be a 3D XPoint memory device in which the cell element can be in a double-stacked storage/selector structure. The structures, functions, and materials of the same components that have been described above with respect to memory device 300 in FIG. 3A are not repeated for ease of description. As shown in FIG. 3B, another array of memory cells 321 in the same plane can be formed above the array of memory cells 301 and share word lines 318 with the array of memory cells 301. Each memory cell 321 can include a cell element including stacked solid electrolyte 308, separator 310, and metal ion reservoir 306 from bottom to top, like memory cell 301. A plurality of bit lines 324 can be formed above and in contact with memory cells 321 to drive memory cells 321 along with word lines 318. Insulating structures 325 can be formed above word lines 318 and laterally between memory cells 321 as well, like insulating structures 303. By stacking more layers of an array of memory cells vertically with word lines and bit lines in a cross-point architecture, the array cell density of memory device 300 can be continuously increased.

It is understood that the structure of memory cell 301 is not limited to the example in FIGs. 3A and 3B and may include any suitable structures. In one example, the relative positions of metal ion reservoir 306 and solid electrolyte 308 may be switched in other examples. In another example, an electrode may be disposed between metal ion reservoir 306 and word line 318 in other examples as. As shown in FIG. 3C, an electrode 312 is vertically between, i.e., sandwiched between, metal ion reservoir 306 and word line 318, according to some embodiments. For example, electrode 312 may be in contact with metal ion reservoir 306 and word line 318 at opposite sides thereof. Electrode 312 can include conductive materials including, but not limited to, W, Co, Cu, Al, metal nitride, carbon, polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, electrode 312 includes W or titanium nitride (TiN) . Although not shown, it is understood that in some examples, another electrode may be disposed between solid electrolyte 308 and bit line 304 as well. That is, memory cell 301 may further include a first electrode between metal ion reservoir 306 and word line 318 and/or a second electrode between solid electrolyte 308 and bit line 304.

It is further understood that the cell element of memory cell 301 is not limited to the example in FIGs. 3A and 3B as long as the cell element can be programmed to have multiple threshold voltages in selector-less memory cell 301. FIG. 4 illustrates a side view of a cross-section of another exemplary memory cell 401 with multiple threshold voltages, according to some embodiments of the present disclosure. Memory cell 401 may replace memory cell 301 in memory device 300 in FIGs. 3A–3C in some examples.

As shown in FIG. 4, memory cell 401 can include a cell element without a selector. That is, memory cell 401 can be a selector-less memory cell. Different from known memory cells each including a cell element and a selector connected in series, the cell element of memory cell 401 can perform dual functions of storing data and switching as it can be configured to have multiple threshold voltages without the presence of a separate selector. A single bit of data can be stored in each memory cell 401 and can be written or read by varying the voltage applied to a respective cell element, which eliminates the need for selectors (e.g., OTS selectors, transistors, or diodes) . As shown in FIG. 4A, the cell element of each memory 401 can include doped arsenic selenide 402. In some embodiments, arsenic selenide 402 is doped with silver (Ag) , copper (Cu) , silicon (Si) , germanium (Ge) , or any combination thereof. In some embodiments, memory cell 401 further includes electrode (s) 404 at one or both opposite sides of doped arsenic selenide 402 to be in contact with the word line and/or bit line (e.g., word line 318 and bit line 304 in FIGs. 3A–3C) .

The cell element in the selector-less memory cells disclosed herein (e.g., memory cells 301 and 401) can be configured to have a plurality of threshold voltages (e.g., threshold switching voltages) at different levels, such as a first threshold voltage Vt1 and a second threshold voltage Vt2 greater than Vt1, as shown in FIG. 9. The two different threshold voltages Vt1 and Vt2 (or even more threshold voltages) can be set using program operations, i.e., programmed, to the cell element of a selector-less memory cell by positive or negative program pulses with different amplitudes and/or widths, as described below in detail. In some embodiments, when a first voltage pulse is applied across the cell element, the cell element is configured to have the first threshold voltage Vt1; when a second voltage pulse is applied across the cell element, the cell element is configured to have the second threshold voltage Vt2. In some embodiments, the second threshold voltage Vt2 is greater than the first threshold voltage Vt2 when the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse, and/or when the width of the first voltage pulse is great than the width of the second voltage pulse. That is, a first program pulse with low amplitude and/or long width can program the first threshold voltage Vt1 smaller than the second threshold voltage Vt2 programmed by a second program pulse with high amplitude and/or short width.

With respect to memory cell 301 in FIGs. 3A–3C, positive program pulses (e.g., positive voltage pulses) applied from metal ion reservoir 306 to solid electrolyte 308 (e.g., in the negative z-direction in FIGs. 3A–3C) can be used to program the threshold voltages of memory cell 301. In some embodiments, the cell element of memory cell 301 is configured to be insulative prior to the program operations (i.e., a native/virgin cell) . In some embodiments, the cell element of memory cell 301 is configured to have the first threshold voltage Vt1 when a first positive voltage pulse is applied from metal ion reservoir 306 to solid electrolyte 308, i.e., using a first program operation. In some embodiments, the cell element of memory cell 301 is configured to be insulative again when a negative voltage pulse is applied from solid electrolyte 308 to metal ion reservoir 306, i.e., using an erase operation. In some embodiments, the cell element of memory cell 301 is configured to have the second threshold voltage Vt2 when a second positive voltage pulse is applied from metal ion reservoir 306 to solid electrolyte 308 again, i.e., using a second program operation. In one example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In another example, the width of the second positive voltage pulse is smaller than the width of the first positive voltage pulse. In still another example, the amplitude of the second positive voltage pulse is greater than the amplitude of the first positive voltage pulse, and the width of the second positive voltage pulse is smaller than the width of the first positive voltage pulse. In either of the three examples above, the second threshold voltage Vt2 may be programmed to be greater than the first threshold voltage Vt1. In some embodiments, the amplitude of the negative voltage pulse is greater than the amplitudes of the first and second positive voltage pulses in order to set the cell element of memory cell 301 back to insulative, i.e., erasing memory cell 301.

With respect to memory cell 401 in FIG. 4, the cell element may not be configured to be insulative either in the native/virgin cell or using an erase operation, which is different from memory cell 301. In some embodiments, the cell element of memory cell 401 is configured to have a native threshold voltage Vtn, as opposed to being insulative, prior to the program operations (i.e., a native/virgin cell) . In some embodiments, the cell element of memory cell 401 is configured to have the first threshold voltage Vt1 when a first voltage pulse is applied across the cell element, i.e., using a first program operation. In some embodiments, the cell element of memory cell 401 is configured to have the second threshold voltage Vt2 when a second voltage pulse is applied across the cell element again, i.e., using a second program operation. In one example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In another example, the width of the second voltage pulse is smaller than the width of the first voltage pulse. In still another example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse, and the width of the second voltage pulse is smaller than the width of the first voltage pulse. In either of the three examples above, the second threshold voltage Vt2 may be programmed to be greater than the first threshold voltage Vt1. In some embodiment, no erase operation is performed to erase the cell element of memory cell 401, i.e., setting the cell element to be insulative.

FIGs. 5A and 5B illustrate schematic diagrams of the operation of an exemplary array of memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. As shown in FIGs. 5A and 5B, an array of memory cells 502 (e.g., corresponding to memory cells 301 in FIGs. 3A–3C or memory cells 401 in FIG. 4) can be formed as the intersections (cross-points) of word lines 504 (e.g., corresponding to word lines 318 in FIGs. 3A–3C) and bit lines 506 (e.g., corresponding to bit lines 304 in FIGs. 3A–3C) , respectively. Each memory cell 502 can be a selector-less memory cell having a cell element configured to have multiple threshold voltages.

In FIG. 5A, to operate the array of memory cells 502, a word line voltage (V _w) having a value of either 0 or V/2 can be applied to each word line 504, and a bit line voltage (V _b) having a value of either 0 or -V/2 can be applied to each bit line 506. The voltage (Va) applied to each memory cell 502 can thus be either 0, V/2, or V. In some embodiments, V is set to be any voltage pulse described above for programming or erasing the cell element of memory cell 502. As shown in FIG. 5A, only memory cell 502 (Va = V, in the dotted circle in FIG. 5A) at the intersection of the pair of word line 504 and bit line 506 with non-zero voltages can be selected for programming or erasing. Other memory cells 502 (Va = 0 or V/2) at each intersection of a respective pair of word line 504 and bit line 506 with at least one zero voltage are not selected for programming or erasing, according to some embodiments.

In FIG. 5B, to operate the array of memory cells 502, a word line voltage (V _w) having a value of either V/2 or V can be applied to each word line 504, and a bit line voltage (V _b) having a value of either 0 or V/2 can be applied to each bit line 506. The voltage (Va) applied to each memory cell 502 can thus be either 0, V/2, or V. In some embodiments, V is set to be any voltage pulse described above for programming or erasing the cell element of memory cell 502. As shown in FIG. 5B, only memory cell 502 (Va = V, in the dotted circle in FIG. 5B) at the intersection of the pair of word line 504 and bit line 506 with non-V/2 voltages can be selected for programming or erasing. Other memory cells 502 (Va = 0 or V/2) at each intersection of a respective pair of word line 504 and bit line 506 with at least one V/2 voltage are not selected for programming or erasing, according to some embodiments.

FIGs. 6A–6H illustrate an exemplary fabrication process for forming a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. FIG. 7 illustrates a flowchart of an exemplary method 700 for forming a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. Examples of the memory device depicted in FIGs. 6A–6H and 7 include memory device 300 depicted in FIGs. 3A–3C. FIGs. 6A–6H and 7 will be described together. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7.

Referring to FIG. 7, method 700 starts at operation 702, in which a cell element layer is formed above a substrate. In some embodiments, to form the cell element layer, layers of a solid electrolyte, a separator, and a metal ion reservoir are sequentially deposited. The metal ion reservoir can include at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide. The solid electrolyte can include at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride. The separator can include at least one of silicon oxide, aluminum oxide, or gadolinium oxide. In some embodiments, a conductor layer is formed on the substrate prior to the formation of the cell element layer, such that the cell element layer is formed on the conductor layer.

Referring to FIG. 6A, a conductor layer 604 is formed on a substrate 602. In some embodiments, a metal layer, such as a W layer, is deposited using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , or any combination thereof.

As illustrated in FIG. 6A, a cell element layer 605 is formed on conductor layer 604. In some embodiments, to form cell element layer 605, a solid electrolyte layer 606, a separator layer 612, and a metal ion reservoir layer 614 are sequentially deposited on conductor layer 604 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. For example, metal ion reservoir layer 614 may include Ag, Cu, AgS, CuS, AgSe, CuSe, or any combinations thereof, solid electrolyte layer 606 may include GeSe, GeS, AgSe, AgS, CuTe, or any combination thereof, and separator layer 612 may include SiO, AlO, GdO, or any combination thereof. In one example, the thickness of solid electrolyte layer 606 may be between about 10 nm and about 100 nm, the thickness of metal ion reservoir layer 614 is between about 5 nm and about 50 nm, and the thickness of separator layer 612 is between about 1 nm and about 10 nm.

In some embodiments, a dielectric layer 618 is formed on cell element layer 605 by depositing dielectric materials, such as silicon nitride, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof to act as the etching mask of cell element layer 605 in the later process. In some embodiments, an electrode layer (not shown) is formed between cell element layer 605 and dielectric layer 618 by depositing conductive materials, such as W, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof to form electrodes (e.g., electrodes 312 in FIG. 3C) between cell elements 622 and conductor layer (word line) 630.

In some embodiments, to form the cell element layer, a layer of arsenic selenide is deposited, and the layer of arsenic selenide is doped with at least one of silver, copper, silicon, or germanium. As shown in FIG. 4, AsSe layer 402 may be deposited on conductor layer 604 (e.g., shown in FIG. 6A) using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. AsSe layer 402 then may be doped with Ag, Cu, Si, and/or Ge using ion implantation and/or thermal diffusion. In some embodiments, in situ doping is performed to dope AsSe layer 402 while depositing AsSe layer 402, for example, using CVD.

Method 700 proceeds to operation 704, as illustrated in FIG. 7, in which a plurality of gaps are formed through the cell element layer to separate the cell element layer into a plurality of cell elements each configured to have a plurality of threshold voltages. In some embodiments, to form the plurality of gaps, the cell element layer is double patterned, and the double-patterned cell element layer is etched through.

As illustrated in FIG. 6B, cell element layer 605, conductor layer 604, and dielectric layer 618 (e.g., shown in FIG. 6A) are etched through in the y-direction (e.g., the bit line direction) to form a plurality of gaps 620. In some embodiments, cell element layer 605, conductor layer 604, and dielectric layer 618 are double patterned first. For example, dielectric layer 618 may be patterned by lithography, development, and etching. Double patterning can include, but not limited to, litho-etch-litho-etch (LELE) pitch- splitting or self-aligned double patterning (SADP) , to control the critical dimensions of cell elements 622 to be formed from cell element layer 605. In some embodiments, double-patterned cell element layer 605 and conductor layer 604 are then etched through in the y-direction to form parallel gaps 620 in the y-direction using double-patterned dielectric layer 618 as the etching mask. Cell element layer 605 and conductor layer 604 can be etched through by one or more wet etching and/or dry etching processes, such as deep reactive-ion etching (DRIE) , using the double-patterned etching mask to simultaneously form parallel gaps 620. Cell elements 622 separated by gaps 620 and each including parts of cell element layer 605 (e.g., solid electrolyte layer 606, separator layer 612, and metal ion reservoir layer 614, or doped AsSe layer 402 in FIG. 4) are thereby formed, according to some embodiments. As described above in detail, each cell element 622 can be configured to have a plurality of threshold voltages. In some embodiments, conductor layer 604 is separated by gaps 620 as well, forming bit lines below and in contact with cell elements 622, respectively.

Method 700 proceeds to operation 706, as illustrated in FIG. 7, in which a plurality of insulating structures are formed in the plurality of gaps between the plurality of cell elements. In some embodiments, to form the plurality of insulating structures, one or more dielectric layers are deposited on the plurality of cell elements and into the plurality of gaps to fill the plurality of gaps, and the deposited dielectric layers are planarized to expose the plurality of cell elements.

As illustrated in FIG. 6C, an encapsulation layer 624 is deposited on cell elements 622 and into gaps 620 to protect the exposed cell elements 622. In some embodiments, a dielectric layer, such as a silicon nitride layer, is deposited along the sidewalls and top surfaces of cell elements 622 to fully cover cell elements 622 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof to form encapsulation layer 624. In some embodiments, encapsulation layer 624 is deposited using ALD to form a thin, conformal layer without fully filling gaps 620 between cell elements 622.

As illustrated in FIG. 6D, a capping layer 626 is deposited over encapsulation layer 624 to fill gaps 620. In some embodiments, a dielectric layer, such as a silicon oxide layer, is deposited over encapsulation layer 624 and into gaps 620 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, any other suitable deposition process, or any combination thereof to form capping layer 626. In some embodiments, to fully fill gaps 620 without air gaps, capping layer 626 is formed by depositing silicon oxide using ALD or flowable CVD or by spin-coating spin-on dielectrics (SODs) . Insulating structures 629 laterally between cell elements 622 and each including encapsulation layer 624 and capping layer 626 are thereby formed, according to some embodiments.

As illustrated in FIG. 6E, a planarization process, such as chemical mechanical polishing (CMP) , grinding, or etching, is used to planarized capping layer 626 and encapsulation layer 624 to remove parts of planarized capping layer 626 and encapsulation layer 624 on the top surfaces of cell elements 622. In some embodiments, the planarization process continues to remove dielectric layer 618 (e.g., shown in FIG. 6D) to expose metal ion reservoir layer 614 of each cell element 622. Although FIGs. 6A–6E illustrate the gap etching and filling processes only in the y-direction for ease of description, it is understood that to form pillar-shaped memory cells that can be self-aligned at the intersections of perpendicular bit lines and word lines, cell element layer 605 may need to be etched in two perpendicular directions (e.g., both the x-direction and y-direction) to form perpendicular gaps filled with insulating structures. The same gap etching and filling processes described above with respect to FIGs. 6A–6E may be performed again in the x-direction as needed.

Method 700 proceeds to operation 708, as illustrated in FIG. 7, in which a plurality of word lines are formed above and in contact with the plurality of cell elements. As illustrated in FIG. 6F, a conductor layer 630 is formed on cell elements 622 and insulating structures 629. In some embodiments, a metal layer, such as a W layer, is deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Conductor layer 630 can then be patterned using, for example, double patterning, and etched, for example, using RIE, in the x-direction (e.g., the word line direction) of FIG. 6F to form a plurality of word lines above and in contact with cell elements 622 (e.g., metal ion reservoir layer 614) .

In some embodiments, another array of cell elements are formed above and in contact with the word lines using similar processes as described above with respect to FIGs. 6A–6E and 7. As illustrated in FIG. 6G, a cell element layer 631 is formed on conductor layer 630 (forming the word lines) , and a conductor layer 644 is formed on cell element layer 631. In some embodiments, to form cell element layer 631 and conductor layer 644, a solid electrolyte layer 632, a separator layer 638, a metal ion reservoir layer 640, and conductor layer 644 are sequentially deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As illustrated in FIG. 6H, cell elements 651 each including parts of solid electrolyte layer 632, separator layer 638, and metal ion reservoir layer 640 and laterally separated by insulating structures 649 are formed from cell element layer 631 using the processes described above with respect to FIGs. 6B–6E. Conductor 644 can be patterned and etched to form a plurality of bit lines above and in contact with cell elements 651, respectively, as well. The processes for forming similar components that have been described above with respect to FIGs. 6A–6E are not repeated for ease of description.

FIG. 8 illustrates a flowchart of an exemplary method 800 for operating a memory device having memory cells with multiple threshold voltages, according to some embodiments of the present disclosure. Examples of the memory device depicted in FIG. 8 include memory device 300 depicted in FIGs. 3A–3C or any other memory devices disclosed herein. It is understood that the operations shown in method 800 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 8.

Referring to FIG. 8, method 800 starts at operation 802, in which one of the memory cells is programmed to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines. For example, memory cell 301 may be programmed to the first threshold voltage Vt1 by applying a first positive voltage pulse from metal ion reservoir 306 to solid electrolyte 308.

Method 800 proceeds to operation 804, as illustrated in FIG. 8, in which the memory cell is programmed to a second threshold voltage by applying a second voltage pulse between the bit line and the word line. In some embodiments, when at least one of (i) the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse, or (ii) the width of the first voltage pulse is greater than the width of the second voltage pulse, the second threshold voltage is greater than the first threshold voltage. For example, memory cell 301 may be programmed to the second threshold voltage Vt2 greater than the first threshold voltage Vt1 by applying a second positive voltage pulse from metal ion reservoir 306 to solid electrolyte 308. In one example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse. In another example, the width of the first voltage pulse is greater than the width of the second voltage pulse. In still another example, the amplitude of the second voltage pulse is greater than the amplitude of the first voltage pulse, and the width of the first voltage pulse is greater than the width of the second voltage pulse.

In some embodiments, the memory cell is programmed to be insulative by applying a third voltage pulse between the bit line and the word line. The polarity of the third voltage pulse can be opposite to the polarity of the first voltage pulse or the polarity of the second voltage pulse. For example, memory cell 301 may be programmed to be inclusive (i.e., erased) by applying a negative voltage pulse from solid electrolyte 308 to metal ion reservoir 306.

Method 800 proceeds to operation 806, as illustrated in FIG. 8, in which the memory cell is sensed at a sensing voltage between the first and second threshold voltages. For example, memory cell 301 may be sensed at a sensing voltage Vs between the first and second threshold voltages Vt1 and Vt2, e.g., Vt1 < Vs < Vt2.

According to one aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes a cell element without a selector. The cell element is configured to have a plurality of threshold voltages.

In some embodiments, the cell element includes stacked a metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.

In some embodiments, the metal ion reservoir includes at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide.

In some embodiments, the solid electrolyte includes at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.

In some embodiments, the separator includes a dielectric. In some embodiments, the dielectric includes at least one of silicon oxide, aluminum oxide, or gadolinium oxide.

In some embodiments, a thickness of the solid electrolyte is between about 10 nm and about 100 nm.

In some embodiments, a thickness of the solid electrolyte is between about 10 nm and about 100 nm, a thickness of the metal ion reservoir is between about 5 nm and about 50 nm, and a thickness of the separator is between about 1 nm and about 10 nm.

In some embodiments, when a first positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte, the cell element is configured to have a first threshold voltage of the plurality of threshold voltages. In some embodiments, when a second positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte, the cell element is configured to have a second threshold voltage of the plurality of threshold voltages. In some embodiments, when a negative voltage pulse is applied from the solid electrolyte to the metal ion reservoir, the cell element is configured to be insulative.

In some embodiments, when at least one of (i) a second amplitude of the second positive voltage pulse is greater than a first amplitude of the first positive voltage pulse, or (ii) a first width of the first positive voltage pulse is greater than a second width of the second positive voltage pulse, the second threshold voltage is greater than the first threshold voltage.

In some embodiments, the cell element includes doped arsenic selenide. In some embodiments, the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.

In some embodiments, when a first voltage pulse is applied across the cell element, the cell element is configured to have a first threshold voltage of the plurality of threshold voltages. In some embodiments, when a second voltage pulse is applied across the cell element, the cell element is configured to have a second threshold voltage of the plurality of threshold voltages.

In some embodiments, when at least one of (i) a second amplitude of the second voltage pulse is greater than a first amplitude of the first voltage pulse, or (ii) a first width of the first voltage pulse is greater than a second width of the second voltage pulse, the second threshold voltage is greater than the first threshold voltage.

In some embodiments, the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

According to another aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes stacked a metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.

In some embodiments, the metal ion reservoir includes at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide, the solid electrolyte includes at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride, and the separator includes at least one of silicon oxide, aluminum oxide, or gadolinium oxide.

According to still another aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes doped arsenic selenide.

In some embodiments, the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.

According to yet another aspect of the present disclosure, a method for forming a memory device is disclosed. A cell element layer is formed. A plurality of gaps are formed through the cell element layer to separate the cell element layer into a plurality of cell elements each configured to have a plurality of threshold voltages. A plurality of insulating structures are formed in the plurality of gaps between the plurality of cell elements.

In some embodiments, to form the cell element layer, layers of a solid electrolyte, a separator, and a metal ion reservoir are sequentially deposited.

In some embodiments, to form the plurality of gaps, the cell element layer is double patterned, and the double-patterned cell element layer is etched through.

In some embodiments, to form the plurality of insulating structures, one or more dielectric layers are deposited on the plurality of cell elements and into the plurality of gaps to fill the plurality of gaps, and the deposited dielectric layers are planarized to expose the cell elements.

In some embodiments, after forming the plurality of insulating structures, a plurality of word lines are formed above and in contact with the plurality of cell elements.

According to yet another aspect of the present disclosure, a method for operating a memory device is disclosed. The memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. One of the memory cells is programmed to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines. The memory cell is programmed to a second threshold voltage by applying a second voltage pulse between the bit line and the word line. The memory cell is sensed at a sensing voltage between the first and second threshold voltages.

In some embodiments, the memory cell is programmed to be insulative by applying a third voltage pulse between the bit line and the word line. In some embodiments, a third polarity of the third voltage pulse is opposite to a first polarity of the first voltage pulse or a second polarity of the second voltage pulse.

In some embodiments, at least one of (i) a second amplitude of the second voltage pulse is greater than a first amplitude of the first voltage pulse, or (ii) a first width of the first voltage pulse is greater than a second width of the second voltage pulse, the second threshold voltage is greater than the first threshold voltage.

The foregoing description of the specific embodiments will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific embodiments, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary embodiments of the present disclosure as contemplated by the inventor (s) , and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises a cell element without a selector, and the cell element is configured to have a plurality of threshold voltages.
The memory device of claim 1, wherein the cell element comprises stacked a metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.
The memory device of claim 2, wherein the metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide.
The memory device of claim 2 or 3, wherein the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride.
The memory device of any one of claims 2-4, wherein the separator comprises a dielectric.
The memory device of claim 5, wherein the dielectric comprises at least one of silicon oxide, aluminum oxide, or gadolinium oxide.
The memory device of any one of claims 2-6, wherein a thickness of the solid electrolyte is between about 10 nm and about 100 nm, a thickness of the metal ion reservoir is between about 5 nm and about 50 nm, and a thickness of the separator is between about 1 nm and about 10 nm.
The memory device of any one of claims 2-7, wherein

when a first positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte, the cell element is configured to have a first threshold voltage of the plurality of threshold voltages;

when a second positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte, the cell element is configured to have a second threshold voltage of the plurality of threshold voltages; and

when a negative voltage pulse is applied from the solid electrolyte to the metal ion reservoir, the cell element is configured to be insulative.
The memory device of claim 8, wherein when at least one of (i) a second amplitude of the second positive voltage pulse is greater than a first amplitude of the first positive voltage pulse, or (ii) a first width of the first positive voltage pulse is greater than a second width of the second positive voltage pulse, the second threshold voltage is greater than the first threshold voltage.
The memory device of claim 1, wherein the cell element comprises doped arsenic selenide.
The memory device of claim 10, wherein the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.
The memory device of claim 10 or 11, wherein

when a first voltage pulse is applied across the cell element, the cell element is configured to have a first threshold voltage of the plurality of threshold voltages; and

when a second voltage pulse is applied across the cell element, the cell element is configured to have a second threshold voltage of the plurality of threshold voltages.
The memory device of claim 12, wherein when at least one of (i) a second amplitude of the second voltage pulse is greater than a first amplitude of the first voltage pulse, or (ii) a first width of the first voltage pulse is greater than a second width of the second voltage pulse, the second threshold voltage is greater than the first threshold voltage.
The memory device of any one of claims 1-13, wherein the plurality of word lines and the plurality of bit lines are in a cross-point architecture.
A memory device, comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises stacked a metal ion reservoir, a solid electrolyte, and a separator vertically between the metal ion reservoir and the solid electrolyte.
The memory device of claim 15, wherein

the metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide;

the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride; and

the separator comprises at least one of silicon oxide, aluminum oxide, or gadolinium oxide.
The memory device of claim 15 or 16, wherein

when a first positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte, the memory cell is configured to have a first threshold voltage;

when a second positive voltage pulse is applied from the metal ion reservoir to the solid electrolyte, the memory cell is configured to have a second threshold voltage; and

when a negative voltage pulse is applied from the solid electrolyte to the metal ion reservoir, the memory cell is configured to be insulative.
A memory device, comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises doped arsenic selenide.
The memory device of claim 18, wherein the arsenic selenide is doped with at least one of silver, copper, silicon, or germanium.
The memory device of claim 18 or 19, wherein

when a first voltage pulse is applied across the memory cell, the memory cell is configured to have a first threshold voltage; and

when a second voltage pulse is applied across the memory cell, the memory cell is configured to have a second threshold voltage.
A method for forming a memory device, comprising:

forming a cell element layer;

forming a plurality of gaps through the cell element layer to separate the cell element layer into a plurality of cell elements each configured to have a plurality of threshold voltages; and

forming a plurality of insulating structures in the plurality of gaps between the plurality of cell elements.
The method of claim 21, wherein forming the cell element layer comprises sequentially depositing layers of a solid electrolyte, a separator, and a metal ion reservoir.
The method of claim 22, wherein

the metal ion reservoir comprises at least one of silver, copper, silver sulfide, copper sulfide, silver selenide, or copper selenide;

the solid electrolyte comprises at least one of germanium selenide, germanium sulfide, silver selenide, silver sulfide, or copper telluride; and

the separator comprises at least one of silicon oxide, aluminum oxide, or gadolinium oxide.
The method of claim 21, wherein forming the cell element layer comprises:

depositing a layer of arsenic selenide; and

doping the layer of arsenic selenide with at least one of silver, copper, silicon, or germanium.
The method of any one of claims 21-24, wherein forming the plurality of gaps comprises:

double patterning the cell element layer; and

etching through the double-patterned cell element layer.
The method of any one of claims 21-25, wherein forming the plurality of insulating structures comprises:

depositing one or more dielectric layers on the plurality of cell elements and into the plurality of gaps to fill the plurality of gaps; and

planarizing the deposited dielectric layers to expose the plurality of cell elements.
The method of any one of claims 21-26, further comprising, after forming the plurality of insulating structures, forming a plurality of word lines above and in contact with the plurality of cell elements.
A method for operating a memory device, the memory device comprising a plurality of bit lines, a plurality of word lines, and a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines, the method comprising:

programming one of the memory cells to a first threshold voltage by applying a first voltage pulse between a respective one of the plurality of bit lines and a respective one of the plurality of word lines;

programming the memory cell to a second threshold voltage by applying a second voltage pulse between the bit line and the word line; and

sensing the memory cell at a sensing voltage between the first and second threshold voltages.
The method of claim 28, further comprising programming the memory cell to be insulative by applying a third voltage pulse between the bit line and the word line, wherein a third polarity of the third voltage pulse is opposite to a first polarity of the first voltage pulse or a second polarity of the second voltage pulse.
The method of claim 28 or 29, when at least one of (i) a second amplitude of the second voltage pulse is greater than a first amplitude of the first voltage pulse, or (ii) a first width of the first voltage pulse is greater than a second width of the second voltage pulse, the second threshold voltage is greater than the first threshold voltage.