WO2023004607A1

WO2023004607A1 - Phase-change memory devices with selector having defect reduction material and methods for forming the same

Info

Publication number: WO2023004607A1
Application number: PCT/CN2021/108803
Authority: WO
Inventors: Jun Liu; Shao-Fu Sanford Chu; Sannian SONG; Zhitang Song
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-07-28
Filing date: 2021-07-28
Publication date: 2023-02-02
Also published as: CN113795924A

Abstract

In certain aspects, a memory device includes a plurality of bit lines (104), a plurality of word lines (106), and a plurality of memory cells (108). Each of the plurality of memory cells (108) is disposed at an intersection of a respective one of the plurality of bit lines (104) and a respective one of the plurality of word lines (106). Each of the plurality of memory cells (108) includes stacked a phase-change memory (PCM) element (110) and a selector (112) having a defect reduction material.

Description

PHASE-CHANGE MEMORY DEVICES WITH SELECTOR HAVING DEFECT REDUCTION MATERIAL AND METHODS FOR FORMING THE SAME

BACKGROUND

The present disclosure relates to phase-change memory (PCM) devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. PCM array cells can be vertically stacked in 3D to form a 3D PCM.

SUMMARY

In one aspect, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of the plurality of memory cells is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes stacked a phase-change memory (PCM) element and a selector having a defect reduction material.

In another aspect of the present disclosure, a phase-change memory (PCM) cell includes a PCM element and a selector having a defect reduction material.

In still another aspect of the present disclosure, a method for forming a memory device includes depositing a selector using a deposition process and introducing a defect reduction material into the selector, and depositing a phase-change memory (PCM) element on the selector.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a perspective view of an exemplary 3D cross-point (XPoint) memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a side view of a cross-section of a 3D XPoint memory device having ovonic threshold switch (OTS) selectors.

FIG. 3 illustrates a side view of a cross-section of an exemplary 3D PCM device having OTS selectors with defect reduction material, according to some aspects of the present disclosure.

FIG. 4A illustrates a schematic of defects distribution in an exemplary OTS selector, according to some aspects of the present disclosure.

FIG. 4B illustrates a schematic of defects distribution in an exemplary OTS selector with defect reduction material, according to some aspects of the present disclosure.

FIG. 4C illustrates measured I-V characteristics of a 3D XPoint memory device having the exemplary OTS selector, according to some aspects of the present disclosure.

FIG. 4D illustrates measured I-V characteristics of another 3D XPoint memory device having the exemplary OTS selector with defect reduction material, according to some aspects of the present disclosure.

FIG. 4E illustrates measured I-V characteristics of yet another 3D XPoint memory device having the exemplary OTS selector with defect reduction material, according to some aspects of the present disclosure.

FIG. 4F illustrates diagrams of device speed tests of 3D XPoint memory devices having the exemplary OTS selector with defect reduction material, according to some aspects of the present disclosure.

FIG. 5 illustrates a schematic diagram of the operation of an exemplary array of PCM cells having OTS selectors, according to some aspects of the present disclosure.

FIGs. 6A-6C illustrate an exemplary fabrication process for forming a 3D PCM device having OTS selectors with defect reduction material, according to some aspects of the present disclosure.

FIG. 7 illustrates a flowchart of an exemplary method for forming a 3D PCM device having OTS selectors with defect reduction material, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some implementations, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other implementations whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layer thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “3D memory device” refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

A PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. PCM cells can be vertically stacked in 3D to form a 3D PCM.

3D PCMs include 3D cross-point (XPoint) memory, which stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable. For example, FIG. 1 illustrates a perspective view of an exemplary 3D XPoint memory device 100, according to some implementations of the present disclosure. 3D XPoint memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some implementations. 3D XPoint memory device 100 includes a plurality of parallel lower bit lines 102 in the same plane and a plurality of parallel upper bit lines 104 in the same plane above lower bit lines 102.3D XPoint memory device 100 also includes a plurality of parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally along the word line direction in the plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is noted that z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D XPoint memory device 100. The substrate (not shown) of 3D XPoint memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D XPoint memory device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

As shown in FIG. 1, 3D XPoint memory device 100 includes a plurality of memory cells 108 each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each memory cell 108 has a vertical square pillar shape. Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. Memory cells 108 in 3D XPoint memory device 100 are arranged in a memory array.

In existing 3D XPoint memory, the materials of selector 112 are ovonic threshold switch (OTS) materials, such as zinc telluride (ZnTe) , which exhibits a field-dependent volatile resistance switching behavior (known as “OTS phenomenon” ) when an external bias voltage (Va) higher than the threshold voltage is applied (Vth) . For example, FIG. 2 illustrates a side view of a cross-section of a 3D XPoint memory device 200 having OTS selectors. 3D XPoint memory device 200 includes a plurality of parallel bit lines 204 above a substrate 202 and a plurality of parallel word lines 216 above bit lines 204.3D XPoint memory device 200 also includes a plurality of memory cells 201 each disposed at an intersection of a respective pair of bit line 204 and word line 216. Adjacent memory cells 201 are separated by an insulating structure 203. Each memory cell 201 includes an OTS selector 208 and a PCM element 212 above OTS selector 208. Each memory cell 201 further includes three

electrodes

206, 210, and 214 vertically between a respective bit line 204, OTS selector 208, PCM element 212, and a respective word line 216, respectively.

OTS selector 208 includes an OTS material, such as ZnTe. At lower voltage (|Va| < Vth) , the high resistance of OTS selector 208 in its off-state keeps the off-state current (Ioff) low. At higher voltage (|Va| > Vth) , OTS selector 208 undergoes OTS phenomenon and switches to the on-state with low resistance; thus, the current through OTS selector 208 in the on-state (Ion) increases. The volatile on-state is maintained as long as high voltage is supplied. However, leakage current accumulated through all unselected memory cells 201 limits the scalability of array size. That is, the larger the array size is, the larger the overall leakage current is. Furthermore, leakage current issue also degrades the read operation margin when the accumulated leakage current is too large to set or reset unselected devices accidentally. Leakage current can also introduce parasitic resistance-related voltage that limits overall memory cell array size. A unique composition of selector and method of fabricating thereof to improve undesirable device leakage is proposed to address the above-mentioned challenges.

FIG. 3 illustrates a side view of a cross-section of an exemplary 3D PCM device 300 having selectors with defect reduction material, according to some implementations of the present disclosure. 3D PCM device 300, such as a 3D XPoint memory device, can include a plurality of bit lines 304 above a substrate 302, which can include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. Bit lines 304 can be parallel to one another and in the same plane. In some implementations, a plurality of parallel bit lines 304 each extends laterally in the y-direction (e.g., the bit line direction) in FIG. 3.3D PCM device 300 can further include a plurality of word lines 316 above bit lines 304. Word lines 316 can be parallel to one another and in the same plane. In some implementations, a plurality of parallel word lines 316 each extends laterally in the x-direction (e.g., the word line direction) in FIG. 3. Word lines 316 and bit lines 304 of 3D PCM device 300, such as a 3D XPoint memory device, can be perpendicularly arranged conductors in a cross-point architecture. Bit lines 304 and word lines 316 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each of bit lines 304 and word lines 316 includes a metal, such as tungsten.

In some implementations, 3D PCM device 300 includes a plurality of memory cells 301 each disposed at an intersection of a respective one of bit lines 304 and a respective one of word lines 316. Each memory cell 301 can be accessed individually by a current applied through a respective word line 316 and a respective bit line 304 in contact with memory cell 301. As shown in FIG. 3, 3D PCM device 300 can further include insulating structures 303 laterally between adjacent memory cells 301. In some implementations, each memory cell 301 has a vertical pillar shape (e.g., similar to memory cell 108 in FIG. 1) , and insulating structures 303 can extend laterally in both x-direction and y-direction to separate the pillar-shaped memory cells 301. In some implementations, insulating structure 303 includes one or more dielectric layers, such as an encapsulation layer (not shown) formed along the sidewalls of memory cells 301 and bit lines 304 and a capping layer (not shown) filling the remaining space between memory cells 301. The dielectric layers of insulating structures 303 can include dielectric materials, including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, low dielectric constant (low-k) dielectrics, or any combination thereof. In some implementations, the encapsulation layer and capping layer include silicon nitride and silicon oxide, respectively.

Each memory cell 301 can include stacked a PCM element 312, a selector 308, a first electrode 306 between bit line 304 and selector 308, a second electrode 310 between selector 308 and PCM element 312, and a third electrode 314 between PCM element 312 and word line 316. PCM element 312 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. Electrical currents can be applied to switch the phase-change material (or at least a fraction of it that blocks the current path) of PCM element 312 repeatedly between the two phases to store data. A single bit of data can be stored in each memory cell 301 and can be written or read by varying the voltage applied to a respective selector 308, which eliminates the need for transistors and replaces the conventional OTS selectors (e.g., OTS selector 208 in FIG. 2) . That is,

electrodes

310 and 314 can be arranged on opposite sides (e.g., above and below) of PCM element 312 to separate PCM element 312 from direct contacts with other components. It is understood that the structure of memory cell 301 is not limited to the example in FIG. 3 and may include any suitable structures. In one example, the relative positions of selector 308 and PCM element 312 may be switched in other examples. In another example, the number and relative positions of

electrodes

310 and 314 in memory cell 301 may vary in other examples as well.

The materials of PCM element 312 include chalcogenide-based alloys (chalcogenide glass) , such as germanium antimony telluride (GeSbTe or GST) alloy, or any other suitable phase-change materials, according to some implementations.

Electrodes

306, 310, and 314 can include conductive materials including, but not limited to, W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each of

electrodes

306, 310, and 314 includes carbon, such as amorphous carbon (a-C) .

As shown in FIG. 3, selector 308 includes defect reduction material 309 in FIG. 4B. In some implementations, the thickness of selector 308 is between 5 nm and 50 nm, such as between 5 nm and 50 nm (e.g., 5 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some implementations, the thickness of selector 308 is 30 nm.

Various implementations in accordance with the present disclosure provide 3D PCM devices, e.g., 3D XPoint memory device, having OTS selectors with defect reduction material, and fabrication method thereof. Compared with OTS selectors (e.g., 208 in FIG. 4A) , OTS selectors (e.g., 308 in FIG. 4B) with defect reduction material (e.g., 309 in FIG. 4B) can reduce leakage current and parasitic resistance-related voltage without significant impact to other critical material or electrical parameters, thereby improving read operation margin and enable larger cell array. For instance, the OTS selector (e.g., 208 in FIG. 4A) may have multiple highly distorted vacancy-like defects formed at grain boundaries, surfaces, and other areas of misfit resulting from the deposition of the material. These defects may have free carriers such as electrons or holes formed therein to provide additional leakage paths when voltage applied upon. The defect reduction material disclosed herein can be used to repair these dangling-bond defects, which leads to a significant improvement in the electronic properties such as reducing the leakage current without materially change the characteristics of the OTS selector. For instance, the OTS elector (e.g., 308 in FIG. 4B) may include an amorphous chalcogenide threshold switching material including Ge _xSe _yAs _zSi _t. And the defect reduction material (e.g., 309 in FIG. 4B) may include nitrogen (N) , carbon (C) , oxygen (O) , boron (B) , phosphorus (P) , sulfur (S) , or a combination thereof. For instance, nitrogen ions may be combined with the dangling-bond defects and filled into those vacancies to form a more stable configuration, in which it is strongly bonded to a Si atom or other atoms of Ge _xSe _yAs _zSi _t such that the free carriers cannot be easily moved through the lattice. In some implementations, selector 308 includes Ge _xSe _yAs _zSi _tN _s, where x is 0.03 to 0.2 (e.g., 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20) , y is 0.3 to 0.6 (e.g., 0.3, 0.4, 0.5, or 0.6) , z is 0.15 to 0.45 (e.g., 0.15, 0.20, 0.25, 0.30, 0.35, 0.40, or 0.45) , t is 0.02 to 0.20 (e.g., 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20) , and s is 0.005 to 0.1 (e.g., 0.005, 0.010, 0.015, 0.020, 0.025, 0.030, 0.035, 0.040, 0.045, 0.050, 0.055, 0.060, 0.065, 0.070, 0.075, 0.080, 0.085, 0.090, 0.095, or 0.100) . In some implementations, selector 308 includes Ge _xSe _yAs _zSi _tC _s, where x is 0.03 to 0.2 (e.g., 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20) , y is 0.3 to 0.6 (e.g., 0.3, 0.4, 0.5, or 0.6) , z is 0.15 to 0.45 (e.g., 0.15, 0.20, 0.25, 0.30, 0.35, 0.40, or 0.45) , t is 0.02 to 0.2 (e.g., 0.02, 0.03, 0.04, 0.05, 0.06, 0.07, 0.08, 0.09, 0.10, 0.11, 0.12, 0.13, 0.14, 0.15, 0.16, 0.17, 0.18, 0.19, or 0.20) , and s is 0.002 to 0.1 (e.g., 0.002, 0.004, 0.006, 0.008, 0.010, 0.015, 0.020, 0.025, 0.030, 0.035, 0.040, 0.045, 0.050, 0.055, 0.060, 0.065, 0.070, 0.075, 0.080, 0.085, 0.090, 0.095, or 0.100) . It is noted that x, y, z, t, and s are mole fraction of respective elements and that the sum of all mole fractions is always equal to 1.

FIGs. 4C-4E illustrate measured I-V characteristics of a 3D XPoint memory device having an OTS selector without or with defect reduction material (e.g., 309 in FIG. 4B) . For instance, FIG. 4C shows a reference 3D XPoint memory device having the exemplary OTS selector without defect reduction material, and FIG. 4D shows another 3D XPoint memory device having the exemplary OTS selector with defect reduction material, e.g., by introducing 4 standard cubic centimeters per minute (sccm) nitrogen gas (N ₂) airflow during sputter deposition of 30 nm threshold switching material of the selector. Also, FIG. 4E shows yet another 3D XPoint memory device having the exemplary OTS selector with defect reduction material, e.g., by introducing 8 sccm N ₂ airflow during sputter deposition of a 30 nm threshold switching material of the selector. As illustrated in FIGs. 4C-4E, the threshold voltage (Vth) is reduced, the leakage current is reduced approximately from between 10 ^-6 to 10 ^-7 to between 10 ^-7 to 10 ^-8 A (e.g., 1×10 ^-8, 2×10 ^-8, 3×10 ^-8, 4×10 ^-8, 5×10 ^-8, 6×10 ^-8, 7×10 ^-8, 8×10 ^-8, 9×10 ^-8, or any range bounded by the lower end by any of these values, or in any range defined by any two of these values) after introducing the defect reduction material into the selector. The hold voltage (Vhold) also increases, and the SET current remains at a similar level.

While it is important to reduce the leakage current of the selector, it is also important to retain the same or similar characteristics, especially when the memory device is used to replace Dynamic Random-Access Memory (DRAM) . That is, the switching speed cannot be reduced due to the implementation of the defect reduction material.

FIG. 4F illustrates diagrams of device speed tests of 3D XPoint memory devices having the exemplary OTS selector with defect reduction material, according to some implementations of the present disclosure. The upper three diagrams are diagrams of a device speed test when the selector of the device introducing 4 sccm N ₂ airflow during sputter deposition of 30 nm threshold switching material of the selector, as mentioned in FIG. 4D, and the lower three diagrams are diagrams of a device speed test when the selector of the device introducing 8 sccm N ₂ airflow during sputter deposition of 30 nm threshold switching material of the selector, as mentioned in FIG. 4E. It is shown in FIG. 4F that, after the voltage is applied to the device, the switching speed can be maintained. For instance, the SET speed of the memory device can remain 96 to 110 ns. And a RESET speed of the memory device can remain 12 to 14 ns, which means it is highly desirable that the switch speed remain the same or similar after introducing the defect reduction material into the selector.

FIG. 5 illustrates a schematic diagram of the operation of an exemplary array of PCM cells having selectors with defect reduction material, according to some implementations of the present disclosure. As shown in FIG. 5, an array of PCM cells 502 (e.g., corresponding to memory cells 301 in FIG. 3) can be formed as the intersections (cross-points) of word lines 504 (e.g., corresponding to word lines 316 in FIG. 3) and bit lines 506 (e.g., corresponding to bit lines 304 in FIG. 3) , respectively. Each PCM cell 502 can include a PCM element 508 (e.g., corresponding to PCM element 312 in FIG. 3) in series with a selector (e.g., corresponding to selector 308 in FIG. 3) . To operate the array of PCM cells 502, a word line voltage (Vw) having a value of either 0 or Vhh can be applied to each word line 504, and a bit line voltage (Vb) having a value of either 0 or Vll can be applied to each bit line 506. The voltage (Va) applied to each PCM cell 502 (and selector 510 thereof) can thus be either Vhh, –Vll, 0, or Vhh–Vll. In some implementations, Vhh and Vll are set based on the intrinsic threshold voltage (Vth) of selector 510, such that |Vhh–Vll| ≥ Vth > |Vhhl|, |Vll|, or 0. As shown in FIG. 5, the voltage (Va) is equal to or greater than the threshold voltage (Vth) at only one intersection of word line 504 and bit line 506 with non-zero voltages, according to some implementations. Thus, only PCM cell 502 (in the dotted circle in FIG. 5) at the intersection of the pair of word line 504 and bit line 506 with non-zero voltages can be selected (i.e., (applied with a voltage of Vhh–Vll and in the on-state) . Other PCM cells 502 are not selected and are in the off-state, according to some implementations.

FIGs. 6A–6C illustrate an exemplary fabrication process for forming a 3D PCM device having selectors with defect reduction material, according to some implementations of the present disclosure. FIG. 7 illustrates a flowchart of an exemplary method 700 for forming a 3D PCM device having selectors with defect reduction material, according to some implementations of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 6A–6C and 7 include 3D PCM device 300 depicted in FIG. 3. Examples of selectors with defect reduction material depicted in FIGs. 6A–6C and 7 include selector 308 with defect reduction material 309 depicted in FIG. 4B. FIGs. 6A–6C and 7 will be described together. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7.

Referring to FIG. 7, method 700 starts at operation 702, in which a bit line and a first electrode are deposited above a substrate sequentially. That is, the bit line is deposited on the substrate, and then the first electrode is deposited on the bit line. In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6A, a bit line 604 is formed on a substrate 602, and a first electrode 606 is formed on bit line 604. In some implementations, bit line 604 may include W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, first electrode 606 may include W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, first electrode 606 includes carbon, such as amorphous carbon (a-C) .

Method 700 proceeds to operation 704, as illustrated in FIG. 7, in which a selector is deposited on the first electrode using a sputter deposition, and a defect reduction material is introduced into the selector by using a sputter target or a reactive gas having the defect reduction material. In one example, the defect reduction material, such as N, is introduced into the selector by using a sputter target having the defect reduction material, such as silicon nitride (SiN) . In particular, during sputter deposition process, the first electrode, such as a-C, is placed in a vacuum chamber containing one or more inert gas, such as Ar gas, and a negative charge is applied to a sputter target, such as SiN, with other co-sputter target of threshold switching materials, such as Ge, Se, As, or Si, that will be deposited onto the first electrode to produce the desired thin film of, for example, Ge _xSe _yAs _zSi _tN _s. Free electrons flow from the negatively charged sputter target in the plasma environment, colliding with the outer electronic shell of the Ar gas atoms driving these electrons off due to their like charge. The inert gas atoms become positively charged ions attracted to the negatively charged target material at a very high velocity that sputters off atomic size particles from the sputter target due to the momentum of the collisions. These particles cross the vacuum deposition chamber are deposited as a thin film of material on the surface of the first electrode. In another example, the defect reduction material, such as nitrogen (N) , is introduced into the selector by using a reactive gas having the defect reduction material, such as N ₂ airflow. In particular, during sputter deposition process, the first electrode, such as a-C, is is placed in a vacuum chamber containing one or more inert gas, such as Ar gas to sputter off particles, and one or more reactive gas to be deposited, such as N ₂ gas, and a negative charge is applied to sputter target of threshold switching materials, such as Ge, Se, As, or Si, to produce the desired thin film of, for example, a thin film of Ge _xSe _yAs _zSi _tN _s. Free electrons flow from the negatively charged sputter target in the plasma environment, colliding with the outer electronic shell of the Ar gas atoms driving these electrons off due to their like charge. The inert gas atoms become positively charged ions attracted to the negatively charged target material at a very high velocity that sputters off atomic size particles from the sputter target due to the momentum of the collisions. These particles cross the vacuum deposition chamber, accompany with atoms or ions of the reactive gas, are deposited as a thin film of material on the surface of the first electrode. As mentioned above, atoms or ions N may be introduced and combined with the dangling bonds of other materials of the selector and thus reduce the dangling bond defects. In yet another example, the defect reduction material, such as carbon (C) , is introduced into the selector by using a sputter target having the defect reduction material, such as C target or silicon carbide (SiC) target. In some implementations, the defect reduction material may include N, C, O, B, P, S, or a combination thereof. In some implementations, the sputter target includes SiN, SiC, C, or a combination thereof. In some implementations, the reactive gas includes N ₂. In some implementations, the selector is deposited on the first electrode using a chemical vapor deposition (CVD) , and the defect reduction material is introduced into the selector by using a volatile precursor having the defect reduction material. In one example, the defect reduction material, such as N, is introduced into the selector by using a volatile precursor having the defect reduction material, such as N ₂ airflow. In particular, during CVD process, the first electrode, such as a-C, is exposed to one or more volatile precursors, such as N ₂, and other volatile precursors of threshold switching materials, such as Ge, Se, As, or Si, which react and/or decompose on a surface of the first electrode to produce the desired thin film of, for example, a thin film of Ge _xSe _yAs _zSi _tN _s.

Referring to FIG. 6B, a selector 608 is formed on first electrode 606 using sputter deposition, and a defect reduction material (e.g., 309 in FIG. 4B) is introduced into the selector 608 by using a sputter target or a reactive gas having the defect reduction material.

Method 700 proceeds to operation 706, as illustrated in FIG. 7, in which a second electrode, a PCM element, and a third electrode are deposited on the selector sequentially. In some implementations, the deposition of the second electrode, the PCM element, and the third electrode may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

Referring to FIG. 6C, a second electrode 610, a PCM element 612, and a third electrode 614 are deposited on selector 608 sequentially. In some implementations, PCM element 612 may include a chalcogenide-based alloy. Second electrode 610 and third electrode 614 may include W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof.

Method 700 proceeds to operation 708, as illustrated in FIG. 7, in which a word line is deposited on the third electrode, and thus the memory device (e.g., 300 in FIG. 3) is formed. The deposition of the word line on the third electrode may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

According to one aspect of the present disclosure, a memory device includes a plurality of bit lines, a plurality of word lines, and a plurality of memory cells. Each of a plurality of memory cells is disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines. Each of the plurality of memory cells includes stacked a phase-change memory (PCM) element and a selector having a defect reduction material.

In some implementations, the defect reduction material includes at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.

In some implementations, the selector includes a chalcogenide threshold switching material.

In some implementations, the selector includes Ge _xSe _yAs _zSi _tN _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.10.

In some implementations, the selector includes Ge _xSe _yAs _zSi _tC _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.002 to 0.10.

In some implementations, a thickness of the selector is between 10 nm and 50 nm.

In some implementations, the defect reduction material is configured to fill dangling bond defects of the selector.

In some implementations, a SET speed of the memory device is 96 to 110 ns.

In some implementations, a RESET speed of the memory device is 12 to 14 ns.

In some implementations, a leakage current of the memory device at SET operation is less than 10 ^-7 A.

In some implementations, the plurality of word lines and the plurality of bit lines are in a cross-point architecture.

In some implementations, each of the plurality of memory cells further includes a first electrode vertically between the selector and the respective bit line, a second electrode vertically between the PCM element and the selector, and a third electrode vertically between the PCM element and the respective word line.

According to another aspect of the present disclosure, a phase-change memory (PCM) cell includes a PCM element, and a selector having a defect reduction material.

According to still another aspect of the present disclosure, a method for forming a memory device includes depositing a selector using a deposition process and introducing a defect reduction material into the selector, and depositing a phase-change memory (PCM) element on the selector.

In some implementations, the deposition process includes a physical vapor deposition (PVD) , and the introducing the defect reduction material includes using a sputter target or a reactive gas having the defect reduction material.

In some implementations, the sputter target includes silicon-based material with the defect reduction material.

In some implementations, the sputter target includes at least one of silicon nitride (SiN) , silicon carbide (SiC) , or carbon (C) .

In some implementations, the reactive gas includes nitrogen gas (N ₂) .

In some implementations, the deposition process includes a chemical vapor deposition (CVD) , and the introducing the defect reduction material includes using a volatile precursor having the defect reduction material.

In some implementations, the method further includes sequentially depositing a bit line and a first electrode on a substrate, sequentially depositing a second electrode, the PCM element, and a third electrode on the selector, and forming a word line on the third electrode. The selector is deposited on the first electrode.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Implementations of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary implementations of the present disclosure as contemplated by the inventor (s) , and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A memory device, comprising:

a plurality of bit lines;

a plurality of word lines; and

a plurality of memory cells each disposed at an intersection of a respective one of the plurality of bit lines and a respective one of the plurality of word lines,

wherein each of the plurality of memory cells comprises stacked a phase-change memory (PCM) element and a selector having a defect reduction material.
The memory device of claim 1, wherein the defect reduction material comprises at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.
The memory device of claim 1 or 2, wherein the selector comprises a chalcogenide threshold switching material.
The memory device of any one of claims 1-3, wherein the selector comprises Ge _xSe _yAs _zSi _tN _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.10.
The memory device of any one of claims 1-3, wherein the selector comprises Ge _xSe _yAs _zSi _tC _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.002 to 0.10.
The memory device of any one of claims 1-5, wherein a thickness of the selector is between 10 nm and 50 nm.
The memory device of any one of claims 1-6, wherein the defect reduction material is configured to:

fill dangling bond defects of the selector.
The memory device of any one of claims 1-7, wherein a SET speed of the memory device is 96 to 110 ns.
The memory device of any one of claims 1-8, wherein a RESET speed of the memory device is 12 to 14 ns.
The memory device of any one of claims 1-9, wherein a leakage current of the memory device at SET operation is less than 10 ^-7 A.
The memory device of any one of claims 1-10, wherein the plurality of word lines and the plurality of bit lines are in a cross-point architecture.
The memory device of any one of claims 1-11, wherein each of the plurality of memory cells further comprises a first electrode vertically between the selector and the respective bit line, a second electrode vertically between the PCM element and the selector, and a third electrode vertically between the PCM element and the respective word line.
A phase-change memory (PCM) cell, comprising:

a PCM element; and

a selector having a defect reduction material.
The PCM cell of claim 13, wherein the defect reduction material comprises at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.
The PCM cell of claim 13 or 14, wherein the selector comprises a chalcogenide threshold switching material.
The PCM cell of any one of claims 13-15, wherein the selector comprises Ge _xSe _yAs _zSi _tN _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.10.
The PCM cell of any one of claims 13-16, wherein the selector comprises Ge _xSe _yAs _zSi _tC _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.002 to 0.10.
The PCM cell of any one of claims 13-17, wherein a thickness of the selector is between 10 nm and 50 nm.
The PCM cell of any one of claims 13-18, wherein the defect reduction material is configured to:

fill dangling bond defects of the selector.
A method for forming a memory device, comprising:

depositing a selector using a deposition process and introducing a defect reduction material into the selector; and

depositing a phase-change memory (PCM) element on the selector.
The method of claim 20, wherein the deposition process comprises a physical vapor deposition (PVD) , and the introducing the defect reduction material includes using a sputter target or a reactive gas having the defect reduction material.
The method of claim 21, wherein the sputter target comprises silicon-based material with the defect reduction material.
The method of claim 21 or 22, wherein the sputter target comprises at least one of silicon nitride (SiN) , silicon carbide (SiC) , or carbon (C) .
The method of any one of claims 21-23, wherein the reactive gas comprises nitrogen gas (N ₂) .
The method of claim 20, wherein the deposition process comprises a chemical vapor deposition (CVD) , and the introducing the defect reduction material includes using a volatile precursor having the defect reduction material.
The method of any one of claims 20-25, wherein the defect reduction material comprises at least one of nitrogen, carbon, oxygen, boron, phosphorus, or sulfur.
The method of any one of claims 20-26, wherein the selector comprises a chalcogenide threshold switching material.
The method any one of claims 20-27, wherein the selector comprises Ge _xSe _yAs _zSi _tN _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.005 to 0.10.
The method of any one of claims 20-28, wherein the selector comprises Ge _xSe _yAs _zSi _tC _s, where x is 0.03 to 0.20, y is 0.30 to 0.60, z is 0.15 to 0.45, t is 0.02 to 0.20, and s is 0.002 to 0.10.
The method any one of claims 20-29, further comprising:

sequentially depositing a bit line and a first electrode on a substrate, wherein the selector is deposited on the first electrode;

sequentially depositing a second electrode, the PCM element, and a third electrode on the selector; and

forming a word line on the third electrode.