WO2023087131A1

WO2023087131A1 - Phase-change memory device and method for forming the same

Info

Publication number: WO2023087131A1
Application number: PCT/CN2021/130837
Authority: WO
Inventors: Haibo YANG; Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2023-05-25
Also published as: CN114270520A

Abstract

In certain aspects, a three-dimensional (3D) phase-change memory (PCM) device includes a first PCM cell, a first shrunken PCM cell on the first PCM cell, a second shrunken PCM cell on the first shrunken PCM cell, and a second PCM cell on the second shrunken PCM cell. The first PCM cell includes a first PCM element, the first shrunken PCM cell includes a first shrunken PCM element, the second shrunken PCM cell includes a second shrunken PCM element, and the second PCM cell includes a second PCM element. A width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.

Description

PHASE-CHANGE MEMORY DEVICE AND METHOD FOR FORMING THE SAME

BACKGROUND

The present disclosure relates to phase-change memory (PCM) devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithm, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A three-dimensional (3D) memory architecture can address the density limitation in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. PCM array cells can be vertically stacked in 3D to form a 3D PCM device.

SUMMARY

In one aspect, a three-dimensional (3D) phase-change memory (PCM) device includes a first PCM cell, a first shrunken PCM cell on the first PCM cell, a second shrunken PCM cell on the first shrunken PCM cell, and a second PCM cell on the second shrunken PCM cell. The first PCM cell includes a first PCM element, the first shrunken PCM cell includes a first shrunken PCM element, the second shrunken PCM cell includes a second shrunken PCM element, and the second PCM cell includes a second PCM element. A width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.

In another aspect, a three-dimensional (3D) phase-change memory (PCM) device includes one or more first PCM cells, each including a first PCM element, one or more first shrunken PCM cells on the respective one or more first PCM cells, each including a first shrunken PCM element, one or more second shrunken PCM cells on the respective one or more first shrunken PCM cells, each including a second shrunken PCM element, and one or more second PCM cells on the respective one or more second shrunken PCM cells, each including a second PCM element. A width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.

In yet another aspect, a method for forming a three-dimensional (3D) phase-change memory (PCM) device includes depositing one or more first PCM cells on one or more first bit lines, each first PCM cell including a first PCM element, sequentially depositing one or more first word lines and one or more first shrunken PCM cells on the respective one or more first PCM cells, each first shrunken PCM cell including a first shrunken PCM element, sequentially depositing one or more second bit lines and one or more second shrunken PCM cells on the respective one or more first shrunken PCM cells, each second shrunken PCM cell including a second shrunken PCM element, sequentially depositing one or more second word lines and one or more second PCM cells on the respective one or more second shrunken PCM cells, each second PCM cell including a second PCM element, and depositing one or more third bit lines on the respective one or more second PCM cells.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 illustrates a perspective view of an exemplary 3D phase-change memory (PCM) memory device, according to some aspects of the present disclosure.

FIG. 2 illustrates a side view of a cross-section of a 3D PCM memory device, according to some aspects of the present disclosure.

FIG. 3 illustrates a perspective view of an exemplary 3D PCM device with stacked PCM cells, according to some aspects of the present disclosure.

FIG. 4 illustrates a side view of a cross-section of an exemplary 3D PCM device with shrunken PCM cells, according to some aspects of the present disclosure.

FIG. 5 illustrates a comparison result of resistance changes over operation time between a 3D PCM device with the same cell size and a 3D PCM device with modified cell size, according to some aspects of the present disclosure.

FIGs. 6A-6D illustrate an exemplary fabrication process for forming an exemplary 3D PCM device with shrunken PCM cells, according to some aspects of the present disclosure.

FIG. 7 illustrates a flowchart of an exemplary method for forming an exemplary 3D PCM device with shrunken PCM cells, according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one embodiment, ” “an embodiment, ” “an example embodiment, ” “some implementations, ” etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same embodiment. Further, when a particular feature, structure or characteristic is described in connection with an embodiment, it would be within the knowledge of a person skilled in the pertinent art to affect such feature, structure or characteristic in connection with other implementations whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on”something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “3D” memory device or PCM device refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

A PCM can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials (e.g., chalcogenide alloys) based on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell can be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of it that blocks the current path) repeatedly between the two phases to store data. PCM cells can be vertically stacked in 3D to form a 3D PCM device. 3D PCM device stores data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable.

With the development of 3D memory devices, such as 3D PCM devices, more cells (e.g., PCM cells) are stacked to increase the density of the 3D memory device. However, the issue of high power consumption, cell-to-cell variation, and data retention loss become major constraints for more stacks of memory cells. With regard to power consumption, especially in a PCM array, the thermal crosstalk between neighboring memory cells undesirably raises the temperature of the nearby unselected memory cells when a selected memory cell is programmed with a program voltage. The program voltage, after multiple and continuous programming operations, may accumulatively increase the threshold voltage of the nearby unselected memory cells. It leads to an adverse impact that a higher programming voltage is required to program these unselected memory cells being affected. In particular, when it comes to more than two stacks of memory cells (e.g., four stacks of memory cells) , the inner cells are capped between two outer cells. The capped inner cells may retain and accumulate more heat inside and therefore result in more thermal crosstalk effects and deteriorate power performance. Moreover, with regard to cell-to-cell variation, especially the variation in a vertical direction, the temperature varies between the outer cell and the inner cell vertically due to the heat dissipation as mentioned above. That is, the characteristic of the cells may be changed because of the temperature they are in. Finally, data retention time is also affected by the terminally-activated crystallization of the amorphous PCM material. The more amorphous volume is kept in the PCM element, the more data retention time at the array level can be achieved. That is, the high temperature of the amorphous PCM material creates the possibility of crystallization which reduces the stability of data retention.

To address one or more of the aforementioned issues, the present disclosure introduces a solution in which inner cells of the PCM device may be reduced in thickness and/or width such that the thermal crosstalk is reduced laterally. Also, by reducing the thickness of the PCM cell, the amorphous volume can be kept, thus increasing the data retention time at the array level. Furthermore, by reducing the thickness of the inner cells while maintaining the thickness of the outer cells, the temperature variation is reduced, thus minimizing the cell-to-cell variation affected by the temperature. Moreover, with the reduced thickness of the PCM cell, the Resistive-capacitive (RC) delay may also be improved during reset operation. Finally, as the thickness of the PCM cell is reduced, the crystallization temperature is increased, and the thermal boundary resistance (TBR) is more prominent. TBR is found to enforce a temperature profile that minimizes overheating in the center of the active region of the PCM cell while favoring the formation of an amorphous volume. This phase distribution results in the minimum reset current, which is highly desirable for power consumption and data retention. The present disclosure also provides a method of stacking multiple PCM cells including the shrunken PCM cells and connecting these PCM cells with common bit lines or word lines.

FIG. 1 illustrates a perspective view of an exemplary 3D PCM device 100, according to some implementations of the present disclosure. 3D PCM device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors, according to some implementations. 3D PCM device 100 includes one or more parallel lower bit lines 102 in the same plane and one or more parallel upper bit lines 104 in the same plane above lower bit lines 102.3D PCM device 100 also includes one or more parallel word lines 106 in the same plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally along with the word line direction in the plan view. Each word line 106 is intersected with each lower bit line 102 and each upper bit line 104 in the plan view. In some implementations, each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that the x and y axes are included in FIG. 1 to illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is noted that the z-axis is also included in FIG. 1 to further illustrate the spatial relationship of the components in 3D PCM device 100. The substrate (not shown) of 3D PCM device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D PCM device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationships is applied throughout the present disclosure.

As shown in FIG. 1, 3D PCM device 100 includes one or more PCM cells 108 each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each PCM cell 108 has a vertical square pillar shape. Each PCM cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each PCM cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each PCM cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each PCM cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. PCM cells 108 in 3D PCM device 100 are arranged in a memory array.

FIG. 2 illustrates a side view of a cross-section of an exemplary 3D PCM memory device 200, according to some aspects of the present disclosure. In FIG. 2, 3D PCM memory device 200 includes a substrate 202, one or more parallel bit lines 211 formed on substrate 202, and one or more parallel word lines 221 formed above bit lines 211. Substrate 202 may include silicon (e.g., single crystalline silicon) , silicon germanium (SiGe) , gallium arsenide (GaAs) , germanium (Ge) , silicon on insulator (SOI) , or any other suitable materials. Bit lines 211 and word lines 221 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each of bit lines 211 and word lines 221 includes a metal, such as tungsten.

3D PCM memory device 200 may be divided by isolation layer 218 to form one or more separated pillar-shaped PCM cells 201. In some implementations, each pillar-shaped PCM cell 201 is disposed at an intersection of a respective one of bit lines 211 and a respective one of word lines 221. Each pillar-shaped PCM cell 201 may be accessed individually by a current applied through a respective word line 221 and a respective bit line 211 in contact with pillar-shaped PCM cell 201. Each pillar-shaped PCM cell 201 has a vertical pillar shape (e.g., similar to PCM cell 108 in FIG. 1) , and isolation layer 218 may extend laterally in both x-direction and y-direction to separate pillar-shaped PCM cells 201.

Each pillar-shaped PCM cell 201 includes a first electrode 2071 formed on bit line 211, a selector 205 formed on first electrode 2071, and a second electrode 2072 formed on selector 205. Pillar-shaped PCM cell 201 further includes a PCM element 203 formed on second electrode 2072, and a third electrode 2073 formed on PCM element 203. First electrode 2071, selector 205, and second electrode 2072 are functioned and used as a selector in pillar-shaped PCM cell 201. Second electrode 2072, PCM element 203, and third electrode 2073 function are used as storage elements in pillar-shaped PCM cell 201. It is understood that second electrode 2072 is used as a common electrode in both the selector and the storage element.

First electrode 2071 is formed on bit line 211 and is in contact with selector 205, so that first electrode 2071 serves as a current path and may be formed of a conductive material. In some implementations, first electrode 2071 may be a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations, first electrode 2071 may be a titanium nitride (TiN) layer, but the present disclosure is not limited thereto.

Selector 205 is formed on first electrode 2071, and the resistance of selector 205 is changed in response to a selection voltage applied between first electrode 2071 and second electrode 2072. In some implementations, selector 205 may be an ovonic threshold switch (OTS) device made of at least one of oxygen (O) , sulfur (S) , selenium (Se) , tellurium (Te) , germanium (Ge) , antimony (Sb) , silicon (Si) , or arsenic (As) . The OTS device is formed by OTS material exhibiting an OTS property. With regard to the function of selector 205 including the OTS material, when a voltage lower than a threshold voltage Vth is applied between first electrode 2071 and second electrode 2072, selector 205 may be in a high-resistance state preventing a current from flowing therethrough, and when a voltage higher than the threshold voltage Vth is applied between first electrode 2071 and second electrode 2072, selector 205 may be in a low-resistance state, allowing a current to flow therethrough.

Second electrode 2072 is formed between the selector and the storage element and functions as one of the electrodes of both the selector and the storage element, so second electrode 2072 should be formed by a thermally and electrically insulating material to reduce temperature and electrical interference from the selector and the storage element. Second electrode 2072 may be formed of or include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations, second electrode 2072 may be a titanium nitride (TiN) layer or any suitable conductive layer. In some implementations, second electrode 2072 may be formed by amorphous carbon.

PCM element 203 is formed on second electrode 2072. PCM element 203 is a material whose phase can be reversibly switched between amorphous and crystalline states, depending on a heating time. In general, PCM element 203 may exist in an amorphous and one or sometimes several crystalline phases and can be rapidly and repeatedly switched between these phases. In some implementations, PCM element 203 may include a material whose phase can be reversibly changed using Joule’s heat, which is generated when a voltage is applied between second electrode 2072 and third electrode 2073, and the resistance of PCM element 203 may be changed by such a change in phase. In some implementations, PCM element 203 may include a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) . In some implementations, PCM element 203 may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe) , or TeGeSbS. In some implementations, PCM element 203 may be GeSbTe.

Third electrode 2073 is formed on PCM element 203. In some implementations, the material of third electrode 2073 may be similar to the material of first electrode 2071 or second electrode 2072. In some implementations, the material of third electrode 2073 may be similar to the material of second electrode 2072. Then, word line 221 is formed on third electrode 2073.

It is understood that the position of bit lines 211 and word line 221 corresponding to pillar-shaped PCM cell 201 may be exchanged according to different memory designs. In other words, first electrode 2071 may be formed on a word line, and a bit line may be formed on third electrode 2073.

FIG. 3 illustrates a perspective view of an exemplary 3D PCM device 300 with stacked PCM cells, according to some aspects of the present disclosure. 3D PCM device 300 includes a lower bit line 321, a middle bit line 323 above lower bit line 321, and an upper bit line 325 above middle bit line 323.3D PCM device 300 also includes a lower word line 341 vertically between lower bit line 321 and middle bit line 323, and an upper word line 343 vertically between middle bit line 323 and upper bit line 325. As shown in FIG. 3, each of

bit lines

321, 323, and 325 extends laterally along the bit line direction (e.g., in the x-direction) in the plan view, and each of

word lines

341 and 343 extends laterally along the word line direction (e.g., in the y-direction) in the plan view. Each of

word lines

341 and 343 is intersected with each of

bit lines

321, 323, and 325 in the plan view. In some implementations, each of

word lines

341 and 343 is perpendicular to each of

bit lines

321, 323, and 325.

As shown in FIG. 3, 3D PCM device 300 further includes a first PCM cell 311 disposed at an intersection of lower bit line 321 and lower word line 341, a second PCM cell 331 disposed at an intersection of lower word line 341 and a middle bit line 323, a third PCM cell 351 disposed at an intersection of middle bit line 323 and an upper word line 343, and a fourth PCM cell 371 disposed at an intersection of upper word line 343 and an upper bit line 325. Each of

PCM cells

311, 331, 351, and 371 has a vertical pillar shape. Each of

PCM cells

311, 331, 351, and 371 includes at least a PCM element and a selector stacked vertically. Each of

PCM cells

311, 331, 351, and 371 stores a single bit of data and can be written or read by varying the voltage applied to a respective selector, which replaces the need for transistors. First PCM cell 311 is accessed individually by a current applied through the top and bottom conductors in contact with first PCM cell 311, e.g., lower word line 341 and lower bit line 321. Second PCM cell 331 is accessed individually by a current applied through, e.g., middle bit line 323 and lower word line 341. Third PCM cell 351 is accessed individually by a current applied through, e.g., upper word line 343 and middle bit line 323. Fourth PCM cell 371 is accessed individually by a current applied through, e.g., upper bit line 325 and upper word line 343. Each of

PCM cells

311, 331, 351, and 371 in 3D PCM device 300 are arranged in a memory array. In some implementations, first PCM cell 311 and fourth PCM cell 371 are outer PCM cells, e.g., a first outer PCM cell and a second outer PCM cell. Second PCM cell 331 and third PCM cell 351 are inner PCM cells, e.g., a first inner PCM cell and a second inner PCM cell. In some implementations, each of the first inner PCM cells and the second inner PCM cells can include a shrunken PCM cell which will be discussed later.

FIG. 4 illustrates a side view of a cross-section of an exemplary 3D PCM device 400 with shrunken PCM cells, according to some aspects of the present disclosure. 3D PCM device 400 includes a lower bit line 421, a middle bit line 423 above lower bit line 421, and an upper bit line 425 above middle bit line 423.3D PCM device 400 also includes a lower word line 441 vertically between lower bit line 421 and middle bit line 423, and an upper word line 443 vertically between middle bit line 423 and upper bit line 425. As shown in FIG. 4, each of

bit lines

421, 423, and 425 extends laterally along the bit line direction (e.g., in the x-direction) , and each of

word lines

441 and 443 extends laterally along the word line direction (e.g., in the y-direction) . Each of

word lines

441 and 443 is intersected with each of

bit lines

421, 423, and 425. In some implementations, each of

word lines

441 and 443 is perpendicular to each of

bit lines

421, 423, and 425. In some implementations,

bit lines

421, 423, and 425, and

word lines

441 and 443 can include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicide, or any combination thereof. In some implementations, each of

bit lines

421, 423, and 425, and

word lines

441 and 443 includes a metal, such as tungsten.

As shown in FIG. 4, 3D PCM device 400 further includes a first outer PCM cell 411 disposed at an intersection of lower bit line 421 and lower word line 441, a first shrunken PCM cell 431 disposed at an intersection of lower word line 441 and a middle bit line 423, a second shrunken PCM cell 451 disposed at an intersection of middle bit line 423 and an upper word line 443, and a second outer PCM cell 471 disposed in an intersection of upper word line 443 and an upper bit line 425. Each of

PCM cells

411, 431, 451, and 471 has a vertical pillar shape. Each of

PCM cells

411, 431, 451, and 471 includes at least a PCM element and a selector stacked vertically. Each of

PCM cells

411, 431, 451, and 471 stores a single bit of data and can be written or read by varying the voltage applied to a respective selector, which replaces the need for transistors. First outer PCM cell 411 is accessed individually by a current applied through the top and bottom conductors in contact with first outer PCM cell 411, e.g., lower word line 441 and lower bit line 421. First shrunken PCM cell 431 is accessed individually by a current applied through, e.g., middle bit line 423 and lower word line 441. Second shrunken PCM cell 451 is accessed individually by a current applied through, e.g., upper word line 443 and middle bit line 423. Second outer PCM cell 471 is accessed individually by a current applied through, e.g., upper bit line 425 and upper word line 443. Each of

PCM cells

411, 431, 451, and 471 in 3D PCM device 400 are arranged in a memory array. In some implementations, 3D PCM device 400 may include multiple inner shrunken PCM cells (e.g., first shrunken PCM cell 431 and second shrunken PCM cell 451) between two outer PCM cells (e.g., first outer PCM cell 411 and second outer PCM cell 471) . For example, 3D PCM device 400 may include four inner shrunken PCM cells between two outer PCM cells. In some implementations, the size of the outer PCM cell may be a baseline for all the PCM cells, and the size of shrunken PCM cell is smaller than that of the outer PCM cell. It is noted that each shrunken PCM cell may be smaller in size including both the PCM element and the selector, or it may be smaller in size only in the PCM element. It is also noted that the shrunken PCM cell may refer to a PCM cell with reduced thickness, width, or both.

Specifically, first outer PCM cell 411 include a first bottom electrode 4171 formed on lower bit line 421, a first selector 415 formed on first bottom electrode 4171, a first middle electrode 4172 formed on first selector 415, a first PCM element 413 formed on first middle electrode 4172, and a first top electrode 4173 formed on first PCM element 413. In some implementations, a first adhesive layer or a pair of first adhesive layers 419 may be formed on, below, or both first PCM element 413 to increase the electrical contact or reduce the stress between PCM element and electrodes. First shrunken PCM cell 431 includes a second bottom electrode 4371 formed on lower word line 441, a second selector 435 formed on second bottom electrode 4371, a second middle electrode 4372 formed on second selector 435, a first shrunken PCM element 433 formed on second middle electrode 4372, and a second top electrode 4373 formed on first shrunken PCM element 433. In some implementations, a second adhesive layer or a pair of second adhesive layers 439 may be formed on, below, or both first shrunken PCM element 433 to increase the electrical contact or reduce the stress between PCM element and electrodes. In some implementations, the thickness of the first PCM element 413 is larger than that of first shrunken PCM element 433. In some implementations, the thickness of first PCM element 413 may be 5 to 20 percent, for example, 10 percent more than that of first shrunken PCM element 433. In some implementations, the width of first PCM element 413 is larger than that of first shrunken PCM element 433. In some implementations, the width of first PCM element 413 may be 5 to 20 percent, for example, 10 percent more than that of first shrunken PCM element 433. In some implementations, the thickness of the second PCM element of second PCM cell 471 may be the same as that of first PCM element 413. In some implementations, the width of the second shrunken PCM element of second shrunken PCM cell 451 may be the same as that of first shrunken PCM element 433. Therefore, the width of first PCM element 413 is larger than that of the first shrunken PCM element 433, and the width of the second PCM element of second PCM cell 471 is larger than that of the second shrunken PCM element of second shrunken PCM cell 451. Also, the thickness of first PCM element 413 is larger than that of the first shrunken PCM element 433, and the thickness of the second PCM element of second PCM cell 471 is larger than that of the second shrunken PCM element of second shrunken PCM cell 451.

In some implementations,

electrodes

4171, 4172, 4173, 4371, 4372, and 4373 may include a metal, a conductive metal nitride, a conductive metal oxide, or combinations thereof. In some implementations,

electrodes

4171, 4172, 4173, 4371, 4372, and 4373 may include a titanium nitride (TiN) layer. In some implementations, first middle electrode 4172 and second middle electrode 4372 may be formed by amorphous carbon. The other electrodes in

PCM cells

411, 431, 451, and 471 may include the same or similar materials as

electrodes

4171, 4172, 4173, 4371, 4372, and 4373.

In some implementations,

selectors

415 and 435 may be an ovonic threshold switch (OTS) device made of at least one of oxygen (O) , sulfur (S) , selenium (Se) , tellurium (Te) , germanium (Ge) , antimony (Sb) , silicon (Si) , or arsenic (As) . The OTS device is formed by OTS material exhibiting an OTS property. The other selectors in

PCM cells

411, 431, 451, and 471 may include the same or similar materials as first selector 415 and second selector 435.

In some implementations, first PCM element 413 and first shrunken PCM element 433 may include a chalcogenide composition including at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) . In some implementations, first PCM element 413 and first shrunken PCM element 433 may be a binary (two-element) compound such as GaSb, InSb, InSe, SbTe, or GeTe, a ternary (three-element) compound such as GeSbTe, GaSeTe, InSbTe, SnSbTe, or InSbGe, or a quaternary (four-element) compound such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe) , or TeGeSbS. In some implementations, first PCM element 413 and first shrunken PCM element 433 may be GeSbTe. The other PCM elements and shrunken PCM elements in

PCM cells

411, 431, 451, and 471 may include the same or similar materials as first PCM element 413 and first shrunken PCM element 433. In some implementations, the crystallization temperature PCM elements of inner cells (e.g., first shrunken PCM element 433 of first shrunken PCM cell 431) may be higher than that of first PCM element 433. In some implementations, the crystallization temperature of the PCM elements of the inner cells (e.g., first shrunken PCM element 433 of first shrunken PCM cell 431) may be maintained between 800-900 K during programming operations. In some implementations, the PCM elements of the inner cells (e.g., first shrunken PCM element 433 of first shrunken PCM cell 431) may be further doped with carbon (C) while the PCM elements of the outer cells (e.g., first PCM element 413 of first outer PCM cell 411) may not be doped with carbon or may be doped with less carbon than that of first shrunken PCM element 433, such that the crystallization temperature of first shrunken PCM element 433 may be higher than that of first PCM element 433.

It is understood that the position of

bit lines

421, 423, and 425 and

word lines

441 and 443 corresponding to

PCM cells

411, 431, 451, and 471 may be exchanged according to different memory designs. In other words, first bottom electrode 4171 may be formed on a word line, and a bit line may be formed on first top electrode 4173.

Furthermore, a first isolation layer 418 may be formed on sidewalls of first outer PCM cell 411, and a second isolation layer 438 may be formed on sidewalls of first shrunken PCM cell 431. Since first shrunken PCM cell 431 may be reduced in width, the width of second isolation layer 438 may be larger than that of first isolation layer 418. In some implementations, a lateral distance between shrunken PCM cells (e.g., first shrunken PCM cell 431 and its laterally nearby shrunken PCM cells) is larger than that of between outer PCM cells (e.g., first outer PCM cell 411 and its laterally nearby PCM cells) . In some implementations, a material of isolation layers 418 and 438 may include at least one of silicon nitride (Si ₃N ₄) , silicon dioxide (SiO ₂) , aluminum nitride (AlN) , or aluminum oxide (Al ₂O ₃) .

FIG. 5 illustrates a comparison result of resistance changes over operation time between a 3D PCM device with the same cell size and a 3D PCM device with modified cell size, according to some aspects of the present disclosure. According to FIG. 5, a 3D PCM device including a stack of four PCM cells with the same cell size may have a decline in resistance over operation time since the thermal crosstalk and data retention issue. The crystallization in the amorphous phase accumulated during the continuous operation results in a drop in resistance over time. On the other hand, with modified cell size as provided in the present disclosure, the decline in resistance over operation time has been reduced significantly. In particular, since the inner cells with thickness reduction reduce the reset program pulse amplitude requirement for reach amorphous temperature, the fewer thermal crosstalk to neighbor cell is transmitted and thus, the retention margin is enlarged. Meanwhile, the crystallization temperature of inner cells increases with the reduced thickness and therefore increases the intrinsic retention time.

FIGs. 6A-6D illustrate an exemplary fabrication process for forming an exemplary 3D PCM device with shrunken PCM cells, according to some aspects of the present disclosure. And FIG. 7 illustrates a flowchart of an exemplary method for forming the exemplary 3D PCM device with shrunken PCM cells, according to some aspects of the present disclosure. Examples of the 3D PCM device depicted in FIGs. 6A–6D and 7 include 3D PCM device 400 depicted in FIG. 4. FIGs. 6A–6D and 7 will be described together. It is understood that the operations shown in method 700 are not exhaustive and that other operations can be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed simultaneously, or in a different order than shown in FIG. 7.

Referring to FIG. 7, method 700 starts at operation 702, in which one or more first PCM cells are deposited on one or more first bit lines, and each of the one or more first PCM cells includes a first PCM element. For example, as in FIG. 6A, one or more first PCM cells (e.g., a first PCM cell 611) are deposited on one or more first bit lines (e.g., a first bit line 621) . In some implementations, the one or more first bit lines (e.g., first bit line 621, which may correspond to lower bit line 421 in FIG. 4) and the one or more first PCM cells (e.g., first PCM cell 611, which may correspond to first outer PCM cell 411 in FIG. 4) may be formed on a substrate (e.g., corresponding to substrate 202 in FIG. 2) . To form first PCM cell 611 having first PCM element 613 on first bit line 621, a first bottom electrode (e.g., corresponding to first bottom electrode 4171 in FIG. 4) is deposited on first bit line 621, a first selector (e.g., corresponding to first selector 415 in FIG. 4) is deposited on the first bottom electrode, a first middle electrode (e.g., corresponding to first middle electrode 4172 in FIG. 4) , a first PCM element 613 (e.g., corresponding to first PCM element 413 in FIG. 4) is deposited on the first middle electrode, a first top electrode (e.g., corresponding to first top electrode 4173 in FIG. 4) is deposited on first PCM element 613. In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. In some implementations, first PCM cell 611 is formed by depositing a first PCM stack (not shown) and etching the first PCM stack in a vertical direction (e.g., z-direction) to form the one or more first PCM cells (e.g., first PCM cell 611) . The etching process includes wet etching, dry etching, or a combination thereof.

Referring to FIG. 7, method 700 proceeds to operation 704, in which one or more first word lines and one or more first shrunken PCM cells are sequentially deposited on the respective one or more first PCM cells, each first shrunken PCM cell includes a first shrunken PCM element. For example, as in FIG. 6B, one or more first word lines (e.g., a first word line 641) and one or more first shrunken PCM cells (e.g., a first shrunken PCM cell 631) are sequentially deposited on the respective one or more first PCM cells including first PCM cell 611. Each of the one or more first shrunken PCM cells (e.g., first shrunken PCM cell 631) includes a first shrunken PCM element 633. To form first shrunken PCM cell 631 having first shrunken PCM element 633 on first word line 641, a second bottom electrode (e.g., corresponding to second bottom electrode 4371 in FIG. 4) is deposited on first word line 641, a second selector (e.g., corresponding to second selector 435 in FIG. 4) is deposited on the second bottom electrode, a second middle electrode (e.g., corresponding to second middle electrode 4372 in FIG. 4) , a first shrunken PCM element 633 (e.g., corresponding to first shrunken PCM element 433 in FIG. 4) is deposited on the second middle electrode, a second top electrode (e.g., corresponding to second top electrode 4373 in FIG. 4) is deposited on first shrunken PCM element 633. In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. In some implementations, first shrunken PCM cell 631 is formed by depositing a second PCM stack (not shown) and etching the second PCM stack in a vertical direction (e.g., z-direction) to form one or more first shrunken PCM cells (e.g., first shrunken PCM cell 631) . The etching process includes wet etching, dry etching, or a combination thereof.

In some implementations, the width of each second trenches 663 etching through the second PCM stack is larger than the width of each first trenches 661 etching through the first PCM stack. Therefore, first shrunken PCM cell 631 has a smaller width than first PCM cell 611.

Referring to FIG. 7, method 700 proceeds to operation 706, in which one or more second bit lines and one or more second shrunken PCM cells are sequentially deposited on the respective one or more first shrunken PCM cells. For example, as in FIG. 6C, one or more second bit lines (e.g., a second bit line 623) and one or more second shrunken PCM cells (e.g., a second shrunken PCM cell 651) are sequentially deposited on the respective one or more first shrunken PCM cells (e.g., first shrunken PCM cell 631) . The forming of second shrunken PCM cell 651 having second shrunken PCM element 653 is similar to the forming of first shrunken PCM cell 631 having first shrunken PCM element 633. In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. In some implementations, second shrunken PCM cell 651 is formed by depositing a third PCM stack (not shown) and etching the third PCM stack in a vertical direction (e.g., z-direction) to form one or more second shrunken PCM cells (e.g., second shrunken PCM cell 651) . The etching process includes wet etching, dry etching, or a combination thereof.

In some implementations, the width of each third trenches 665 etching through the third PCM stack is larger than the width of each first trenches 661 etching through the first PCM stack. Therefore, second shrunken PCM cell 651 has a smaller width than first PCM cell 611. In some implementations, the width of each third trenches 665 etching through the third PCM stack is the same as the width of each second trenches 663 etching through the second PCM stack. Therefore, second shrunken PCM cell 651 has the same width as first shrunken PCM cell 631.

Referring to FIG. 7, method 700 proceeds to operation 708, in which one or more second word lines and one or more second PCM cells are sequentially formed on the respective one or more second shrunken PCM cells. For example, as in FIG. 6D, one or more second word lines (e.g., a second word line 643) and one or more second PCM cells (e.g., a second PCM cell 671) are sequentially deposited on the respective one or more second shrunken PCM cells (e.g., second shrunken PCM cell 651) . The forming of second PCM cell 671 having second PCM element 673 is similar to the forming of first PCM cell 611 having first PCM element 613. In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. In some implementations, second PCM cell 671 is formed by depositing a fourth PCM stack (not shown) and etching the fourth PCM stack in a vertical direction (e.g., z-direction) to form one or more second PCM cells (e.g., second PCM cell 671) . The etching process includes wet etching, dry etching, or a combination thereof.

In some implementations, the width of each fourth trenches 667 etching through the fourth PCM stack is smaller than the width of each third trenches 665 etching through the third PCM stack. Therefore, second PCM cell 671 has a larger width than second shrunken PCM cell 651. In some implementations, the width of each fourth trenches 667 etching through the fourth PCM stack is the same as the width of each first trenches 661 etching through the first PCM stack. Therefore, second PCM cell 671 has the same width as first shrunken PCM cell 631.

Referring to FIG. 7, method 700 proceeds to operation 710, in which one or more third bit lines is formed on the one or more second PCM cells. For example, as shown in FIG. 6D, one or more third bit lines (e.g., a third bit line 625) are deposited on the respective one or more second PCM cells (e.g., second PCM cell 671) . In some implementations, the deposition may include using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof.

According to one aspect of the present disclosure, a three-dimensional (3D) phase-change memory (PCM) device includes a first PCM cell, a first shrunken PCM cell on the first PCM cell, a second shrunken PCM cell on the first shrunken PCM cell, and a second PCM cell on the second shrunken PCM cell. The first PCM cell includes a first PCM element, the first shrunken PCM cell includes a first shrunken PCM element, the second shrunken PCM cell includes a second shrunken PCM element, and the second PCM cell includes a second PCM element. A width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.

In some implementations, the width of the first PCM element is 5 to 20 percent more than that of the first shrunken PCM element, and the width of the second PCM element is 5 to 20 percent more than that of the second shrunken PCM element.

In some implementations, a thickness of the first PCM element is larger than that of the first shrunken PCM element, and a thickness of the second PCM element is larger than that of the second shrunken PCM element.

In some implementations, the thickness of the first PCM element is 5 to 20 percent more than that of the first shrunken PCM element, and the thickness of the second PCM element is 5 to 20 percent more than that of the second shrunken PCM element.

In some implementations, a width of the first PCM cell is larger than that of the first shrunken PCM cell, and a width of the second PCM cell is larger than that of the second shrunken PCM cell.

In some implementations, a width of the first shrunken PCM cell is the same as that of the second shrunken PCM cell, and the width of the second PCM cell is the same as that of the first PCM cell.

In some implementations, a crystallization temperature of the first shrunken PCM element is higher than that of the first PCM element.

In some implementations, a material of the first PCM element and the first shrunken PCM element includes a chalcogenide composition comprising at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .

In some implementations, the first shrunken PCM element is doped with carbon (C) , and the first shrunken PCM element is not doped with carbon or is doped with less carbon than that of the first shrunken PCM element.

In some implementations, the 3D PCM device further includes a lower bit line, a lower word line, a middle bit line, an upper word line, an upper bit line. The first PCM cell is formed between the lower bit line and the lower word line, the first shrunken PCM cell is formed between the lower word line and the middle bit line, the second shrunken PCM cell is formed between the middle bit line and the upper word line, and the second PCM cell is formed between the upper word line and the upper bit line.

In some implementations, the lower bit line is intersected with the lower word line, the lower word line is intersected with the middle bit line, the middle bit line is intersected with the upper word line, and the upper word line is intersected with the upper bit line in the plan view.

In some implementations, the first PCM cell includes a first bottom electrode formed on the lower bit line, a first selector formed on the first bottom electrode, a first middle electrode formed on the first selector, the first PCM element formed on the first middle electrode, and a first top electrode formed on the first PCM element. The first shrunken PCM cell includes a second bottom electrode formed on the lower word line, a second selector formed on the second bottom electrode, a second middle electrode formed on the second selector, the first shrunken PCM element formed on the second middle electrode, and a second top electrode formed on the first shrunken PCM element.

In some implementations, the 3D PCM device further includes a pair of first adhesive layers formed on and below the first PCM element, and a pair of second adhesive layers formed on and below the first shrunken PCM element.

In some implementations, the 3D PCM device further includes a first isolation layer formed on sidewalls of the first PCM cell, and a second isolation layer formed on sidewalls of the first shrunken PCM cell.

According to another aspect of the present disclosure, a three-dimensional (3D) phase-change memory (PCM) device includes one or more first PCM cells, each including a first PCM element, one or more first shrunken PCM cells on the respective one or more first PCM cells, each including a first shrunken PCM element, one or more second shrunken PCM cells on the respective one or more first shrunken PCM cells, each including a second shrunken PCM element, and one or more second PCM cells on the respective one or more second shrunken PCM cells, each including a second PCM element. A width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.

In some implementations, the width of the first shrunken PCM cell is the same as that of the second shrunken PCM cell, and the width of the second PCM cell is the same as that of the first PCM cell.

In some implementations, a material of the first PCM element and the first shrunken PCM element comprises a chalcogenide composition comprising at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .

In some implementations, the 3D PCM device further includes one or more lower bit lines, one or more lower word lines, one or more middle bit lines, one or more upper word lines, and one or more upper bit lines. The first PCM cell is formed between a respective lower bit line of the one or more lower bit lines and a respective lower word line of the one or more lower word lines, the first shrunken PCM cell is formed between the respective lower word line of the one or more lower word lines and a respective middle bit line of the one or more middle bit lines, the second shrunken PCM cell is formed between the respective middle bit line of the one or more middle bit lines and a respective upper word line of the one or more upper word lines, and the second PCM cell is formed between the respective upper word line of the one or more upper word lines and a respective upper bit line of the one or more upper bit lines.

In some implementations, the one or more lower bit lines are intersected with the respective one or more lower word lines, the one or more lower word lines are intersected with the respective one or more middle bit lines, the one or more middle bit lines are intersected with of the respective one or more upper word lines, and the one or more upper word lines are intersected with the respective one or more upper bit lines in a plan view.

In some implementations, the 3D PCM device further includes one or more first isolation layers separating the one or more first PCM cells, and one or more second isolation layers separating the one or more first shrunken PCM cells.

According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) phase-change memory (PCM) device includes depositing one or more first PCM cells on respective one or more first bit lines, each first PCM cell including a first PCM element, sequentially depositing one or more first word lines and one or more first shrunken PCM cells on the respective one or more first PCM cells, each first shrunken PCM cell including a first shrunken PCM element, sequentially depositing one or more second bit lines and one or more second shrunken PCM cells on the respective one or more first shrunken PCM cells, each second shrunken PCM cell including a second shrunken PCM element, sequentially depositing one or more second word lines and one or more second PCM cells on the respective one or more second shrunken PCM cells, each second PCM cell including a second PCM element, and depositing one or more third bit lines on the respective one or more second PCM cells.

In some implementations, the method further includes depositing the one or more first bit lines on a substrate before depositing the one or more first PCM cells on the one or more first bit lines.

In some implementations, depositing of the one or more first PCM cells includes depositing a first PCM stack and etching the first PCM stack in a vertical direction to form the one or more first PCM cells. Depositing of the one or more first shrunken PCM cells includes depositing a second PCM stack and etching the second PCM stack in the vertical direction to form the one or more first shrunken PCM cells. Depositing of the one or more second shrunken PCM cells includes depositing a third PCM stack and etching the third PCM stack in the vertical direction to form the one or more second shrunken PCM cells. Depositing of the one or more second shrunken PCM cells includes depositing a fourth PCM stack and etching the fourth PCM stack in the vertical direction to form the one or more second PCM cells.

In some implementations, a width of each second trenches etching through the second PCM stack is larger than a width of each first trenches etching through the first PCM stack, and a width of each third trenches etching through the third PCM stack is larger than a width of each fourth trenches etching through the fourth PCM stack.

In some implementations, the width of each third trenches etching through the third PCM stack is the same as the width of each second trenches etching through the second PCM stack, and the width of each first trenches etching through the first PCM stack is the same as the width of each fourth trenches etching through the fourth PCM stack.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Implementations of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all exemplary implementations of the present disclosure as contemplated by the inventor (s) , and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary implementations, but should be defined only in accordance with the following claims and their equivalents.

Claims

A three-dimensional (3D) phase-change memory (PCM) device, comprising:

a first PCM cell;

a first shrunken PCM cell on the first PCM cell;

a second shrunken PCM cell on the first shrunken PCM cell; and

a second PCM cell on the second shrunken PCM cell, wherein the first PCM cell comprises a first PCM element, the first shrunken PCM cell comprises a first shrunken PCM element, the second shrunken PCM cell comprises a second shrunken PCM element, and the second PCM cell comprises a second PCM element, and wherein a width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.
The 3D PCM device of claim 1, wherein the width of the first PCM element is 5 to 20 percent more than that of the first shrunken PCM element, and the width of the second PCM element is 5 to 20 percent more than that of the second shrunken PCM element.
The 3D PCM device of claim 1 or 2, wherein a thickness of the first PCM element is larger than that of the first shrunken PCM element, and a thickness of the second PCM element is larger than that of the second shrunken PCM element.
The 3D PCM device of claim 3, wherein the thickness of the first PCM element is 5 to 20 percent more than that of the first shrunken PCM element, and the thickness of the second PCM element is 5 to 20 percent more than that of the second shrunken PCM element.
The 3D PCM device of any one of claims 1-4, wherein a width of the first PCM cell is larger than that of the first shrunken PCM cell, and a width of the second PCM cell is larger than that of the second shrunken PCM cell.
The 3D PCM device of any one of claims 1-5, wherein the width of the first shrunken PCM cell is the same as that of the second shrunken PCM cell, and the width of the second PCM cell is the same as that of the first PCM cell.
The 3D PCM device of any one of claims 1-6, wherein a crystallization temperature of the first shrunken PCM element is higher than that of the first PCM element.
The 3D PCM device of any one of claims 1-7, wherein a material of the first PCM element and the first shrunken PCM element comprises a chalcogenide composition comprising at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .
The 3D PCM device of any one of claims 1-8, wherein the first shrunken PCM element is doped with carbon (C) , and the first shrunken PCM element is not doped with carbon or is doped with less carbon than that of the first shrunken PCM element.
The 3D PCM device of any one of claims 1-9, further comprising:

a lower bit line;

a lower word line;

a middle bit line;

an upper word line; and

an upper bit line, wherein the first PCM cell is formed between the lower bit line and the lower word line, the first shrunken PCM cell is formed between the lower word line and the middle bit line, the second shrunken PCM cell is formed between the middle bit line and the upper word line, and the second PCM cell is formed between the upper word line and the upper bit line.
The 3D PCM device of claim 10, wherein the lower bit line is intersected with the lower word line, the lower word line is intersected with the middle bit line, the middle bit line is intersected with the upper word line, and the upper word line is intersected with the upper bit line in a plan view.
The 3D PCM device of claim 11, wherein the first PCM cell comprises:

a first bottom electrode formed on the lower bit line,

a first selector formed on the first bottom electrode,

a first middle electrode formed on the first selector,

the first PCM element formed on the first middle electrode, and

a first top electrode formed on the first PCM element, and wherein the first shrunken PCM cell comprises:

a second bottom electrode formed on the lower word line,

a second selector formed on the second bottom electrode,

a second middle electrode formed on the second selector,

the first shrunken PCM element formed on the second middle electrode, and

a second top electrode formed on the first shrunken PCM element.
The 3D PCM device of any one of claims 1-12, further comprising:

a pair of first adhesive layers formed on and below the first PCM element; and

a pair of second adhesive layers formed on and below the first shrunken PCM element.
The 3D PCM device of any one of claims 1-13, further comprising:

a first isolation layer formed on sidewalls of the first PCM cell; and

a second isolation layer formed on sidewalls of the first shrunken PCM cell.
A three-dimensional (3D) phase-change memory (PCM) device, comprising:

one or more first PCM cells, each comprising a first PCM element;

one or more first shrunken PCM cells on the respective one or more first PCM cells, each comprising a first shrunken PCM element;

one or more second shrunken PCM cells on the respective one or more first shrunken PCM cells, each comprising a second shrunken PCM element; and

one or more second PCM cells on the respective one or more second shrunken PCM cells, each comprising a second PCM element, wherein a width of the first PCM element is larger than that of the first shrunken PCM element, and a width of the second PCM element is larger than that of the second shrunken PCM element.
The 3D PCM device of claim 15, wherein the width of the first PCM element is 5 to 20 percent more than that of the first shrunken PCM element, and the width of the second PCM element is 5 to 20 percent more than that of the second shrunken PCM element.
The 3D PCM device of claim 15 or 16, wherein a thickness of the first PCM element is larger than that of the first shrunken PCM element, and a thickness of the second PCM element is larger than that of the second shrunken PCM element.
The 3D PCM device of claim 17, wherein the thickness of the first PCM element is 5 to 20 percent more than that of the first shrunken PCM element, and the thickness of the second PCM element is 5 to 20 percent more than that of the second shrunken PCM element.
The 3D PCM device of any one of claims 15-18, wherein a width of the first PCM cell is larger than that of the first shrunken PCM cell, and a width of the second PCM cell is larger than that of the second shrunken PCM cell.
The 3D PCM device of any one of claims 15-19, wherein the width of the first shrunken PCM cell is the same as that of the second shrunken PCM cell, and the width of the second PCM cell is the same as that of the first PCM cell.
The 3D PCM device of any one of claims 15-20, wherein a crystallization temperature of the first shrunken PCM element is higher than that of the first PCM element.
The 3D PCM device of any one of claims 15-21, wherein a material of the first PCM element and the first shrunken PCM element comprises a chalcogenide composition comprising at least one of germanium (Ge) , antimony (Sb) , tellurium (Te) , indium (In) , or gallium (Ga) .
The 3D PCM device of any one of claims 15-22, wherein the first shrunken PCM element is doped with carbon (C) , and the first shrunken PCM element is not doped with carbon or is doped with less carbon than that of the first shrunken PCM element.
The 3D PCM device of any one of claims 15-23, further comprising:

one or more lower bit lines;

one or more lower word lines;

one or more middle bit lines;

one or more upper word lines; and

one or more upper bit lines, wherein the first PCM cell is formed between a respective lower bit line of the one or more lower bit lines and a respective lower word line of the one or more lower word lines, the first shrunken PCM cell is formed between the respective lower word line of the one or more lower word lines and a respective middle bit line of the one or more middle bit lines, the second shrunken PCM cell is formed between the respective middle bit line of the one or more middle bit lines and a respective upper word line of the one or more upper word lines, and the second PCM cell is formed between the respective upper word line of the one or more upper word lines and a respective upper bit line of the one or more upper bit lines.
The 3D PCM device of claim 24, wherein the one or more lower bit lines are intersected with the respective one or more lower word lines, the one or more lower word lines are intersected with the respective one or more middle bit lines, the one or more middle bit lines are intersected with the respective one or more upper word lines, and the one or more upper word lines are intersected with of the respective one or more upper bit lines in a plan view.
The 3D PCM device of any one of claims 15-25, further comprising:

one or more first isolation layers separating the one or more first PCM cells; and

one or more second isolation layers separating the one or more first shrunken PCM cells.
A method for forming a three-dimensional (3D) phase-change memory (PCM) device, comprising:

depositing one or more first PCM cells on one or more first bit lines, each first PCM cell comprising a first PCM element;

sequentially depositing one or more first word lines and one or more first shrunken PCM cells on the respective one or more first PCM cells, each first shrunken PCM cell comprising a first shrunken PCM element;

sequentially depositing one or more second bit lines and one or more second shrunken PCM cells on the respective one or more first shrunken PCM cells, each second shrunken PCM cell comprising a second shrunken PCM element;

sequentially depositing one or more second word lines and one or more second PCM cells on the respective one or more second shrunken PCM cells, each second PCM cell comprising a second PCM element; and

depositing one or more third bit lines on the respective one or more second PCM cells.
The method of claim 27, further comprising:

depositing the one or more first bit lines on a substrate before depositing the one or more first PCM cells on the respective one or more first bit lines.
The method of claim 27 or 28, wherein depositing of the one or more first PCM cells comprises:

depositing a first PCM stack and etching the first PCM stack in a vertical direction to form the one or more first PCM cells, wherein depositing of the one or more first shrunken PCM cells comprises:

depositing a second PCM stack and etching the second PCM stack in the vertical direction to form the one or more first shrunken PCM cells, wherein depositing of the one or more second shrunken PCM cells comprises:

depositing a third PCM stack and etching the third PCM stack in the vertical direction to form the one or more second shrunken PCM cells, and wherein depositing of the one or more second shrunken PCM cells comprises:

depositing a fourth PCM stack and etching the fourth PCM stack in the vertical direction to form the one or more second PCM cells.
The method of claim 29, wherein a width of each second trenches etching through the second PCM stack is larger than a width of each first trenches etching through the first PCM stack, and wherein a width of each third trenches etching through the third PCM stack is larger than a width of each fourth trenches etching through the fourth PCM stack.
The method of claim 30, wherein the width of each third trenches etching through the third PCM stack is the same as the width of each second trenches etching through the second PCM stack, and wherein the width of each first trenches etching through the first PCM stack is the same as the width of each fourth trenches etching through the fourth PCM stack.