CN114270520A

CN114270520A - Phase change memory device and method of forming the same

Info

Publication number: CN114270520A
Application number: CN202180004640.8A
Authority: CN
Inventors: 杨海波; 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2021-11-16
Filing date: 2021-11-16
Publication date: 2022-04-01
Also published as: WO2023087131A1

Abstract

In a particular aspect, a three-dimensional (3D) Phase Change Memory (PCM) device includes a first PCM cell, a first punctured PCM cell on the first PCM cell, a second punctured PCM cell on the first punctured PCM cell, and a second PCM cell on the second punctured PCM cell. The first PCM cell includes a first PCM element, the first punctured PCM cell includes a first punctured PCM element, the second punctured PCM cell includes a second punctured PCM element, and the second PCM cell includes a second PCM element. The width of the first PCM element is greater than the width of the first punctured PCM element and the width of the second PCM element is greater than the width of the second punctured PCM element.

Description

Phase change memory device and method of forming the same

Technical Field

The present disclosure relates to a phase-change memory (PCM) device and a method of manufacturing the same.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of memory cells approaches the lower limit, planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.

Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripherals for controlling signals to and from the memory array. For example, based on electrothermal heating and quenching of a phase change material, PCMs may utilize the difference between the resistivities of the amorphous and crystalline phases in the phase change material. PCM array cells may be vertically stacked in 3D to form a 3D PCM device.

Disclosure of Invention

In one aspect, a three-dimensional (3D) Phase Change Memory (PCM) device includes a first PCM cell, a first punctured PCM cell on the first PCM cell, a second punctured PCM cell on the first punctured PCM cell, and a second PCM cell on the second punctured PCM cell. The first PCM cell includes a first PCM element, the first punctured PCM cell includes a first punctured PCM element, the second punctured PCM cell includes a second punctured PCM element, and the second PCM cell includes a second PCM element. The width of the first PCM element is greater than the width of the first punctured PCM element and the width of the second PCM element is greater than the width of the second punctured PCM element.

In another aspect, a three-dimensional (3D) Phase Change Memory (PCM) device includes: one or more first PCM cells, each first PCM cell comprising a first PCM element; one or more first punctured PCM cells on a respective one or more first PCM cells, each first punctured PCM cell comprising a first punctured PCM element; one or more second punctured PCM cells on the respective one or more first punctured PCM cells, each second punctured PCM cell including a second punctured PCM element; and one or more second PCM cells on the respective one or more second punctured PCM cells, each second PCM cell including a second PCM element. The width of the first PCM element is greater than the width of the first punctured PCM element and the width of the second PCM element is greater than the width of the second punctured PCM element.

In yet another aspect, a method for forming a three-dimensional (3D) Phase Change Memory (PCM) device includes: depositing one or more first PCM cells on the one or more first bit lines, each first PCM cell comprising a first PCM element; sequentially depositing one or more first wordlines and one or more first punctured PCM cells, each first punctured PCM cell comprising a first punctured PCM element, on a respective one or more first PCM cells; sequentially depositing one or more second bitlines and one or more second punctured PCM cells on the corresponding one or more first punctured PCM cells, each second punctured PCM cell comprising a second punctured PCM element; sequentially depositing one or more second wordlines and one or more second PCM cells, each comprising a second PCM element, on the respective one or more second shrunk PCM cells; and depositing one or more third bitlines over the respective one or more second PCM cells.

Drawings

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.

Fig. 1 illustrates a perspective view of an example 3D Phase Change Memory (PCM) memory device, according to some aspects of the present disclosure.

Fig. 2 illustrates a side view of a cross section of a 3D PCM memory device in accordance with some aspects of the present disclosure.

Fig. 3 illustrates a perspective view of an example 3D PCM device having stacked PCM cells according to some aspects of the present disclosure.

Fig. 4 illustrates a side view of a cross section of an example 3D PCM device having a collapsed PCM cell according to some aspects of the present disclosure.

Fig. 5 illustrates a comparison result of resistance variation over operation time between a 3D PCM device having the same cell size and a 3D PCM device having a modified cell size according to some aspects of the present disclosure.

Fig. 6A-6D illustrate an exemplary fabrication process for forming an exemplary 3D PCM device having a shrunk PCM cell according to some aspects of the present disclosure.

Fig. 7 illustrates a flow diagram of an example method for forming an example 3D PCM device with a punctured PCM cell according to some aspects of the present disclosure.

The present disclosure will be described with reference to the accompanying drawings.

Detailed Description

While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Accordingly, one skilled in the relevant art will appreciate that: other configurations and arrangements may be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some implementations," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other implementations whether or not explicitly described.

Generally, terms may be understood at least in part from their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey a singular use or a plural use, depending, at least in part, on the context. In addition, the term "based on" may be understood as not necessarily intending to express an exclusive set of factors, but may allow for the presence of other factors not necessarily explicitly described, again depending at least in part on the context.

It should be readily understood that the meaning of "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest way such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "on … …" or "above … …" means not only "on something" or "above something", but may also include the meaning of "it is on something" or "it is above something" with no intervening features or layers therebetween (i.e., directly on something).

Further, spatially relative terms, such as "below … …," "below … …," "below," "over … …," "on," and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature(s) as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure, or may have an extent less than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogenous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term "3D" memory device or PCM device refers to a semiconductor device having memory cells that may be vertically arranged on a laterally oriented substrate such that the number of memory cells may be increased in a vertical direction relative to the substrate. As used herein, the term "perpendicular" refers to nominally perpendicular to a lateral surface of a substrate.

Based on electrothermal heating and quenching of phase change materials (e.g., chalcogenide alloys), PCMs may utilize the difference between the resistivities of the amorphous and crystalline phases in the phase change material. Phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least a portion of the material's blocking current path) between the two phases to store data. The PCM cells may be vertically stacked in 3D to form a 3D PCM device. 3D PCM devices store data based on changes in resistance of bulk material properties (e.g., in a high resistance state or a low resistance state) in conjunction with a stackable cross-point data access array capable of bit addressing.

As 3D memory devices (e.g., 3D PCM devices) evolve, more cells (e.g., PCM cells) are stacked to increase the density of the 3D memory devices. However, the problems of high power consumption, cell-to-cell variation (cell-to-cell variation) and data retention loss are major limitations for more stacks of memory cells. With respect to power consumption, particularly in PCM arrays, thermal cross-talk between adjacent memory cells can undesirably raise the temperature of nearby unselected memory cells when selected memory cells are programmed by a programming voltage. After a number of successive programming operations, the program voltage may increase the threshold voltage of nearby unselected memory cells in an accumulative manner. This results in the adverse effect of requiring higher programming voltages to program the affected unselected memory cells. In particular, when more than two storage cell stacks are involved (e.g., four storage cell stacks), the inner unit is capped between the two outer units. The capped inner unit may hold and accumulate more heat internally and thus cause more thermal cross-talk effects and reduced power performance. Further, regarding the inter-cell variation, particularly the variation in the vertical direction, the temperature between the external cell and the internal cell varies in the vertical direction due to the heat dissipation as described above. That is, the characteristics of the cells may change due to the temperature at which they are exposed. Finally, the data retention time is also affected by the thermally activated crystallization of the amorphous PCM material. The more amorphous volume held in the PCM element, the longer the data retention time at the array level can be achieved. That is, the high temperature of the amorphous PCM material may create a possibility of crystallization, which may decrease stability of data retention.

To address one or more of the above issues, the present disclosure introduces a solution in which the thickness and/or width of the internal cells of the PCM device may be reduced such that thermal crosstalk is laterally reduced. Furthermore, by reducing the thickness of the PCM cell, amorphous volume may be maintained, thereby increasing data retention time at the array level. Furthermore, by reducing the thickness of the inner unit while maintaining the thickness of the outer unit, temperature variation is reduced, thereby minimizing temperature-affected inter-unit variation. Furthermore, as the thickness of the PCM cell is reduced, resistance-capacitance (RC) delay may also be improved during a reset operation. Finally, as the PCM cell thickness decreases, the crystallization temperature increases, and the Thermal Boundary Resistance (TBR) becomes more prominent. It has been found that TBR achieves a temperature profile that minimizes overheating in the center of the active area of the PCM cell while also facilitating the formation of amorphous volume. This phase distribution contributes to a minimum reset current, which is very desirable for power consumption and data retention. The present disclosure also provides a method of stacking a plurality of PCM cells, including a punctured PCM cell, and connecting the PCM cells to a common bit line or word line.

Fig. 1 illustrates a perspective view of an exemplary 3D PCM device 100 according to some embodiments of the present disclosure. According to some embodiments, the 3D PCM device 100 has a transistor-less cross-point architecture that positions memory cells at the intersections of vertical conductors. The 3D PCM device 100 includes one or more parallel lower bit lines (lower bit lines) 102 in the same plane and one or more parallel upper bit lines (upper bit lines) 104 in the same plane above the lower bit lines 102. The 3D PCM device 100 also includes one or more parallel wordlines 106 vertically located between the lower bitline 102 and the upper bitline 104 in the same plane. As shown in fig. 1, each lower bitline 102 and each upper bitline 104 extend laterally (parallel to the wafer plane) in plan view along a bitline direction, and each wordline 106 extends laterally along a wordline direction in plan view. In a plan view, each word line 106 intersects each lower bit line 102 and each upper bit line 104. In some embodiments, each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It should be noted that the x and y axes are included in fig. 1 to show two orthogonal directions in the wafer plane. The x-direction is the word line direction and the y-direction is the bit line direction. It should be noted that the z-axis is also included in fig. 1 to further illustrate the spatial relationship of components in 3D PCM device 100. The substrate (not shown) of the 3D PCM device 100 comprises two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to both the x and y axes. As used herein, when a substrate is located in a lowermost plane of a semiconductor device (e.g., 3D PCM device 100) in a z-direction (a vertical direction perpendicular to an x-y plane), it is determined in the z-direction whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device) relative to the substrate of the semiconductor device. Throughout this disclosure, the same concepts are applied to describe spatial relationships.

As shown in fig. 1, the 3D PCM device 100 includes one or more PCM cells 108, each disposed at an intersection of a lower bitline 102 or an upper bitline 104 and a corresponding wordline 106. Each PCM cell 108 has a vertical square pillar shape. Each PCM cell 108 includes at least a vertically stacked PCM element 110 and a selector 112. Each PCM cell 108 stores a single bit of data and can be written or read by varying the voltage applied to the corresponding selector 112, which replaces the need for a transistor. Each PCM cell 108 is individually accessed by current applied through top and bottom conductors (e.g., respective word line 106 and lower bit line 102 or upper bit line 104) in contact with each PCM cell 108. The PCM cells 108 in the 3D PCM device 100 are arranged in a memory array.

Fig. 2 illustrates a side view of a cross-section of an example 3D PCM memory device 200 in accordance with some aspects of the present disclosure. In fig. 2, a 3D PCM memory device 200 includes a substrate 202, one or more parallel bitlines 211 formed on the substrate 202, and one or more parallel wordlines 221 formed over the bitlines 211. Substrate 202 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), Silicon On Insulator (SOI), or any other suitable material. The bit line 211 and the word line 221 may comprise a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the bit line 211 and the word line 221 comprises a metal, such as tungsten.

The 3D PCM memory device 200 may be divided by an isolation layer 218 to form one or more spaced apart pillar PCM cells 201. In some embodiments, each pillar PCM cell 201 is disposed at an intersection of a corresponding one of the bit lines 211 and a corresponding one of the word lines 221. Each pillar PCM cell 201 is individually accessible by a current applied through a corresponding word line 221 and a corresponding bit line 211 in contact with the pillar PCM cell 201. Each of the pillar PCM cells 201 has a vertical pillar shape (e.g., similar to the PCM cell 108 in fig. 1), and the isolation layer 218 may laterally extend in the x-direction and the y-direction to separate the pillar PCM cells 201.

Each of the pillar PCM cells 201 includes a first electrode 2071 formed on the bit line 211, a selector 205 formed on the first electrode 2071, and a second electrode 2072 formed on the selector 205. The pillar-shaped PCM cell 201 further includes a PCM element 203 formed on the second electrode 2072, and a third electrode 2073 formed on the PCM element 203. The first electrode 2071, the selector 205 and the second electrode 2072 are functionally modularized and function as a selection device in the pillar-shaped PCM cell 201. The second electrode 2072, the PCM element 203 and the third electrode 2073 are functionally modularized and function as a storage element in the pillar-shaped PCM cell 201. It is to be understood that the second electrode 2072 serves as a common electrode in the selection device and the memory element.

The first electrode 2071 is formed on the bit line 211 and is in contact with the selector 205, so that the first electrode 2071 serves as a current path and may be formed of a conductive material. In some embodiments, the first electrode 2071 may be a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the first electrode 2071 may be a titanium nitride (TiN) layer, but the disclosure is not limited thereto.

The selector 205 is formed on the first electrode 2071, and the resistance of the selector 205 changes in response to a selection voltage applied between the first electrode 2071 and the second electrode 2072. In some embodiments, the selector 205 may be an Ovonic Threshold Switch (OTS) device made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material having OTS properties. Regarding the function of the selector 205 including the OTS material, the selector 205 may be in a high resistance state that prevents a current from flowing when a voltage lower than a threshold voltage Vth is applied between the first electrode 2071 and the second electrode 2072, and the selector 205 may be in a low resistance state that allows a current to flow when a voltage higher than the threshold voltage Vth is applied between the first electrode 2071 and the second electrode 2072.

The second electrode 2072 is formed between the selector and the memory element and serves as one electrode of both the selector and the memory element, and thus the second electrode 2072 should be formed of a thermally and electrically insulating material to reduce temperature interference and electrical interference from the selector and the memory element. The second electrode 2072 may be formed of, or may include, for example, a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the second electrode 2072 may be a titanium nitride (TiN) layer or any suitable conductive layer. In some embodiments, the second electrode 2072 may be formed of amorphous carbon.

The PCM element 203 is formed on the second electrode 2072. The PCM element 203 is a material whose phase can be reversibly switched between an amorphous state and a crystalline state according to a heating time. Generally, the PCM element 203 may be present in the form of an amorphous phase and one crystalline phase, or the PCM element 203 may sometimes be present in the form of an amorphous phase and several crystalline phases, and may be switched between these phases rapidly and repeatedly. In some embodiments, the PCM element 203 may include a material whose phase may be reversibly changed using joule heat, which is generated when a voltage is applied between the second electrode 2072 and the third electrode 2073, and the resistance of the PCM element 203 may be changed by such phase change. In some embodiments, the PCM element 203 may include a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, the PCM element 203 may be a binary (two-element) compound, such as GaSb, InSb, InSe, SbTe, or GeTe; ternary (three-element) compounds, such as GeSbTe, GaSeTe, InSbTe, SnSbTe or InSbGe; or quaternary (four-element) compounds, such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), or TeGeSbS. In some embodiments, the PCM element 203 may be GeSbTe.

A third electrode 2073 is formed on the PCM element 203. In some embodiments, the material of the third electrode 2073 may be similar to the material of the first electrode 2071 or the second electrode 2072. In some embodiments, the material of the third electrode 2073 may be similar to the material of the second electrode 2072. Then, the word line 221 is formed on the third electrode 2073.

It should be understood that the locations of the bitlines 211 and the wordlines 221 corresponding to the pillar PCM cells 201 may be interchanged according to different memory designs. That is, the first electrode 2071 may be formed on the word line, and the bit line may be formed on the third electrode 2073.

Fig. 3 illustrates a perspective view of an example 3D PCM device 300 having stacked PCM cells according to some aspects of the present disclosure. The 3D PCM apparatus 300 includes a lower bitline 321, an intermediate bitline 323 above the lower bitline 321, and an upper bitline 325 above the intermediate bitline 323.3. The PCM device 300 also includes a lower wordline 341 positioned vertically between the lower bit line 321 and the intermediate bit line 323, and an upper wordline 343 positioned vertically between the intermediate bit line 323 and the upper bit line 325. As shown in fig. 3, in plan view, each of the

bit lines

321, 323, and 325 extends laterally along a bit line direction (e.g., in the x-direction); and each of the word lines 341 and 343 extends laterally along a word line direction (e.g., in the y-direction) in plan view. In a plan view, each of the word lines 341 and 343 intersects with each of the

bit lines

321, 323, and 325. In some implementations, each of the word lines 341 and 343 is perpendicular to each of the

bit lines

321, 323, and 325.

As shown in fig. 3, the 3D PCM device 300 further includes a first PCM cell 311 disposed at an intersection of a lower bit line 321 and a lower word line 341, a second PCM cell 331 disposed at an intersection of the lower word line 341 and an intermediate bit line 323, a third PCM cell 351 disposed at an intersection of the intermediate bit line 323 and an upper word line 343, and a fourth PCM cell 371 disposed at an intersection of the upper word line 343 and the upper word line 325. Each of the

PCM cells

311, 331, 351, and 371 has a vertical pillar shape. Each of the

PCM cells

311, 331, 351, and 371 includes at least a vertically stacked PCM element and a selector. Each of

PCM cells

311, 331, 351, and 371 stores a single bit of data and can be written or read by changing the voltage applied to the corresponding selector, which replaces the need for transistors. The first PCM cell 311 is individually accessed by currents applied through top and bottom conductors (e.g., the lower word line 341 and the lower bit line 321) in contact with the first PCM cell 311. The second PCM cell 331 is individually accessed by currents applied through, for example, the middle bit line 323 and the lower word line 341. The third PCM cell 351 is individually accessed by a current applied through, for example, the upper word line 343 and the middle bit line 323. The fourth PCM cell 371 is individually accessed by currents applied through, for example, the upper bit line 325 and the upper word line 343. Each of the

PCM cells

311, 331, 351, and 371 in the 3D PCM device 300 is arranged in a memory array. In some embodiments, first PCM cell 311 and fourth PCM cell 371 are external PCM cells, e.g., a first external PCM cell and a second external PCM cell. The second and

third PCM cells

331 and 351 are internal PCM cells, e.g., first and second internal PCM cells. In some embodiments, each of the first and second inner PCM cells may include a punctured PCM cell, which will be discussed later.

Fig. 4 illustrates a side view of a cross section of an example 3D PCM device 400 having a collapsed PCM cell according to some aspects of the present disclosure. The 3D PCM device 400 includes a lower bit line 421, an intermediate bit line 423 above the lower bit line 421, and an upper bit line 425 above the intermediate bit line 423. The 3D PCM device 400 further includes a lower word line 441 vertically positioned between the lower bit line 421 and the middle bit line 423, and an upper word line 443 vertically positioned between the middle bit line 423 and the upper bit line 425. As shown in fig. 4, each of the

bit lines

421, 423, and 425 extends laterally along a bit line direction (e.g., in the x-direction), and each of the word lines 441 and 443 extends laterally along a word line direction (e.g., in the y-direction). Each of the word lines 441 and 443 intersects each of the

bit lines

421, 423, and 425. In some embodiments, each of the word lines 441 and 443 is perpendicular to each of the

bit lines

421, 423, and 425. In some embodiments, the

bit lines

421, 423, and 425 and the word lines 441 and 443 may include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each of the

bit lines

421, 423, and 425 and the word lines 441 and 443 includes a metal, such as tungsten.

As shown in fig. 4, the 3D PCM device 400 further includes a first external PCM cell 411 disposed at the intersection of the lower bit line 421 and the lower word line 441, a first punctured PCM cell 431 disposed at the intersection of the lower word line 441 and the middle bit line 423, a second punctured PCM cell 451 disposed at the intersection of the middle bit line 423 and the upper word line 443, and a second external PCM cell 471 disposed at the intersection of the upper word line 443 and the upper word line 425. Each of the

PCM cells

411, 431, 451, and 471 has a vertical pillar shape. Each of the

PCM cells

411, 431, 451, and 471 includes at least a vertically stacked PCM element and a selector. Each of

PCM cells

411, 431, 451, and 471 stores a single bit of data and may be written to or read by varying the voltage applied to the corresponding selector, which replaces the need for a transistor. The first external PCM cell 411 is individually accessed by currents applied through top and bottom conductors (e.g., the lower word line 441 and the lower bit line 421) in contact with the first external PCM cell 411. The first punctured PCM cell 431 is accessed solely by the current applied through, for example, the middle bit line 423 and the lower word line 441. The second punctured PCM cell 451 is accessed solely by the current applied through, for example, the upper wordline 443 and the middle bitline 423. The second external PCM cell 471 is accessed solely by the current applied through, for example, the upper bitline 425 and the upper wordline 443. Each of the

PCM cells

411, 431, 451, and 471 in the 3D PCM device 400 is arranged in a memory array. In some embodiments, 3D PCM device 400 may include a plurality of inner punctured PCM cells (e.g., first punctured PCM cell 431 and second punctured PCM cell 451) between two outer PCM cells (e.g., first outer PCM cell 411 and second outer PCM cell 471). For example, 3D PCM device 400 may include four inner punctured PCM cells between two outer PCM cells. In some embodiments, the size of the external PCM cell may be a reference (baseline) for all PCM cells, and the size of the punctured PCM cell is smaller than the size of the external PCM cell. It should be noted that each punctured PCM cell may be smaller in size in both the PCM element and the selector (i.e., comprising two elements), or it may be smaller in size only in the PCM element. It should also be noted that a shrunk PCM cell may refer to a PCM cell having a reduced thickness, width, or both.

Specifically, the first external PCM cell 411 includes a first bottom electrode 4171 formed on the lower bit line 421, a first selector 415 formed on the first bottom electrode 4171, a first middle electrode 4172 formed on the first selector 415, a first PCM element 413 formed on the first middle electrode 4172, and a first top electrode 4173 formed on the first PCM element 413. In some embodiments, one first adhesive layer or a pair of first adhesive layers 419 may be formed on, under, or both the first PCM element 413 to increase electrical contact between the PCM element and the electrode or to reduce stress between the PCM element and the electrode. The first punctured PCM cell 431 includes a second bottom electrode 4371 formed on the lower word line 441, a second selector 435 formed on the second bottom electrode 4371, a second middle electrode 4372 formed on the second selector 435, a first punctured PCM element 433 formed on the second middle electrode 4372, and a second top electrode 4373 formed on the first punctured PCM element 433. In some embodiments, one second adhesive layer or a pair of second adhesive layers 439 may be formed on, under, or both the first shrunk PCM element 433 to increase electrical contact between the PCM element and the electrode or to reduce stress between the PCM element and the electrode. In some embodiments, the thickness of the first PCM element 413 is greater than the thickness of the first shrunk PCM element 433. In some embodiments, the thickness of the first PCM element 413 may be 5% to 20%, e.g., 10%, greater than the thickness of the first collapsed PCM element 433. In some embodiments, the width of the first PCM element 413 is greater than the width of the first punctured PCM element 433. In some embodiments, the width of the first PCM element 413 may be 5% to 20%, for example 10%, larger than the width of the first punctured PCM element 433. In some embodiments, the thickness of the second PCM element of the second PCM cell 471 may be the same as the thickness of the first PCM element 413. In some embodiments, the width of the second punctured PCM element of the second punctured PCM cell 451 may be the same as the width of the first punctured PCM element 433. Thus, the width of the first PCM element 413 is greater than the width of the first punctured PCM element 433 and the width of the second PCM element of the second PCM cell 471 is greater than the width of the second punctured PCM element of the second punctured PCM cell 451. In addition, the thickness of the first PCM element 413 is greater than the thickness of the first PCM element 433, and the thickness of the second PCM element of the second PCM cell 471 is greater than the thickness of the second PCM element of the second PCM cell 451.

In some embodiments,

electrodes

4171, 4172, 4173, 4371, 4372, and 4373 may comprise a metal, a conductive metal nitride, a conductive metal oxide, or a combination thereof. In some embodiments, the

electrodes

4171, 4172, 4173, 4371, 4372, and 4373 may comprise a titanium nitride (TiN) layer. In some embodiments, the first and second

intermediate electrodes

4172 and 4372 may be formed of amorphous carbon. The other electrodes in

PCM cells

411, 431, 451, and 471 may include the same or similar materials as

electrodes

4171, 4172, 4173, 4371, 4372, and 4373.

In some embodiments,

selectors

415 and 435 may be Ovonic Threshold Switch (OTS) devices made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material having OTS properties. Other selectors in the

PCM cells

411, 431, 451, and 471 may include the same or similar materials as the first selector 415 and the second selector 435.

In some embodiments, the first PCM element 413 and the first shrinkage PCM element 433 may include a chalcogenide composition including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, the first PCM element 413 and the first contracting PCM element 433 may be binary (bi-element) compounds, such as GaSb, InSb, InSe, SbTe, or GeTe; the first PCM element 413 and the first shrink PCM element 433 may be ternary (three-element) compounds, such as GeSbTe, GaSeTe, InSbTe, SnSbTe or InSbGe; or the first PCM element 413 and the first shrink PCM element 433 may be a quaternary (four-element) compound, such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), or TeGeSbS. In some embodiments, the first PCM element 413 and the first PCM element 433 may be GeSbTe. The other PCM elements in the

PCM cells

411, 431, 451 and 471 and the shrinking PCM element may comprise the same or similar materials as the first PCM element 413 and the first shrinking PCM element 433. In some embodiments, the crystallization temperature of the PCM element of the inner cell (e.g., the first shrunk PCM element 433 of the first shrunk PCM cell 431) may be higher than the crystallization temperature of the first PCM element 433. In some embodiments, the crystallization temperature of the PCM element of the inner cell (e.g., the first shrink PCM element 433 of the first shrink PCM cell 431) may be maintained between 800K-900K during the programming operation. In some embodiments, the PCM element of the inner cell (e.g., the first PCM element 433 of the first shrunk PCM cell 431) may be further doped with carbon (C), while the PCM element of the outer cell (e.g., the first PCM element 413 of the first outer PCM cell 411) may be not doped with carbon or doped with less carbon than the first shrunk PCM element 433, such that the crystallization temperature of the first shrunk PCM element 433 may be higher than the crystallization temperature of the first PCM element 433.

It should be understood that the locations of the

bit lines

421, 423, and 425 and the word lines 441 and 443 corresponding to the

PCM cells

411, 431, 451, and 471 can be swapped according to different memory designs. In other words, the first bottom electrode 4171 may be formed on the word line, and the bit line may be formed on the first top electrode 4173.

In addition, the first isolation layer 418 may be formed on sidewalls of the first external PCM cell 411, and the second isolation layer 438 may be formed on sidewalls of the first shrunk PCM cell 431. Since the width of the first shrunk PCM cell 431 may be reduced, the width of the second isolation layer 438 may be greater than the width of the first isolation layer 418. In some embodiments, the lateral distance between punctured PCM cells (e.g., first punctured PCM cell 431 and its laterally adjacent punctured PCM cell) is greater than the lateral distance between external PCM cells (e.g., first external PCM cell 411 and its laterally adjacent PCM cell). In some embodiments, the material of isolation layers 418 and 438 may include silicon nitride (Si)₃N₄) Silicon dioxide (SiO)₂) Aluminum nitride (AlN) or aluminum oxide (Al)₂O₃) At least one of (1).

Fig. 5 illustrates a comparison result of resistance variation over operation time between a 3D PCM device having the same cell size and a 3D PCM device having a modified cell size according to some aspects of the present disclosure. According to fig. 5, the resistance of a 3D PCM device comprising a stack of four PCM cells having the same cell size may decrease over operation time due to thermal cross-talk and data retention problems. Crystallization in the amorphous phase that accumulates during continuous operation results in a decrease in resistance over time. On the other hand, with modified cell sizes as provided in the present disclosure, the drop in resistance over operating time has been significantly reduced. In particular, since the reduced thickness of the inner cell reduces the reset programming pulse amplitude requirement for reaching amorphous temperature, there is less thermal cross-talk transferred to neighboring cells and thus increased retention margin (retention margin). At the same time, the crystallization temperature of the inner cell increases with decreasing thickness, and thus increases the intrinsic retention time.

Fig. 6A-6D illustrate an exemplary fabrication process for forming an exemplary 3D PCM device having a shrunk PCM cell according to some aspects of the present disclosure. Also, fig. 7 illustrates a flow diagram of an example method for forming an example 3D PCM device having a punctured PCM cell according to some aspects of the present disclosure. Examples of the 3D PCM device shown in fig. 6A-6D and 7 include the 3D PCM device 400 shown in fig. 4. Fig. 6A to 6D and fig. 7 will be described together. It should be understood that the operations illustrated by method 700 are not exhaustive, and that other operations may be performed before, after, or between any of the illustrated operations. Further, some operations may be performed concurrently, or in a different order than shown in FIG. 7.

Referring to fig. 7, a method 700 begins with operation 702, where one or more first PCM cells are deposited on one or more first bit lines, and each of the one or more first PCM cells includes a first PCM element. For example, as in FIG. 6A, one or more first PCM cell (e.g., first PCM cell 611) products are deposited on one or more first bit lines (e.g., first bit line 621). In some embodiments, one or more first bit lines (e.g., first bit line 621, which may correspond to lower bit line 421 in fig. 4) and one or more first PCM cells (e.g., first PCM cell 611, which may correspond to first external PCM cell 411 in fig. 4) may be formed on a substrate (e.g., corresponding to substrate 202 in fig. 2). To form the first PCM cell 611 with the first PCM element 613 on the first bitline 621, a first bottom electrode (e.g., corresponding to the first bottom electrode 4171 in fig. 4) is deposited on the first bitline 621, a first selector (e.g., corresponding to the first selector 415 in fig. 4) is deposited on the first bottom electrode, a first intermediate electrode (e.g., corresponding to the first intermediate electrode 4172 in fig. 4) is deposited on the first selector, the first PCM element 613 (e.g., corresponding to the first PCM element 413 in fig. 4) is deposited on the first intermediate electrode, and a first top electrode (e.g., corresponding to the first top electrode 4173 in fig. 4) is deposited on the first PCM element 613. In some embodiments, depositing may include using one or more thin film deposition processes, including but not limited to Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, first PCM cell 611 is formed by: a first PCM stack (not shown) is deposited and etched in a vertical direction (e.g., z-direction) to form one or more first PCM cells (e.g., first PCM cells 611). The etching process includes wet etching, dry etching, or a combination thereof.

Referring to fig. 7, the method 700 proceeds to operation 704, where one or more first wordlines and one or more first punctured PCM cells, each including a first punctured PCM element, are sequentially deposited over corresponding one or more first PCM cells. For example, as shown in FIG. 6B, one or more first wordlines (e.g., first wordline 641) and one or more first punctured PCM cells (e.g., first punctured PCM cell 631) are sequentially deposited over corresponding one or more first PCM cells (including first PCM cell 611). Each of the one or more first punctured PCM cells (e.g., first punctured PCM cells 631) includes a first punctured PCM element 633. To form the first punctured PCM cell 631 having the first punctured PCM element 633 on the first wordline 641, a second bottom electrode (e.g., corresponding to the second bottom electrode 4371 in fig. 4) is deposited on the first wordline 641, a second selector (e.g., corresponding to the second selector 435 in fig. 4) is deposited on the second bottom electrode, a second intermediate electrode (e.g., corresponding to the second intermediate electrode 4372 in fig. 4) is deposited on the second selector, a first punctured PCM element 633 (e.g., corresponding to the first punctured PCM element 433 in fig. 4) is deposited on the second intermediate electrode, and a second top electrode (e.g., corresponding to the second top electrode 4373 in fig. 4) is deposited on the first punctured PCM element 633. In some embodiments, depositing may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the first punctured PCM cell 631 is formed by: a second PCM stack (not shown) is deposited and etched in a vertical direction (e.g., the z-direction) to form one or more first shrunk PCM cells (e.g., first shrunk PCM cells 631). The etching process includes wet etching, dry etching, or a combination thereof.

In some embodiments, the width of each second trench 663 etched through the second PCM stack is greater than the width of each first trench 661 etched through the first PCM stack. Thus, the first punctured PCM cell 631 has a smaller width than the first PCM cell 611.

Referring to FIG. 7, the method 700 proceeds to operation 706, where one or more second bitlines and one or more second punctured PCM cells are deposited sequentially over corresponding one or more first punctured PCM cells. For example, as shown in fig. 6C, one or more second bitlines (e.g., second bitline 623) and one or more second punctured PCM cells (e.g., second punctured PCM cell 651) are sequentially deposited on the corresponding one or more first punctured PCM cells (e.g., first punctured PCM cell 631). Forming the second punctured PCM cell 651 with the second punctured PCM element 653 is similar to forming the first punctured PCM cell 631 with the first punctured PCM element 633. In some embodiments, depositing may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the second punctured PCM cell 651 is formed by: a third PCM stack (not shown) is deposited and etched in a vertical direction (e.g., the z-direction) to form one or more second shrunk PCM cells (e.g., second shrunk PCM cells 651). The etching process includes wet etching, dry etching, or a combination thereof.

In some embodiments, the width of each third trench 665 etched through the third PCM stack is greater than the width of each first trench 661 etched through the first PCM stack. Thus, the second punctured PCM cell 651 has a smaller width than the first PCM cell 611. In some embodiments, the width of each third trench 665 etched through the third PCM stack is the same as the width of each second trench 663 etched through the second PCM stack. Therefore, the second punctured PCM cell 651 has the same width as the first punctured PCM cell 631.

Referring to FIG. 7, method 700 proceeds to operation 708, where one or more second wordlines and one or more second PCM cells are sequentially formed over corresponding one or more second punctured PCM cells. For example, as shown in fig. 6D, one or more second wordlines (e.g., second wordline 643) and one or more second PCM cells (e.g., second PCM cell 671) are sequentially deposited on corresponding one or more second shrunk PCM cells (e.g., second shrunk PCM cell 651). Forming the second PCM cell 671 with second PCM element 673 is similar to forming the first PCM cell 611 with the first PCM element 613. In some embodiments, depositing may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof. In some embodiments, the second PCM cell 671 is formed by: a fourth PCM stack (not shown) is deposited and etched in a vertical direction (e.g., the z-direction) to form one or more second PCM cells (e.g., second PCM cell 671). The etching process includes wet etching, dry etching, or a combination thereof.

In some embodiments, the width of each fourth trench 667 etched through the fourth PCM stack is less than the width of each third trench 665 etched through the third PCM stack. Therefore, the second PCM cell 671 has a width greater than that of the second punctured PCM cell 651. In some embodiments, the width of each fourth trench 667 etched through the fourth PCM stack is the same as the width of each first trench 661 etched through the first PCM stack. Thus, the second PCM cell 671 has the same width as the first PCM cell 611.

Referring to fig. 7, the method 700 proceeds to operation 710 where one or more third bit lines are formed over one or more second PCM cells. For example, as shown in fig. 6D, one or more third bit lines (e.g., third bit line 625) are deposited over respective one or more second PCM cells (e.g., second PCM cell 671). In some embodiments, depositing may include using one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, electroplating, electroless plating, any other suitable deposition process, or any combination thereof.

According to one aspect of the present disclosure, a three-dimensional (3D) Phase Change Memory (PCM) device includes a first PCM cell, a first punctured PCM cell on the first PCM cell, a second punctured PCM cell on the first punctured PCM cell, and a second PCM cell on the second punctured PCM cell. The first PCM cell includes a first PCM element, the first punctured PCM cell includes a first punctured PCM element, the second punctured PCM cell includes a second punctured PCM element, and the second PCM cell includes a second PCM element. The width of the first PCM element is greater than the width of the first punctured PCM element and the width of the second PCM element is greater than the width of the second punctured PCM element.

In some embodiments, the width of the first PCM element is 5% to 20% greater than the width of the first punctured PCM element, and the width of the second PCM element is 5% to 20% greater than the width of the second punctured PCM element.

In some embodiments, the thickness of the first PCM element is greater than the thickness of the first shrunk PCM element, and the thickness of the second PCM element is greater than the thickness of the second shrunk PCM element.

In some embodiments, the thickness of the first PCM element is 5% to 20% greater than the thickness of the first shrunk PCM element, and the thickness of the second PCM element is 5% to 20% greater than the thickness of the second shrunk PCM element.

In some embodiments, the width of the first PCM cell is greater than the width of the first punctured PCM cell, and the width of the second PCM cell is greater than the width of the second punctured PCM cell.

In some embodiments, the width of the first punctured PCM cell is the same as the width of the second punctured PCM cell, and the width of the second PCM cell is the same as the width of the first PCM cell.

In some embodiments, the crystallization temperature of the first shrunk PCM element is higher than the crystallization temperature of the first PCM element.

In some embodiments, the material of the first PCM element and the first shrinkage PCM element comprises a chalcogenide component comprising at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

In some embodiments, the first shrunk PCM element is doped with carbon (C) and the first PCM element is not doped with carbon, or is doped with less carbon than the first shrunk PCM element.

In some embodiments, the 3D PCM device further includes a lower bitline, a lower wordline, a middle bitline, an upper wordline, an upper bitline. The first PCM cell is formed between a lower bitline and a lower wordline, the first punctured PCM cell is formed between the lower wordline and an intermediate bitline, the second punctured PCM cell is formed between the intermediate bitline and an upper wordline, and the second PCM cell is formed between the upper wordline and the upper bitline.

In some embodiments, in a plan view, the lower bit line intersects the lower word line, the lower word line intersects the middle bit line, the middle bit line intersects the upper word line, and the upper word line intersects the upper bit line.

In some embodiments, the first PCM cell includes a first bottom electrode formed on a lower bit line, a first selector formed on the first bottom electrode, a first intermediate electrode formed on the first selector, a first PCM element formed on the first intermediate electrode, and a first top electrode formed on the first PCM element. The first shrunk PCM cell includes a second bottom electrode formed on the lower word line, a second selector formed on the second bottom electrode, a second intermediate electrode formed on the second selector, a first shrunk PCM element formed on the second intermediate electrode, and a second top electrode formed on the first shrunk PCM element.

In some embodiments, the 3D PCM device further includes a pair of first adhesive layers formed above and below the first PCM element, and a pair of second adhesive layers formed above and below the first shrink PCM element.

In some embodiments, the 3D PCM device further includes a first isolation layer formed on sidewalls of the first PCM cell, and a second isolation layer formed on sidewalls of the first shrunk PCM cell.

According to another aspect of the present disclosure, a three-dimensional (3D) Phase Change Memory (PCM) device includes: one or more first PCM cells, each first PCM cell comprising a first PCM element; one or more first punctured PCM cells on a respective one or more first PCM cells, each first punctured PCM cell comprising a first punctured PCM element; one or more second punctured PCM cells on the respective one or more first punctured PCM cells, each second punctured PCM cell including a second punctured PCM element; and one or more second PCM cells on the respective one or more second punctured PCM cells, each second PCM cell including a second PCM element. The width of the first PCM element is greater than the width of the first punctured PCM element and the width of the second PCM element is greater than the width of the second punctured PCM element.

In some embodiments, the 3D PCM device further includes one or more lower bitlines, one or more lower wordlines, one or more intermediate bitlines, one or more upper wordlines, and one or more upper bitlines. The first PCM cells are formed between respective ones of the one or more lower bitlines and respective ones of the one or more lower wordlines, the first punctured PCM cells are formed between respective ones of the one or more lower wordlines and respective ones of the one or more intermediate bitlines, the second punctured PCM cells are formed between respective ones of the one or more intermediate bitlines and respective ones of the one or more upper wordlines, and the second PCM cells are formed between respective ones of the one or more upper wordlines and respective ones of the one or more upper bitlines.

In some embodiments, in plan view, one or more lower bit lines intersect with a respective one or more lower word lines, one or more lower word lines intersect with a respective one or more intermediate bit lines, one or more intermediate bit lines intersect with a respective one or more upper word lines, and one or more upper word lines intersect with a respective one or more upper bit lines.

In some embodiments, the 3D PCM device further comprises one or more first isolation layers separating the one or more first PCM cells, and one or more second isolation layers separating the one or more first punctured PCM cells.

According to yet another aspect of the present disclosure, a method for forming a three-dimensional (3D) Phase Change Memory (PCM) device includes: depositing one or more first PCM cells on respective one or more first bit lines, each first PCM cell comprising a first PCM element; sequentially depositing one or more first wordlines and one or more first punctured PCM cells, each first punctured PCM cell comprising a first punctured PCM element, on a respective one or more first PCM cells; sequentially depositing one or more second bitlines and one or more second punctured PCM cells on the corresponding one or more first punctured PCM cells, each second punctured PCM cell comprising a second punctured PCM element; sequentially depositing one or more second wordlines and one or more second PCM cells, each comprising a second PCM element, on the respective one or more second shrunk PCM cells; and depositing one or more third bitlines over the respective one or more second PCM cells.

In some embodiments, the method further comprises depositing one or more first bitlines on the substrate before depositing the one or more first PCM cells on the one or more first bitlines.

In some embodiments, depositing one or more first PCM cells comprises: depositing a first PCM stack; and etching the first PCM stack in a vertical direction to form one or more first PCM cells. Depositing one or more first shrunk PCM cells comprises: depositing a second PCM stack; and etching the second PCM stack in a vertical direction to form one or more first shrunk PCM cells. Depositing one or more second shrunk PCM cells comprises: depositing a third PCM stack; and etching the third PCM stack in a vertical direction to form one or more second shrunk PCM cells. Depositing one or more second shrunk PCM cells comprises: depositing a fourth PCM stack; and etching the fourth PCM stack in a vertical direction to form one or more second PCM cells.

In some embodiments, a width of each second trench etched through the second PCM stack is greater than a width of each first trench etched through the first PCM stack, and a width of each third trench etched through the third PCM stack is greater than a width of each fourth trench etched through the fourth PCM stack.

In some embodiments, the width of each third trench etched through the third PCM stack is the same as the width of each second trench etched through the second PCM stack, and the width of each first trench etched through the first PCM stack is the same as the width of each fourth trench etched through the fourth PCM stack.

The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such changes and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Embodiments of the present disclosure have been described above with the aid of functional blocks (functional building blocks) illustrating embodiments of specific functions and relationships thereof. Boundaries of these functional blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.

The summary and abstract sections may set forth one or more, but not all exemplary embodiments of the present disclosure as contemplated by one or more inventors, and are therefore not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A three-dimensional (3D) Phase Change Memory (PCM) device comprising:

a first PCM cell;

a first punctured PCM cell over the first PCM cell;

a second punctured PCM cell over the first punctured PCM cell; and

a second PCM cell on the second punctured PCM cell, wherein the first PCM cell includes a first PCM element, the first punctured PCM cell includes a first punctured PCM element, the second punctured PCM cell includes a second punctured PCM element, and the second PCM cell includes a second PCM element, and wherein a width of the first PCM element is greater than a width of the first punctured PCM element and a width of the second PCM element is greater than a width of the second punctured PCM element.

2. The 3D PCM device of claim 1, wherein a width of the first PCM element is 5% to 20% greater than a width of the first punctured PCM element, and a width of the second PCM element is 5% to 20% greater than a width of the second punctured PCM element.

3. The 3D PCM device of claim 1 or 2, wherein a thickness of the first PCM element is greater than a thickness of the first collapsed PCM element, and a thickness of the second PCM element is greater than a thickness of the second collapsed PCM element.

4. The 3D PCM device of claim 3, wherein a thickness of the first PCM element is 5% to 20% greater than a thickness of the first shrunk PCM element, and a thickness of the second PCM element is 5% to 20% greater than a thickness of the second shrunk PCM element.

5. The 3D PCM device of any of claims 1-4, wherein a width of the first PCM cell is greater than a width of the first punctured PCM cell, and a width of the second PCM cell is greater than a width of the second punctured PCM cell.

6. The 3D PCM device of any of claims 1-5, wherein a width of the first punctured PCM cell is the same as a width of the second punctured PCM cell, and a width of the second PCM cell is the same as a width of the first PCM cell.

7. The 3D PCM device of any of claims 1-6, wherein a crystallization temperature of the first contracting PCM element is higher than a crystallization temperature of the first PCM element.

8. The 3D PCM device of any of claims 1-7, wherein the material of the first PCM element and the first contracting PCM element comprises a chalcogenide component comprising at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

9. The 3D PCM device of any of claims 1-8, wherein the first shrunk PCM element is doped with carbon (C) and the first PCM element is not doped with carbon or is doped with less carbon than the first shrunk PCM element is doped with carbon.

10. The 3D PCM device of any of claims 1-9, further comprising:

a lower bit line;

a lower word line;

a middle bit line;

an upper word line; and

an upper bit line, wherein the first PCM cell is formed between the lower bit line and the lower word line, the first punctured PCM cell is formed between the lower word line and the middle bit line, the second punctured PCM cell is formed between the middle bit line and the upper word line, and the second PCM cell is formed between the upper word line and the upper bit line.

11. The 3D PCM device of claim 10, wherein, in plan view, the lower bitline intersects the lower wordline, the lower wordline intersects the middle bitline, the middle bitline intersects the upper wordline, and the upper wordline intersects the upper bitline.

12. The 3D PCM device of claim 11, wherein the first PCM cell comprises:

a first bottom electrode formed on the lower bit line,

a first selector formed on the first bottom electrode,

a first intermediate electrode formed on the first selector,

the first PCM element formed on the first intermediate electrode, and

a first top electrode formed on the first PCM element, and wherein the first shrunk PCM cell comprises:

a second bottom electrode formed on the lower word line,

a second selector formed on the second bottom electrode,

a second intermediate electrode formed on the second selector,

the first shrunk PCM element formed on the second intermediate electrode, an

A second top electrode formed on the first shrunk PCM element.

13. The 3D PCM device of any of claims 1-12, further comprising:

a pair of first adhesive layers formed above and below the first PCM element; and

a pair of second adhesive layers formed above and below the first shrink PCM element.

14. The 3D PCM device of any of claims 1-13, further comprising:

a first isolation layer formed on sidewalls of the first PCM cell; and

a second isolation layer formed on sidewalls of the first shrunk PCM cell.

15. A three-dimensional (3D) Phase Change Memory (PCM) device comprising:

one or more first PCM cells, each first PCM cell comprising a first PCM element;

one or more first punctured PCM cells on a respective one or more of the first PCM cells, each first punctured PCM cell comprising a first punctured PCM element;

one or more second punctured PCM cells on respective ones of the one or more first punctured PCM cells, each second punctured PCM cell including a second punctured PCM element; and

one or more second PCM cells on respective said one or more second punctured PCM cells, each second PCM cell comprising a second PCM element, wherein a width of the first PCM element is greater than a width of the first punctured PCM element, and a width of the second PCM element is greater than a width of the second punctured PCM element.

16. The 3D PCM device of claim 15, wherein a width of the first PCM element is 5% to 20% greater than a width of the first punctured PCM element, and a width of the second PCM element is 5% to 20% greater than a width of the second punctured PCM element.

17. The 3D PCM device of claim 15 or 16, wherein a thickness of the first PCM element is greater than a thickness of the first collapsed PCM element, and a thickness of the second PCM element is greater than a thickness of the second collapsed PCM element.

18. The 3D PCM device of claim 17, wherein the thickness of the first PCM element is 5% to 20% greater than the thickness of the first PCM element, and the thickness of the second PCM element is 5% to 20% greater than the thickness of the second PCM element.

19. The 3D PCM device of any of claims 15-18, wherein a width of the first PCM cell is greater than a width of the first punctured PCM cell and a width of the second PCM cell is greater than a width of the second punctured PCM cell.

20. The 3D PCM device of any of claims 15-19, wherein a width of the first punctured PCM cell is the same as a width of the second punctured PCM cell, and the width of the second PCM cell is the same as the width of the first PCM cell.

21. The 3D PCM device of any of claims 15-20, wherein a crystallization temperature of the first contracting PCM element is higher than a crystallization temperature of the first PCM element.

22. The 3D PCM device of any of claims 15-21, wherein the material of the first PCM element and the first contracting PCM element comprises a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga).

23. The 3D PCM device of any of claims 15-22, wherein the first PCM element is doped with carbon (C) and the first PCM element is not doped with carbon or is doped with less carbon than the first PCM element.

24. The 3D PCM device of any of claims 15-23, further comprising:

one or more lower bit lines;

one or more lower word lines;

one or more intermediate bit lines;

one or more upper word lines; and

one or more upper bitlines, wherein the first PCM cells are formed between respective ones of the one or more lower bitlines and respective ones of the one or more lower wordlines, the first punctured PCM cells are formed between the respective ones of the one or more lower wordlines and respective ones of the one or more intermediate bitlines, the second punctured PCM cells are formed between the respective ones of the one or more intermediate bitlines and respective ones of the one or more upper wordlines, and the second PCM cells are formed between the respective ones of the one or more upper wordlines and respective ones of the one or more upper bitlines.

25. The 3D PCM device of claim 24, wherein, in plan view, the one or more lower bitlines intersect the respective one or more lower wordlines, the one or more lower wordlines intersect the respective one or more intermediate bitlines, the one or more intermediate bitlines intersect the respective one or more upper wordlines, and the one or more upper wordlines intersect the respective one or more upper bitlines.

26. The 3D PCM device of any of claims 15-25, further comprising:

one or more first isolation layers separating the one or more first PCM cells; and

one or more second isolation layers separating the one or more first shrunk PCM cells.

27. A method for forming a three-dimensional (3D) Phase Change Memory (PCM) device, comprising:

depositing one or more first PCM cells on the one or more first bit lines, each first PCM cell comprising a first PCM element;

sequentially depositing one or more first wordlines and one or more first punctured PCM cells, each first punctured PCM cell comprising a first punctured PCM element, over a respective one or more first PCM cells;

sequentially depositing one or more second bitlines and one or more second punctured PCM cells on the corresponding one or more first punctured PCM cells, each second punctured PCM cell comprising a second punctured PCM element;

sequentially depositing one or more second wordlines and one or more second PCM cells, each comprising a second PCM element, on the respective one or more second shrunk PCM cells; and

depositing one or more third bitlines on the respective one or more second PCM cells.

28. The method of claim 27, further comprising:

depositing the one or more first bit lines on the substrate before depositing the one or more first PCM cells on the respective one or more first bit lines.

29. The method of claim 27 or 28, wherein depositing the one or more first PCM cells comprises: depositing a first PCM stack and etching the first PCM stack in a vertical direction to form the one or more first PCM cells,

wherein depositing the one or more first shrunk PCM cells comprises: depositing a second PCM stack and etching the second PCM stack in the vertical direction to form the one or more first shrunk PCM cells,

wherein depositing the one or more second shrunk PCM cells comprises: depositing a third PCM stack and etching the third PCM stack in the vertical direction to form the one or more second shrunk PCM cells, and

wherein depositing the one or more second shrunk PCM cells comprises: depositing a fourth PCM stack and etching the fourth PCM stack in the vertical direction to form the one or more second PCM cells.

30. The method of claim 29, wherein a width of each second trench etched through the second PCM stack is greater than a width of each first trench etched through the first PCM stack, and a width of each third trench etched through the third PCM stack is greater than a width of each fourth trench etched through the fourth PCM stack.

31. The method of claim 30, wherein a width of each third trench etched through the third PCM stack is the same as a width of each second trench etched through the second PCM stack, and wherein a width of each first trench etched through the first PCM stack is the same as a width of each fourth trench etched through the fourth PCM stack.