CN114375475A - Memory device and layout thereof - Google Patents

Memory device and layout thereof Download PDF

Info

Publication number
CN114375475A
CN114375475A CN202180004837.1A CN202180004837A CN114375475A CN 114375475 A CN114375475 A CN 114375475A CN 202180004837 A CN202180004837 A CN 202180004837A CN 114375475 A CN114375475 A CN 114375475A
Authority
CN
China
Prior art keywords
bit line
region
memory device
line selector
peripheral block
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202180004837.1A
Other languages
Chinese (zh)
Inventor
王晓娟
雷威锋
李建平
彭首春
刘威
刘峻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Original Assignee
Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yangtze River Advanced Storage Industry Innovation Center Co Ltd filed Critical Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Publication of CN114375475A publication Critical patent/CN114375475A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0026—Bit-line or column circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0023—Address circuits or decoders
    • G11C13/0028—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/10—Phase change RAM [PCRAM, PRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/20—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes
    • H10B63/24—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having two electrodes, e.g. diodes of the Ovonic threshold switching type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
    • H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
    • H10B63/84—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
    • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device

Landscapes

  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Semiconductor Memories (AREA)

Abstract

In certain aspects, a memory device includes a peripheral block and a memory block on the peripheral block. The peripheral block includes a first wordline driver region in a second quadrant of the peripheral block, a second wordline driver region in a fourth quadrant of the peripheral block, a first bitline selector region in a third quadrant of the peripheral block, and a second bitline selector region in a first quadrant of the peripheral block.

Description

Memory device and layout thereof
Background
The present disclosure relates to memory devices and layouts thereof.
Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become challenging and costly. As a result, the storage density of the planar memory cell approaches the upper limit.
Three-dimensional (3D) memory architectures can address density limitations in planar memory cells. The 3D memory architecture includes a memory array and peripheral devices for controlling signals to and from the memory array. For example, phase-change memory (PCM) may utilize a difference between resistivities of an amorphous phase and a crystalline phase in a phase-change material based on electrothermal heating and quenching of the phase-change material. PCM array cells may be vertically stacked in 3D to form a 3D PCM device.
The layout configuration of the peripheral devices in the memory device corresponds to the pattern and configuration of a plurality of peripheral cells or components therein.
Disclosure of Invention
In one aspect, a memory device includes a peripheral block and a memory block on the peripheral block. The peripheral block includes a first wordline driver region in a second quadrant of the peripheral block, a second wordline driver region in a fourth quadrant of the peripheral block, a first bitline selector region in a third quadrant of the peripheral block, and a second bitline selector region in a first quadrant of the peripheral block.
In another aspect, a memory device includes a plurality of peripheral blocks and a plurality of memory blocks. Each memory block is on a corresponding peripheral block. Each peripheral block includes a first wordline driver region in a second quadrant of the respective peripheral block, a second wordline driver region in a fourth quadrant of the respective peripheral block, a first bitline selector region in a third quadrant of the respective peripheral block, and a second bitline selector region in a first quadrant of the respective peripheral block.
Drawings
The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate aspects of the present disclosure and, together with the description, further serve to explain the principles of the disclosure and to enable a person skilled in the pertinent art to make and use the disclosure.
Fig. 1 illustrates a perspective view of an example 3D Phase Change Memory (PCM) device, according to some aspects of the present disclosure.
Fig. 2A and 2B illustrate side views of cross sections of an example 3D PCM device according to some aspects of the present disclosure.
Fig. 3 illustrates a perspective view of an example 3D PCM device having interconnect layers according to some aspects of the present disclosure.
Fig. 4A and 4B illustrate side views of cross sections of an example memory device including a 3D PCM device, an interconnect layer, and a peripheral device, according to some aspects of the present disclosure.
Fig. 5A and 5B illustrate side views of cross sections of an example memory device including a 3D PCM device, an interconnect layer, and a peripheral device, according to some aspects of the present disclosure.
Fig. 6A and 6B illustrate layouts of example peripheral blocks of a memory device according to some aspects of the present disclosure.
FIG. 7 illustrates a layout of an example peripheral block of a memory device according to some aspects of the present disclosure.
Fig. 8A and 8B illustrate a layout of an example peripheral block of a memory device according to some aspects of the present disclosure.
FIG. 9 illustrates a layout of an example peripheral block of a memory device according to some aspects of the present disclosure.
FIG. 10 illustrates a layout of an example peripheral block of a memory device according to some aspects of the present disclosure.
The present disclosure will be described with reference to the accompanying drawings.
Detailed Description
While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the relevant art will recognize that other configurations and arrangements can be used without parting from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.
It should be noted that references in the specification to "one embodiment," "an example embodiment," "some implementations," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other implementations whether or not explicitly described.
Generally, terms may be understood at least in part from their usage in context. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" may also be understood to convey singular or plural usage, depending, at least in part, on the context. In addition, the term "based on" may be understood as not necessarily intended to convey an exclusive set of factors, but may allow for the presence of additional factors not necessarily expressly described, again depending at least in part on the context.
It should be readily understood that the meaning of "on … …", "above … …" and "above … …" in this disclosure should be interpreted in the broadest way such that "on … …" means not only "directly on something", but also includes the meaning of "on something" with intervening features or layers therebetween, and "above … …" or "above … …" means not only "above something" or "above something", but may also include the meaning of "it is above something" or "it is above something" without intervening features or layers therebetween (i.e., directly on something).
Further, spatially relative terms, such as "below … …," "below … …," "below," "above … …," "on," and the like, may be used herein to describe one element or feature's relationship to another element(s) or feature as illustrated for ease of description. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.
As used herein, the term "substrate" refers to a material on which a subsequent layer of material is added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.
As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have an extent less than the extent of the underlying or overlying structure. Furthermore, the layer may be a region of a homogenous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of the continuous structure or between any pair of horizontal planes at the top and bottom surfaces of the continuous structure. The layers may extend horizontally, vertically and/or along a tapered surface. The substrate may be a layer, which may include one or more layers therein, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.
As used herein, the term "3D" memory device or PCM device refers to a semiconductor device having memory cells that may be vertically arranged on a laterally oriented substrate such that the number of memory cells may be scaled up in the vertical direction relative to the substrate. As used herein, the term "perpendicular" refers to nominally perpendicular to a lateral surface of a substrate.
PCMs may utilize the difference between the resistivities of amorphous and crystalline phases in a phase change material (e.g., a chalcogenide alloy) based on electrothermal heating and quenching of the phase change material. The phase change material in a PCM cell may be located between two electrodes and a current may be applied to repeatedly switch the material (or at least a portion thereof that blocks the current path) between the two phases to store data. The PCM cells may be vertically stacked in 3D to form a 3D PCM device. 3D PCM devices store data based on a change in resistance of a bulk material property (e.g., in a high resistance state or a low resistance state) and incorporate a stackable cross-point data access array so as to be bit addressable.
As memory devices have evolved, more memory cells have been arranged in memory blocks of a memory array to increase the density of the memory devices. A 3D memory device may have stacked memory cells (e.g., PCM cells) and thus have twice or more memory cells than a planar memory device, resulting in a problem of arranging peripheral devices that control the operation of the memory array. For example, peripheral cells (e.g., bit line drivers, word line drivers, bit line selectors, word line selectors, local data lines, etc.) in a peripheral block may be arranged corresponding to the configuration of the respective memory blocks. Since there is limited space in each peripheral block, the layout configuration of the peripheral blocks corresponding to the memory blocks affects the array efficiency of the memory device.
First, some peripheral cells (e.g., word line drivers, local data lines, etc.) may not be traversed by a bit line or word line from above, requiring additional bypass routing paths or space for the interconnects. These additional bypass routing paths increase the area size of the peripheral blocks and reduce the overall array efficiency of the memory device.
Second, the memory device may include a plurality of peripheral blocks and a plurality of memory blocks in a compact arrangement. However, additional space for power supply lines should be left between the peripheral blocks to provide power supply to the peripheral cells in each peripheral block, thereby reducing array efficiency of the memory device.
Third, conventional interconnect layers below the memory array may not be able to carry high power currents from the top metal layer above the memory array, requiring a large width of these interconnect layers. These further reduce the array efficiency of the memory device.
Finally, some of the remaining regions in the separated portion of the peripheral block may need to have the same well potential and require additional wiring paths for connection. The more remaining areas are laid out in the disjunct portions, the more routing paths are required, which increases the cost and complexity of the routing.
To address one or more of the above issues, the present disclosure introduces a layout in which a plurality of remaining regions in the separation portion are combined, which leaves more area for the peripheral cells (e.g., more space for the active region of the transistor of the word driver or bit line selector). Furthermore, contact areas in adjacent peripheral blocks may be shared, reducing gaps between peripheral blocks, and requiring no additional width for interconnect layers. In particular, the mirroring of the layout not only merges the remaining areas in the adjacent peripheral blocks, but also allows sharing of the contact areas in the adjacent peripheral blocks. Thus, the area density and array efficiency are significantly increased.
Fig. 1 illustrates a perspective view of an exemplary 3D PCM device 100 according to some embodiments of the present disclosure. According to some embodiments, the 3D PCM device 100 has a transistor-less cross-point architecture that positions memory cells at the intersections of vertical conductors. The 3DPCM device 100 includes one or more parallel bottom bit lines 133 in the same plane and one or more parallel top bit lines 131 in the same plane above the bottom bit lines 133. The 3D PCM device 100 also includes one or more parallel wordlines (e.g., top wordline 141, bottom wordline 143, or a combination thereof) in the same plane vertically between the bottom bitline 133 and the top bitline 131. As shown in fig. 1, each bottom bitline 133 and each top bitline 131 extend laterally along a bitline direction (e.g., x-direction) in plan view (parallel to the wafer plane), and each wordline 141/143 extends laterally along a wordline direction (e.g., y-direction) in plan view. In plan view, each word line 141/143 intersects each bottom bit line 133 and each top bit line 131. In some embodiments, each word line 141/143 is perpendicular to each bottom bit line 133 and each top bit line 131.
Note that the x and y axes are included in fig. 1 to show two orthogonal directions in the wafer plane. The x-direction is the bit line direction and the y-direction is the word line direction. Note that the x-direction and y-direction are interchangeable; that is, the x-direction may be a word line direction, and the y-direction may be a bit line direction. It should also be noted that the z-axis is included in fig. 1 to further illustrate the spatial relationship of components in the 3D PCM device 100. The substrate (not shown) of the 3D PCM device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the back side opposite the front side of the wafer. The z-axis is perpendicular to the x-and y-axes. As used herein, when a substrate is positioned in a z-direction in a lowermost plane of a semiconductor device (e.g., 3D PCM device 100), it is determined in the z-direction (a vertical direction perpendicular to an x-y plane) whether one component (e.g., layer or device) of the semiconductor device is "on," "above," or "below" another component (e.g., layer or device) relative to the substrate of the semiconductor device. The same concepts used to describe the spatial relationships are applied throughout this disclosure.
As shown in fig. 1, the 3D PCM device 100 includes one or more top PCM cells 151, each top PCM cell 151 disposed at an intersection of a top bitline 131 and a corresponding wordline 141/143, and one or more bottom PCM cells 153, each bottom PCM cell 153 disposed at an intersection of a bottom bitline 133 and a corresponding wordline 141/143. In some embodiments, each of the top PCM cell 151 or the bottom PCM cell 153 has a vertical square pillar shape. In some embodiments, each of the top PCM cell 151 or the bottom PCM cell 153 includes at least a vertically stacked PCM element and a selector. Each of the top PCM cell 151 or the bottom PCM cell 153 stores a single bit of data and may be written or read by changing a voltage applied to a corresponding selector (not shown), which replaces the need for a transistor. Each of top PCM cell 151 or bottom PCM cell 153 is individually accessed by a current applied through top and bottom conductors (e.g., respective word line 141/143 and top or bottom bit line 131 or 133) in contact with each PCM cell. The top PCM cell 151 or the bottom PCM cell 153 in the 3D PCM device 100 is arranged in a memory array. In some embodiments, a PCM element may include a chalcogenide component including at least one of germanium (Ge), antimony (Sb), tellurium (Te), indium (In), or gallium (Ga). In some embodiments, each of bit lines 131, 133 and word line 141/143 includes a metal, such as tungsten. In some embodiments, the PCM element may be a binary (two-element) compound, such as GaSb, InSb, InSe, SbTe, or GeTe; ternary (three-element) compounds, such as GeSbTe, GaSeTe, InSbTe, SnSbTe or InSbGe; or quaternary (four-element) compounds, such as AgInSbTe, (GeSn) SbTe, GeSb (SeTe), or TeGeSbS. In some embodiments, the selector may be an Ovonic Threshold Switch (OTS) device made of at least one of oxygen (O), sulfur (S), selenium (Se), tellurium (Te), germanium (Ge), antimony (Sb), silicon (Si), or arsenic (As). The OTS device is formed of an OTS material that exhibits OTS characteristics.
Furthermore, as shown in fig. 1, the 3D PCM device 100 may also include one or more top bitline contacts 121 connected to the top bitline 131, one or more bottom bitline contacts 123 connected to the bottom bitline 133, and one or more wordline contacts 125 connected to the wordline 141/143. The top bitline contact 121, the bottom bitline contact 123, and the wordline contact 125 may extend vertically in the z-direction. In some implementations, each of the top bit line contact 121, the bottom bit line contact 123, and the word line contact 125 includes a metal, such as tungsten.
Fig. 2A and 2B illustrate side views of schematic cross-sections of an example 3D PCM memory device 100, according to some aspects of the present disclosure. In fig. 2A, in a y-z plane cross section, 3D PCM memory device 100 includes a plurality of parallel top bitlines 131 formed on top PCM cells 151 (not shown in the figure) and a plurality of parallel bottom bitlines 133 formed above bottom PCM cells 153 (not shown in the figure). Word line 141/143 extends laterally in the y-direction between top PCM cell 151 and bottom PCM cell 153. In fig. 2B, in an x-z plane cross section, the 3D PCM memory device 100 includes a top bitline 131 extending laterally in the x-direction and connected to a top bitline contact 121 extending vertically in the z-direction. The 3D PCM memory device 100 further comprises a bottom bitline 133 extending laterally in the x-direction and connected to a bottom bitline contact 123 extending vertically in the z-direction. In some implementations, the top bitline contact 121 and the wordline contact 125 extend vertically in areas where either the top PCM cell 151 or the bottom PCM cell 153 is not formed above or below.
Fig. 3 illustrates a perspective view of an exemplary 3D PCM device 300 according to some embodiments of the present disclosure. The 3D PCM device 300 includes one or more parallel bottom bit lines 333 (e.g., corresponding to the bottom bit lines 133 in fig. 1), one or more parallel top bit lines 331 (e.g., corresponding to the bottom bit lines 131 in fig. 1) in the same plane above the bottom bit lines 333, one or more parallel word lines 341/343 (e.g., corresponding to the word lines 141/143 in fig. 1) in the same plane vertically between the bottom bit lines 333 and the top bit lines 331. As shown in fig. 3, each bottom bitline 333 and each top bitline 331 extend laterally in plan view (parallel to the wafer plane) along a bitline direction (e.g., the x-direction), and each wordline 341/343 extends laterally in plan view along a wordline direction (e.g., the y-direction). In plan view, each word line 341/343 intersects each bottom bit line 333 and each top bit line 331. In some embodiments, each word line 341/343 is perpendicular to each bottom bit line 333 and each top bit line 331.
As shown in FIG. 3, the 3D PCM device 300 includes one or more top PCM cells 351 (e.g., corresponding to top PCM cells 151 of FIG. 1) and one or more bottom PCM cells 353 (e.g., corresponding to top PCM cells 153 of FIG. 1), where each top PCM351 cell is disposed at the intersection of a top bitline 331 and a corresponding wordline 341/343, and each bottom PCM353 cell is disposed at the intersection of a bottom bitline 333 and a corresponding wordline 341/343. In some embodiments, each of the top PCM cell 351 or the bottom PCM cell 353 has a vertical square pillar shape. In some embodiments, each of the top PCM cell 351 or the bottom PCM cell 353 includes at least a vertically stacked PCM element (not shown) and a selector (not shown). Each of the top PCM cell 351 or the bottom PCM cell 353 stores a single bit of data and can be written or read by changing a voltage applied to a corresponding selector (not shown), which replaces the need for a transistor. Each of the top PCM cell 351 or the bottom PCM cell 353 is individually accessed by a current applied through top and bottom conductors (e.g., a respective word line 341/343 and a top bit line 331 or a bottom bit line 333) in contact with each PCM cell. Either the top PCM cell 351 or the bottom PCM cell 353 in the 3D PCM device 300 is arranged in a memory array. The 3D PCM device 300 may also include one or more top bitline contacts 321 (e.g., corresponding to the top bitline contacts 121 in fig. 1) connected to the top bitline 331, one or more bottom bitline contacts 323 (e.g., corresponding to the bottom bitline contacts 123 in fig. 1) connected to the bottom bitline 333, and one or more wordline contacts 325 (e.g., corresponding to the wordline contacts 125 in fig. 1) connected to the wordline 341/343. The top bitline contact 321, the bottom bitline contact 323, and the wordline contact 325 may extend vertically in the z-direction. In some embodiments, each of the top bitline contact 321, the bottom bitline contact 323, and the wordline contact 325 comprises a metal, such as tungsten.
The 3D PCM device 300 may include one or more top interconnect layers 365 (also referred to as top metal layers or M5 layers) extending laterally over memory cells (e.g., top PCM cell 351 or bottom PCM cell 353) of a memory array. The 3D PCM device 300 may also include one or more first interconnect layers 364 (also referred to as M4 layers) extending laterally under memory cells (e.g., top PCM cell 351 or bottom PCM cell 353) of the memory array. The 3D PCM device 300 may also include one or more via contacts 327 extending vertically (e.g., in the z-direction) and connected between the top interconnect layer 365 and the first interconnect layer 364.
Fig. 4A and 4B illustrate side views of schematic cross-sections of an example 3D PCM device 300 according to some aspects of the present disclosure. In fig. 4A, in a y-z plane cross section, a 3D PCM device 300 includes a plurality of parallel top bitlines 331 formed on a top PCM cell 351 (not shown), and a plurality of parallel bottom bitlines 333 formed above a bottom PCM cell 353 (not shown). Word line 341/343 extends laterally in the y-direction between top PCM cell 351 and bottom PCM cell 353. Top interconnect layer 365 (also referred to as a top metal layer or M5 layer) extends laterally over memory cells (e.g., top PCM cell 351 or bottom PCM cell 353) of the memory array. In some implementations, the top interconnect layer 365 extends in a y-direction perpendicular to the bit lines and parallel to the word lines. The first interconnect layer 364 extends laterally in the x-direction or the y-direction under memory cells (e.g., top PCM cell 351 or bottom PCM cell 353) of the memory array. The via contact 327 extends vertically in the z-direction and connects between the top interconnect layer 365 and the first interconnect layer 364. In some embodiments, the via contact 327 may extend further into, or through the substrate.
In fig. 4B, in an x-z plane cross section, the 3D PCM device 300 includes a top bitline 331 extending laterally in the x-direction and connected to a top bitline contact 321 extending vertically in the z-direction. The 3D PCM device 300 also includes a bottom bitline 333 extending laterally in the x-direction and connected to a bottom bitline contact 323 extending vertically in the z-direction. In some implementations, the top bitline contact 321 and the wordline contact 325 extend vertically in an area where either the top PCM cell 351 or the bottom PCM cell 353 are not formed above or below.
As shown in fig. 4A and 4B, the 3D PCM device 300 may further include one or more peripheral blocks located below the memory array. The peripheral block may include one or more peripheral cells including a bottom bit line selector 303, a word line driver 305, or a top bit line selector 301. This can also be seen in fig. 5A and 5B, where the 3D PCM device 300 includes a substrate 307 and one or more peripheral cells including a bottom bitline selector 303, a wordline driver 305, or a top bitline selector 301 formed on the substrate 307. Word line driver 305 may be connected to word line 341/343 via word line contact 325. A plurality of interconnect layers, such as top interconnect layer 365, first interconnect layer 364, second interconnect layer 363 (also referred to as an M3 layer), third interconnect layer 362 (also referred to as an M2 layer), fourth interconnect layer 361 (also referred to as an M1 layer), may extend laterally (e.g., in the x-direction or y-direction) and be connected between word lines or bit lines via contacts. Substrate 307 may comprise silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. In some embodiments, each of the word line drivers (e.g., word line driver 305), bit line drivers, or bit line selectors (e.g., bottom bit line selector 303 and top bit line selector 301) includes a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, or a combination thereof.
Fig. 6A and 6B illustrate layouts of example peripheral blocks of a memory device according to some aspects of the present disclosure. As shown in fig. 6A, a 3D PCM memory device 600 (e.g., which may correspond to the 3D PCM device 300) may include a peripheral block including a wordline driver region 605, two bottom bitline selector regions 603 arranged on both sides (e.g., in a middle portion of the two sides) of the wordline driver region 605, and two top bitline selector regions 601 arranged on both sides (e.g., in a bottom portion of the two sides) of the wordline driver region 605. The word line driver region 605 may include one or more word line drivers (e.g., word line drivers 305 in fig. 4A, 4B, 5A, and 5B) formed thereon. The bottom bit line selector region 603 may include one or more bottom bit line selectors (e.g., bottom bit line selector 303 of fig. 4A, 4B, 5A, and 5B) formed thereon. The top bit line selector region 601 may include one or more top bit line selectors (e.g., top bit line selector 301 in fig. 4A, 4B, 5A, and 5B) formed thereon.
In addition, the peripheral blocks in the 3D PCM memory device 600 may further include one or more local data line regions 609 formed between the word line driver region 605 and the bottom bit line selector region 603 or between the word line driver region 605 and the top bit line selector region 601. The local data line region 609 may include one or more local data lines formed thereon. In some embodiments, the local data lines are configured to transfer data between global bit lines or word lines and local bit lines or word lines.
In addition, the peripheral blocks in the 3D PCM memory device 600 may also include one or more bitline driver regions 607 (or also referred to as Y driver regions as they extend in the Y direction) formed between respective bottom and top bitline selector regions 603 and 601. The bit line driver region 607 may include one or more bit line drivers formed thereon.
Since the word line driver regions (e.g., word line driver region 605) are formed between the bottom bit line regions and between the top bit line regions, each peripheral block may have four remaining regions (e.g., first remaining region 6501, second remaining region 6503, third remaining region 6505, and fourth remaining region 6507) separated by the word line driver region 605, bottom bit line selector region 603, and top bit line selector region 601. These remaining regions may have the same well potential and may be connected via additional wiring to achieve the same well potential. These remaining regions may also have other peripheral cells or metal wiring formed thereon.
Further, a plurality of bottom bit lines 633 (e.g., corresponding to bottom bit lines 333), top bit lines 631 (e.g., corresponding to top bit lines 331), and word lines 641 (e.g., corresponding to word lines 341) can be formed and extend laterally over the peripheral block. For example, the bottom bitline 633 and top bitline 631 can extend in the x-direction, while the wordline 641 can extend in the y-direction. These word lines and bit lines may be connected to corresponding drivers and selectors by contacts (e.g., bottom bit line contact 323, top bit line contact 321, and word line contact 325 in fig. 4A-5B) formed in contact areas (e.g., bottom bit line contact area 623, top bit line contact area 621, and word line contact area 625, as shown in fig. 6B). Note that because the word line contacts (e.g., word line contact 325 in fig. 5A) extend vertically and connect between the word line contact region (e.g., word line contact region 625 in fig. 6B) and the word line (e.g., word line 341/343 in fig. 5A), the bit lines cannot be formed above the word line driver region 605, as shown in fig. 6A. This therefore limits the flexibility of routing through the word line regions. Furthermore, as described above, the extended width of the contacts may have a detrimental effect on the array efficiency of the overall memory device. Furthermore, the separated remaining areas may require additional wiring for connection.
In addition, power lines may be required to supply power to the peripheral units in each peripheral block. As shown in fig. 7, laterally extending first interconnect layer 664 (e.g., corresponding to first interconnect layer 364 in fig. 5A-5B), second interconnect layer 663 (e.g., corresponding to second interconnect layer 363 in fig. 5A-5B), and top interconnect layer 665 (e.g., corresponding to top interconnect layer 365 in fig. 5A-5B) may not be able to efficiently transfer power to the peripheral cells in each peripheral block. For example, the power supply may be transmitted through the top interconnect layer 665 to the first interconnect layer 664, from the first interconnect layer 664 to the second interconnect layer 663, and from the second interconnect layer 663 to each peripheral unit. This requires the first interconnect layer 664 to have a larger width to transmit sufficient power. As a result, large gaps (e.g., the gaps shown in fig. 7) are formed between the peripheral blocks, thereby reducing array efficiency.
Fig. 8A and 8B illustrate a layout of an example peripheral block of a memory device according to some aspects of the present disclosure. The peripheral block in the 3D memory device 800 includes a first word line driver region 8051 in the second quadrant of the peripheral block, a second word line driver region 8053 in the fourth quadrant of the peripheral block, a first bit line selector region in the third quadrant of the peripheral block (e.g., including the first bottom bit line selector region 8031 and the first certain bit line selector region 8011), and a second bit line selector region in the first quadrant of the peripheral block (e.g., including the second bottom bit line selector region 8033 and the second top bit line selector region 8013). Note that the quadrants herein are used to illustrate the respective locations of these regions. For example, the first and second word line driver regions 8051, 8053 may be symmetrically arranged on opposite sides of a plane, line, or point. The first top bitline selector region 8011 and the second top bitline selector region 8013 may be symmetrically arranged on opposite sides of a plane, line or point. And the first bottom bitline selector region 8031 and the second bottom bitline selector region 8033 can be symmetrically arranged on opposite sides of a plane, line or point.
In addition, the peripheral blocks in the 3D PCM memory device 800 may further include one or more local data line regions 809 formed adjacent to the first bottom bitline selector region 8031, the first top bitline selector region 8011, the second top bitline selector region 8013, and the second bottom bitline selector region 8033. In some embodiments, the local data line region 809 is formed on a side of the bit line selector region opposite to a side adjacent to the word line driver region. The local data line region 809 may include one or more local data lines formed thereon. In some embodiments, the local data lines are configured to transfer data between global bit lines or word lines and local bit lines or word lines.
In addition, the peripheral blocks in the 3D PCM memory device 800 may further include one or more first bit line driver regions 8071 (or also referred to as Y driver regions because they extend in the Y direction) formed between the respective first bottom bit line selector regions 8031 and first top bit line selector regions 8011, and one or more second bit line driver regions 8073 formed between the respective second bottom bit line selector regions 8033 and second top bit line selector regions 8013.
Since the word line driver regions (e.g., the first word line driver region 8051 and the second word line driver region 8053) are arranged in different quadrants, each peripheral block may have two remaining regions (e.g., the first remaining region 8501 and the second remaining region 8503) in respective quadrants (e.g., the second quadrant and the fourth quadrant). Two remnant areas may require fewer wiring paths to interconnect than four remnant areas (as shown in fig. 6A).
In addition, a plurality of first bottom bit lines 8331, first top bit lines 8311, second bottom bit lines 8313, second top bit lines 8333, and word lines 841 may be formed over the peripheral blocks and extend laterally. For example, first bottom bit line 8331, first top bit line 8311, second bottom bit line 8313, and second top bit line 8333 may extend in the x-direction, while word line 841 may extend in the y-direction. These word lines and bit lines may be connected to respective drivers and selectors by contacts (e.g., bottom bit line contact 323, top bit line contact 321, and word line contact 325 in fig. 5A) formed in contact regions (e.g., first bottom bit line contact region 8231, first top bit line contact region 8211, second bottom bit line contact region 8233, second top bit line contact region 8213, word line contact region 825, as shown in fig. 8B).
Specifically, as shown in FIG. 8B, a first bottom bit line contact region 8231 is formed in an upper portion of the first bottom bit line selector region 8031 and adjacent to the word line contact region 825. A second bottom bit line contact region 8233 is formed in a lower portion of the second bottom bit line selector region 8033 and adjacent to the word line contact region 825. A first top bit line contact region 8211 is formed in a lower portion of first top bit line selector region 8011 and adjacent to word line contact region 825. A second top bitline contact region 8213 is formed in an upper portion of second top bitline selector region 8013. Since the word line contact region 825 may be separated from the first and second word line driver regions 8051 and 8053, the bit lines 8331, 8311, 8313, and 8333 may be formed over the word line driver regions. More wiring flexibility can be achieved. In some embodiments, these contact areas, which are separate and independent from the areas of the peripheral units, may be shared by adjacent peripheral blocks.
In addition, as described above, power supply lines may be required to supply power to the peripheral units in each peripheral block. As shown in fig. 9, one or more via contacts 927 (e.g., corresponding to 327 in fig. 3) may be formed between and separate adjacent peripheral blocks (e.g., between first peripheral block 9001 and second peripheral block 9002). Top interconnect layer 965 (e.g., corresponding to top interconnect layer 365 in fig. 5A-5B) can efficiently transfer power to each peripheral block via respective via contacts 927, and laterally to each peripheral cell.
Further, by mirroring adjacent peripheral blocks, remaining areas in the adjacent blocks (e.g., remaining area 8501 of peripheral block 9001 and its adjacent remaining area in peripheral block 9002) may be combined. Thus, the layout configuration provides a better and easier routing path for connecting these remaining areas.
Also, as shown in fig. 10, the 3D PCM memory device 800 may include a plurality of blocks (e.g., a first block (tile)9010 and a second block 9020) of peripheral blocks (e.g., a first peripheral block 9001, a second peripheral block 9002, a third peripheral block 9003, and the like). Each peripheral block may be separated by a via contact 927 extending in the x-direction and by a plurality of top bit line contacts (e.g., second top bit line contact region 8213 of first peripheral block 9001 and first top bit line contact region 8215 of third peripheral block 9003) extending in the y-direction. In some embodiments, the second top bit line contact region 8213 of the first peripheral block 9001 and the first top bit line contact region 8215 of the third peripheral block 9003 are arranged in parallel aligned with each other and may be shared by bit line selector regions in adjacent blocks. In some embodiments, each peripheral block may be used to control a respective memory block including memory cells (e.g., 351, 353 in fig. 5A) formed above.
According to an aspect of the present disclosure, a memory device includes a peripheral block and a memory block on the peripheral block. The peripheral block includes a first wordline driver region in a second quadrant of the peripheral block, a second wordline driver region in a fourth quadrant of the peripheral block, a first bitline selector region in a third quadrant of the peripheral block, and a second bitline selector region in a first quadrant of the peripheral block.
In some embodiments, the peripheral block further includes a first bitline driver region in a third quadrant of the peripheral block and a second bitline driver region in the first quadrant of the peripheral block.
In some embodiments, the memory device further includes a plurality of bit line drivers in the first bit line driver region and the second bit line driver region, and each bit line driver includes a p-channel metal oxide semiconductor (PMOS) transistor, an n-channel metal oxide semiconductor (NMOS) transistor, or a combination thereof.
In some embodiments, the first bit line selector region includes a first bottom bit line selector region and a first top bit line selector region, and the second bit line selector region includes a second bottom bit line selector region and a second top bit line selector region.
In some embodiments, the first bit line driver region is between the first bottom bit line selector region and the first top bit line selector region, and the second bit line driver region is between the second bottom bit line selector region and the second top bit line selector region.
In some embodiments, the peripheral block further comprises a plurality of local data line regions, each local data line region adjacent to a first bottom bit line selector region, a first top bit line selector region, a second bottom bit line selector region, or a second top bit line selector region.
In some embodiments, the peripheral block further includes a first bottom bit line contact region adjacent to the first bottom bit line selector region, a first top bit line contact region adjacent to the first top bit line selector region, a second bottom bit line contact region adjacent to the second bottom bit line selector region, and a second top bit line contact region adjacent to the second top bit line selector region.
In some embodiments, the peripheral block further includes a word line contact region adjacent to the first word line driver region and the second word line driver region.
In some embodiments, the memory block further includes a plurality of top Phase Change Memory (PCM) cells, a plurality of bottom PCM cells, a top bitline connected to the top PCM cells and extending laterally in a first direction, a bottom bitline connected to the bottom PCM cells and extending laterally in the first direction, and a wordline connected between the top PCM cells and the bottom PCM cells and extending laterally in a second direction, wherein the first direction is perpendicular to the second direction.
In some embodiments, the memory device further includes a plurality of bottom bit line contacts extending vertically and connected between the bottom bit lines and the first bit line selector region or between the bottom bit lines and the second bit line selector region, a plurality of top bit line contacts extending vertically and connected between the top bit lines and the first bit line selector region or between the top bit lines and the second bit line selector region, and a plurality of word line contacts extending vertically and connected between the word lines and the first word line driver region or between the word lines and the second word line driver region.
In some embodiments, the memory device further includes a substrate, and the peripheral bump is formed on the substrate.
In some embodiments, the memory device further includes a plurality of word line drivers in the first word line driver region and the second word line driver region. Each word line driver includes a PMOS transistor, an NMOS transistor, or a combination thereof.
In some embodiments, the memory device further includes a plurality of bit line selectors in the first and second bit line selector regions, and each bit line selector includes a PMOS transistor, an NMOS transistor, or a combination thereof.
In some embodiments, the first and second word line driver regions are symmetrically arranged, and the first and second bit line selector regions are symmetrically arranged.
According to another aspect of the present disclosure, a memory device includes a plurality of peripheral blocks and a plurality of memory blocks. Each memory block is on a corresponding peripheral block. Each peripheral block includes a first wordline driver region in a second quadrant of the respective peripheral block, a second wordline driver region in a fourth quadrant of the respective peripheral block, a first bitline selector region in a third quadrant of the respective peripheral block, and a second bitline selector region in a first quadrant of the respective peripheral block.
In some embodiments, the memory device further includes a plurality of via regions separating the plurality of peripheral blocks. Two adjacent peripheral blocks are mirror symmetric along one of the via regions.
In some embodiments, the memory device further includes a plurality of via contacts extending vertically in each of the plurality of via regions, a top interconnect layer extending laterally over the plurality of memory blocks, and a first interconnect layer extending laterally under the plurality of memory blocks. One of the via contacts is connected between the top interconnect layer and the first interconnect layer.
In some embodiments, each memory block further includes a plurality of top Phase Change Memory (PCM) cells, a plurality of bottom PCM cells, a top bitline connected to the top PCM cells and extending laterally in a first direction, a bottom bitline connected to the bottom PCM cells and extending laterally in the first direction, and a wordline connected between the top PCM cells and the bottom PCM cells and extending laterally in a second direction. The first direction is perpendicular to the second direction.
In some embodiments, the memory device further includes a plurality of bottom bit line contacts extending vertically and connected between the bottom bit lines and the first bit line selector region or between the bottom bit lines and the second bit line selector region, a plurality of top bit line contacts extending vertically and connected between the top bit lines and the first bit line selector region or between the top bit lines and the second bit line selector region, and a plurality of word line contacts extending vertically and connected between the word lines and the first word line driver region or between the word lines and the second word line driver region.
In some implementations, the first interconnect layer is connected to one of a bottom bitline contact, a top bitline contact, or a wordline contact.
In some implementations, each of the plurality of memory blocks is configured to store 16 million (M) bits.
In some embodiments, each peripheral block further includes a first bit line driver region in the third quadrant of the respective peripheral block, and a second bit line driver region in the first quadrant of the respective peripheral block.
In some embodiments, the first bit line selector region includes a first bottom bit line selector region and a first top bit line selector region, and the second bit line selector region includes a second bottom bit line selector region and a second top bit line selector region.
In some embodiments, each peripheral block further includes a first bottom bit line contact region adjacent to the first bottom bit line selector region, a first top bit line contact region adjacent to the first top bit line selector region, a second bottom bit line contact region adjacent to the second bottom bit line selector region, and a second top bit line contact region adjacent to the second top bit line selector region.
In some embodiments, the first top bit line contact region and the adjacent second top bit line contact region of adjacent peripheral blocks are arranged side-by-side and are configured to be shared top bit line contact regions.
The foregoing description of the specific embodiments will so fully reveal the general nature of the disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications such specific embodiments, without undue experimentation, without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.
Embodiments of the present disclosure have been described above with the aid of functional building blocks illustrating embodiments of specific functions and relationships thereof. Boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries may be defined so long as the specified functions and relationships thereof are appropriately performed.
The summary and abstract sections may set forth one or more, but not all exemplary embodiments of the present disclosure as contemplated by the inventor(s), and are therefore not intended to limit the present disclosure and the appended claims in any way.
The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims (25)

1. A memory device, comprising:
a peripheral block; and
a memory block on the peripheral block, wherein the peripheral block comprises:
a first word line driver region in a second quadrant of the peripheral block;
a second word line driver region in a fourth quadrant of the peripheral block;
a first bit line selector region in a third quadrant of the peripheral block; and
a second bit line selector region in a first quadrant of the peripheral block.
2. The memory device of claim 1, wherein the peripheral block further comprises:
a first bit line driver region in the third quadrant of the peripheral block; and
a second bit line driver region in the first quadrant of the peripheral block.
3. The memory device of claim 2, further comprising:
a plurality of bit line drivers in the first bit line driver region and the second bit line driver region, and each of the bit line drivers includes a p-channel metal oxide semiconductor (PMOS) transistor, an n-channel metal oxide semiconductor (NMOS) transistor, or a combination thereof.
4. The memory device of claim 2, wherein the first bit line selector region comprises:
a first bottom bit line selector region; and
a first top bit line selector region, and wherein the second bit line selector region comprises:
a second bottom bit line selector region; and
a second top bit line selector region.
5. The memory device of claim 4, wherein the first bit line driver region is between the first bottom bit line selector region and the first top bit line selector region, and the second bit line driver region is between the second bottom bit line selector region and the second top bit line selector region.
6. The memory device of claim 4 or 5, wherein the peripheral block further comprises:
a plurality of local data line regions, each of the local data line regions adjacent to the first bottom bit line selector region, the first top bit line selector region, the second bottom bit line selector region, or the second top bit line selector region.
7. The memory device of any of claims 4-6, wherein the peripheral block further comprises:
a first bottom bit line contact region adjacent to the first bottom bit line selector region;
a first top bit line contact region adjacent to the first top bit line selector region;
a second bottom bit line contact region adjacent to the second bottom bit line selector region; and
a second top bit line contact region adjacent to the second top bit line selector region.
8. The memory device of any of claims 1-7, wherein the peripheral block further comprises:
a word line contact region adjacent to the first word line driver region and the second word line driver region.
9. The memory device of any of claims 1-8, wherein the memory block further comprises:
a plurality of top Phase Change Memory (PCM) cells;
a plurality of bottom PCM cells;
a top bitline connected to the top PCM cell and extending laterally in a first direction;
a bottom bitline connected to the bottom PCM cell and extending laterally in the first direction; and
a wordline connected between the top PCM cell and the bottom PCM cell and extending laterally in a second direction, wherein the first direction is perpendicular to the second direction.
10. The memory device of claim 9, further comprising:
a plurality of bottom bit line contacts extending vertically and connected between the bottom bit lines and the first bit line selector region or between the bottom bit lines and the second bit line selector region;
a plurality of top bit line contacts extending vertically and connected between the top bit lines and the first bit line selector region or between the top bit lines and the second bit line selector region; and
a plurality of word line contacts extending vertically and connected between the word line and the first word line driver region or between the word line and the second word line driver region.
11. The memory device of any of claims 1-10, further comprising:
a substrate, wherein the peripheral mass is formed on the substrate.
12. The memory device of any of claims 1-11, further comprising:
a plurality of word line drivers in the first and second word line driver regions, each of the word line drivers comprising a PMOS transistor, an NMOS transistor, or a combination thereof.
13. The memory device of any of claims 1-12, further comprising:
a plurality of bit line selectors in the first and second bit line selector regions, each of the bit line selectors comprising a PMOS transistor, an NMOS transistor, or a combination thereof.
14. The memory device of any one of claims 1-13, wherein the first and second word line driver regions are symmetrically arranged and the first and second bit line selector regions are symmetrically arranged.
15. A memory device, comprising:
a plurality of peripheral blocks; and
a plurality of memory blocks, each of the memory blocks being on a respective peripheral block, wherein each of the peripheral blocks comprises:
a first word line driver region in a second quadrant of the corresponding peripheral block;
a second word line driver region in a fourth quadrant of the corresponding peripheral block;
a first bit line selector region in a third quadrant of the respective peripheral block; and
a second bit line selector region in a first quadrant of the corresponding peripheral block.
16. The memory device of claim 15, further comprising:
a plurality of via regions separating the plurality of peripheral blocks, wherein two adjacent peripheral blocks are mirror symmetric along one of the via regions.
17. The memory device of claim 16, further comprising:
a plurality of via contacts extending vertically in each of the plurality of via regions;
a top interconnect layer extending laterally over the plurality of memory blocks; and
a first interconnect layer extending laterally under the plurality of memory blocks, wherein one of the via contacts is connected between the top interconnect layer and the first interconnect layer.
18. The memory device of claim 17, wherein each of the memory blocks further comprises:
a plurality of top PCM cells;
a plurality of bottom PCM cells;
a top bitline connected to the top PCM cell and extending laterally in a first direction;
a bottom bitline connected to the bottom PCM cell and extending laterally in the first direction; and
a wordline connected between the top PCM cell and the bottom PCM cell and extending laterally in a second direction, wherein the first direction is perpendicular to the second direction.
19. The memory device of claim 18, further comprising:
a plurality of bottom bit line contacts extending vertically and connected between the bottom bit lines and the first bit line selector region or between the bottom bit lines and the second bit line selector region;
a plurality of top bit line contacts extending vertically and connected between the top bit lines and the first bit line selector region or between the top bit lines and the second bit line selector region; and
a plurality of word line contacts extending vertically and connected between the word line and the first word line driver region or between the word line and the second word line driver region.
20. The memory device of claim 19, wherein the first interconnect layer is connected to one of the bottom bitline contact, the top bitline contact, or the wordline contact.
21. The memory device of any one of claims 15-20, wherein each of the plurality of memory blocks is configured to store 16 million (M) bits.
22. The memory device of any one of claims 15-21, wherein each of the peripheral blocks further comprises:
a first bit line driver region in the third quadrant of a respective peripheral block; and
a second bit line driver region in the first quadrant of the corresponding peripheral block.
23. The memory device of any one of claims 15-22, wherein the first bit line selector region comprises:
a first bottom bit line selector region; and
a first top bit line selector region, and wherein the second bit line selector region comprises:
a second bottom bit line selector region; and
a second top bit line selector region.
24. The memory device of claim 23, wherein each of the peripheral blocks further comprises:
a first bottom bit line contact region adjacent to the first bottom bit line selector region;
a first top bit line contact region adjacent to the first top bit line selector region;
a second bottom bit line contact region adjacent to the second bottom bit line selector region; and
a second top bit line contact region adjacent to the second top bit line selector region.
25. The memory device of claim 24, wherein the first top bitline contact region and an adjacent second top bitline contact region of adjacent peripheral blocks are arranged side-by-side and configured to be a shared top bitline contact region.
CN202180004837.1A 2021-12-14 2021-12-14 Memory device and layout thereof Pending CN114375475A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/CN2021/137804 WO2023108406A1 (en) 2021-12-14 2021-12-14 Memory device and layout of the same

Publications (1)

Publication Number Publication Date
CN114375475A true CN114375475A (en) 2022-04-19

Family

ID=81142288

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202180004837.1A Pending CN114375475A (en) 2021-12-14 2021-12-14 Memory device and layout thereof

Country Status (2)

Country Link
CN (1) CN114375475A (en)
WO (1) WO2023108406A1 (en)

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2793917A1 (en) * 2010-04-13 2011-10-20 Mosaid Technologies Incorporated Phase change memory with double write drivers
US10658427B2 (en) * 2018-10-18 2020-05-19 Micron Technology, Inc. Memory for embedded applications
KR20210141589A (en) * 2019-04-30 2021-11-23 양쯔 메모리 테크놀로지스 씨오., 엘티디. 3D memory device with 3D phase change memory
WO2022241660A1 (en) * 2021-05-19 2022-11-24 Yangtze Advanced Memory Industrial Innovation Center Co., Ltd Three-dimensional phase-change memory devices and forming method thereof
CN113470712B (en) * 2021-06-29 2022-09-30 长江先进存储产业创新中心有限责任公司 Phase change memory and control circuit thereof

Also Published As

Publication number Publication date
WO2023108406A1 (en) 2023-06-22

Similar Documents

Publication Publication Date Title
US8116129B2 (en) Variable resistance memory device and method of manufacturing the same
US10586593B2 (en) Programmable resistive device and memory using diode as selector
US7453716B2 (en) Semiconductor memory device with stacked control transistors
CN109216542B (en) Variable resistance memory device and method of manufacturing the same
KR100640641B1 (en) Semiconductor memory device having a stacked memory cell and method for manufacturing a stacked memory cell
US20200321519A1 (en) Resistive memory device and method of manufacturing the resistive memory device
US8958229B2 (en) Nonvolatile memory device and method of fabricating same
US20230354725A1 (en) Semiconductor apparatus
US20240138274A1 (en) Semiconductor memory device
CN114375475A (en) Memory device and layout thereof
WO2022151182A1 (en) Phase-change memory cell and method for fabricating the same
CN112840459B (en) Phase change memory cell structure and method of manufacturing the same
CN109768159B (en) memory device
WO2023087131A1 (en) Phase-change memory device and method for forming the same
US11672132B2 (en) Variable resistance memory device
WO2023004609A1 (en) Phase-change memory device and method for forming the same
CN114793471A (en) Three-dimensional memory device and method of manufacturing the same
US20230380194A1 (en) Cross-point architecture for pcram
CN112602152A (en) Memory device having memory cells with multiple threshold voltages and methods of forming and operating the same
KR20220006998A (en) Variable resistance memory device
KR20220003944A (en) Semiconductor memory device
KR20220133015A (en) Resistive memory device

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination