CN112470283A

CN112470283A - Method for reducing thermal crosstalk in 3D cross-point memory arrays

Info

Publication number: CN112470283A
Application number: CN202080002909.4A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2021-03-09
Anticipated expiration: 2040-10-10
Also published as: CN112470283B; WO2022073222A1

Abstract

Systems, methods, and apparatus are described that are capable of reducing the amount of thermal crosstalk between cells in a three-dimensional array of memory cells through the use of a laminate material, which in turn allows for smaller scaled fabrication of memory cells. In the disclosed methods, systems, and devices, a gap between adjacent memory cells is filled with a sacrificial material, and the sacrificial material is later removed to form an air gap. These air gaps are very effective for reducing thermal cross-talk between adjacent cells. It allows scaling to smaller memory cells and pitches with less impact from thermal effects of adjacent cell programming. In addition, it reduces thermal cross-talk between adjacent 3D cross-point memory cells, has good mechanical support during cell fabrication, and improves the scalability of the 3D cross-point memory.

Description

Method for reducing thermal crosstalk in 3D cross-point memory arrays

Technical Field

The present disclosure relates generally to three-dimensional electronic memories. More particularly, the present disclosure relates to the use of lamination, wet etching, oxides, and the formation of air pockets in the geometry of a three-dimensional memory array to increase certain characteristics or properties of the memory array or to reduce undesirable characteristics in the memory array.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become challenging and expensive. Therefore, the memory density of the planar memory cell approaches the upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells.

A Phase Change Memory (PCM) cell is a non-volatile solid-state memory technology that utilizes reversible heat-assisted switching of a phase change material, such as a chalcogenide compound, e.g., GST (germanium antimony tellurium), between states having different resistances. A basic memory cell ("cell") can be programmed to a number of different states or levels exhibiting different resistance characteristics. Programmable cell states can be used to represent different data values, thereby allowing the storage of information.

PCM cells are programmed or erased by self-heating to induce an amorphous or crystalline state to represent 1 and 0. The programming current is directly proportional to the size and cross-sectional area of the PCM cell. In a single level PCM device, each cell may be SET to one of two states, a "SET" state and a "RESET" state, allowing one bit to be stored per cell. In the RESET state (which corresponds to a fully amorphous state of the phase change material), the resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase change material can be transformed into a low resistance, fully crystalline state. This low resistance state provides the SET state of the cell. If the cell is subsequently heated to a high temperature above the melting point of the phase change material, the material reverts to the fully amorphous RESET state upon rapid cooling.

Due to the nature of self-heating, cross-talk occurs when programming adjacent cells. Crosstalk is the interference between signals. Due to process technology scaling, the spacing between adjacent interconnects is reduced. Turning on one signal affects the other. In the worst case this may cause a change in the value of another cell, or it may delay signal transitions, affecting timing. This is classified as a signal integrity problem.

In addition, large programming current requirements also result in large programming voltage requirements due to IR drop (voltage current x resistance). Reading and writing of data in PCM cells is accomplished by applying appropriate voltages to the phase change material via a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes the phase change material to joule heat to an appropriate temperature to induce the desired cell state when cooled. Reading of a PCM cell is performed using cell resistance as a measure of the cell state. The applied read voltage causes a current to flow through the cell, which current depends on the resistance of the cell. Measurement of the cell current thus provides an indication of the programmed cell state. A sufficiently low read voltage is used for the resistance measurement to ensure that the application of the read voltage does not disturb the programmed cell state. Cell state detection may then be performed by comparing the resistance metric to a predefined reference level. The programming current (I) is typically on the order of 100-200 μ A. If the Word Line (WL) and bit line (class B) in a cell encounter large resistances, the voltage drop can be significant.

Therefore, a need exists to reduce the programming current and thermal cross-talk between Phase Change Memory (PCM) cells.

Disclosure of Invention

In creating the techniques of the present invention, it has been recognized that while three-dimensional (3D or 3-D) memory architectures can address the density limitations of planar memory cells, 3D configurations can present new technical challenges. Other technical problems arise as the desired features of 3D memory architectures are pursued (e.g., increased density of 3D cells, or reduction in the fabrication size of the cells).

One example of such a problem is thermal cross-talk between cells. Thermal crosstalk occurs when heat generated from one point or cell within a 3D cell array is transferred to an adjacent cell at another point or cell. During operation of a 3D memory architecture, heat generated from one cell can disturb the normal or desired operation of the cell. The problems due to thermal cross-talk between cells become more and more pronounced as the cell size decreases. Because of the smaller inter-cell distance, smaller spacing or scaling when creating a 3D memory architecture increases the amount or speed of heat transfer between one cell and another. Due to thermal crosstalk, the ability to scale to smaller sizes while still having a functional 3D memory array is compromised.

Accordingly, there is a need for methods, systems, and devices that can overcome conventional methods of creating 3D memory arrays and allow scaling of 3D memory arrays while making them operable despite thermal crosstalk.

Methods, systems, and apparatus for filling gaps between adjacent memory cells with a sacrificial material are shown and described. The sacrificial material is later removed to form air gaps. These air gaps are very effective for reducing thermal cross-talk between adjacent cells. It allows scaling to smaller memory cells and pitches with less impact from thermal effects of adjacent cell programming. In addition, it reduces thermal cross-talk between adjacent 3D cross-point memory cells, provides good mechanical support during cell fabrication, and improves the scalability of the 3D cross-point memory.

In some exemplary embodiments, the electrodes and/or the memory cells may be vertically arranged, and in other exemplary embodiments, the electrodes and/or the memory cells may be horizontally arranged. In some examples, combinations of orientations are possible.

In one aspect, the pillar memory cells are isolated from each other in both the X and Y directions by an air gap. In another aspect, a method for forming a 3D cross-point memory cell array includes: the method includes forming parallel memory cell lines, protecting the memory cell lines with an encapsulation layer, filling gaps between the memory cell lines with a sacrificial film material, performing vertical line patterning to form isolated memory cell pillars, removing the sacrificial material to form air gaps, and forming air gaps in both X and Y directions with a non-conformal gap filler. Yet another additional aspect includes a method for forming a 3D cross-point memory cell array, comprising: forming parallel memory cell lines, protecting the memory cell lines with an encapsulation layer, forming air gaps in one direction with a non-conformal gap filler, performing vertical line patterning to form isolated memory cell pillars, removing sacrificial material to form air gaps; and forming air gaps in both the X and Y directions with a non-conformal gap filler.

In one embodiment of the present technology, a three-dimensional memory includes: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer that three-dimensionally and at least partially encapsulates the first memory cell, the second memory cell, and the electrode such that the first memory cell and the second memory cell are exposed on at least one surface; and an air gap residing between the first storage cell and the second storage cell.

Other embodiments of the present technology may include, for example, any combination of: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer that three-dimensionally and at least partially encapsulates the first memory cell, the second memory cell, and the electrode; configuring the first storage unit and the second storage unit to be exposed on at least one surface; depositing a first layer using a chemical vapor deposition process; depositing a first layer using an atomic deposition method; a second layer at least partially and three-dimensionally surrounding the first layer; a plurality of additional layers, wherein the plurality of layers completely occupy the intra-cellular space; forming the first layer, the second layer, or the additional layer from a dielectric material; selecting a dielectric material includes, but is not limited to, selecting a dielectric material from: nitride layer (NIT), aC or electrode layer, phase change material, ovonic threshold switch material (OTS), or tungsten (W), and the group comprising oxynitride, phase change material, ovonic threshold material, tungsten, nanoporous silicon, Hydrogen Silicates (HSQ), Teflon-AF (polytetrafluoroethylene or PTFE), fluorinated silicon oxide (FSG), lead zirconate titanate (PZT), silicon nitride, tantalum pentoxide, aluminum oxide, zirconium dioxide, hafnium dioxide, and any combination thereof; forming the first layer and the second layer from different materials; the first and second layers are composed of materials selected to minimize heat reflection values.

For example, other embodiments of the invention may include methods that may include, for example, any combination of: providing a first storage unit; providing a second storage unit; providing an electrode electrically connecting the first memory cell and the second memory cell; creating a first layer that three-dimensionally encapsulates the first memory cell, the second memory cell, and the electrode; exposing the first and second memory cells on at least one surface; creating a second layer that at least partially and three-dimensionally surrounds the first layer; creating a plurality of layers such that the plurality of layers partially occupy the intra-cell space; creating an air gap encapsulated by at least one layer; creating an air gap residing in the intra-cell space; removing material between the intra-cell spaces beyond a top of the first storage unit or the second storage unit; adding an electrode substantially on a surface exposed by removing material above a top of the first memory cell or the second memory cell.

Drawings

The foregoing aspects, features and advantages of the disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be employed for the sake of clarity. However, aspects of the disclosure are not intended to be limited to the specific terminology used.

FIG. 1 is an isometric view of a portion of a three-dimensional cross-point memory of the prior art.

Figure 2 is a plan view of a portion of a three-dimensional cross-point memory of the prior art.

Fig. 3A, 3B, and 3C are cross-sectional views of portions of a three-dimensional crosspoint memory and an energy grid created by the memory of an embodiment.

Fig. 4 is a graph showing a relationship between the disturbance current and the resistance of the memory cell.

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sections of a three-dimensional cross-point memory according to an embodiment of the invention.

Fig. 6 depicts a method according to an exemplary embodiment of the present disclosure.

FIG. 7A, FIG. 7B, FIG. 7C-1, FIG. 7C-2, FIG. 7D, FIG. 7E-1, FIG. 7E-2, FIG. 7E-3, and FIG. 7F are cross-sections of a three-dimensional cross-point memory according to an embodiment of the present invention.

Fig. 8 depicts a method according to an exemplary embodiment of the present disclosure.

Detailed Description

The present disclosure addresses the challenges and problems associated with existing and current methods, systems, and devices. The use of lamination, wet etching, oxidation, and changing the shape of particular layers in the geometry of a three-dimensional memory array (i.e., current-sensitive layers in programmable current storage cells) to increase certain characteristics or properties of the storage cells or to reduce undesirable characteristics in the memory array, among other things, is disclosed. Embodiments and examples are shown herein that illustrate the principles of the present disclosure. The present disclosure is not in any way limited to these embodiments and examples, which are presented solely for the purpose of explaining the underlying principles. While specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to those skilled in the art that the present disclosure may also be used in various other applications.

It is noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., merely indicate that the embodiment described may include a particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Further, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

In general, terms may be understood at least in part by the context in which they are used. For example, the term "one or more" as used herein may be used to describe any feature, structure, or characteristic in the singular or may be used to describe a combination of features, structures, or characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" again may be understood to convey a singular use or to convey a plural use, depending at least in part on the context.

It should be readily understood that the meaning of "on.. above," "over.. and" over.. in this disclosure should be interpreted in the broadest manner such that "on.. above" not only means "directly on something," but also includes the meaning of "on something (with intervening features or layers therebetween)," and "on.. above" or "over.. above" not only means "on or over something," but also includes the meaning of "on or over something (without intervening features or layers therebetween)" (i.e., directly on something).

Furthermore, spatially relative terms (e.g., "below," "lower," "above," "upper," etc.) may be used herein to simplify description in order to describe one element or feature's relationship to another element or feature as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The term "substrate" as used herein may refer to any workpiece on which it is desired to form or process a layer of material. Non-limiting examples include silicon, germanium, silicon dioxide, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, spinel, silicon oxide, silicon carbide oxide, glass, gallium nitride, indium nitride, aluminum nitride, glass, combinations or alloys thereof, and other solid materials. The substrate itself may be patterned. The material added atop the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a wide variety of semiconductor materials including, but not limited to, silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

As used herein, the term "layer" refers to a portion of material that includes a region having a thickness. The layer may extend over the entire underlying or overlying structure or may have a smaller extent than the extent of the underlying or overlying structure. Furthermore, a layer may be a region of a homogeneous or inhomogeneous continuous structure having a thickness that is less than the thickness of the continuous structure. For example, a layer may be located between any pair of horizontal planes between or at the top and bottom surfaces of a continuous structure. The layers may extend horizontally, vertically, and/or along a tapered surface. The substrate may be a layer, may include one or more layers in the substrate, and/or may have one or more layers on, above, and/or below the substrate. The layer may comprise multiple layers. For example, the interconnect layer may include one or more conductors and contact layers (in which contacts, interconnect lines, and/or vias are formed) and one or more dielectric layers.

The term "horizontal" as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term "vertical" will refer to a direction perpendicular to the horizontal as previously defined. Terms such as "above," "below," "bottom," "top," "side" (e.g., sidewall), "upper," "lower," "upper," "above," and "below" are defined with respect to the horizontal plane. The term "on …" indicates that there is direct contact between the elements. The term "above …" will allow for intermediate elements.

As used herein, a material (e.g., a dielectric material or an electrode material) will be considered "crystalline" if it exhibits greater than or equal to 30% crystallinity as measured by techniques such as x-ray diffraction (XRD). Amorphous material is considered to be amorphous.

As used herein, the terms "first," "second," and other ordinal words are to be understood as merely providing distinction, and not imposing any particular spatial or temporal order.

As used herein, the term "oxide" of an element will be understood to include additional components in addition to the element and oxygen, including but not limited to dopants or alloys. As used herein, the term "nitride" of an element will be understood to include additional components in addition to the element and nitrogen, including but not limited to dopants or alloys.

Heat transfer occurs through three major physical phenomena, convection, conduction, and radiation. Radiation is a method of energy transfer that does not rely on any contact between the heat source and the heated object. Conduction, on the other hand, is the transfer of heat between substances that are in direct contact with each other. The conductivity between objects in contact with each other depends on the specific physical properties of these objects. For example, conduction through an object depends on the thermal resistance of the material constituting the object. In the circuit, heat transfer may occur by any such phenomenon.

Conduction can also be conceptualized as occurring through phonons. Phonons are collective excitations in the periodic elastic arrangement of matter. Phonons are quasi-particles that can represent the vibrational characteristics of a material or various vibrational modes of an elastic material, and also describe the interactions between interacting particles of an elastic material. Heat in dielectric materials and semiconductors is transmitted primarily through phonons. Depending on the embodiment, the dielectric material may include, but is not limited to, oxynitride, phase change material, ovonic threshold material, tungsten, nanoporous silicon, Hydrogen Silicates (HSQ), Teflon-AF (polytetrafluoroethylene or PTFE), silicon oxyfluoride (FSG), lead zirconate titanate (PZT), silicon nitride, tantalum pentoxide, aluminum oxide, zirconium dioxide, hafnium dioxide, and any combination thereof

When an object is composed of more than one material, the overall thermal resistance of the material may be considered to be composed of the thermal resistances of the constituent materials. However, the presence of more than one material in a system or object creates a thermal boundary resistance between these materials. Phonons may also undergo scattering in materials by interacting with defects, other phonons, grain boundaries, different isotopes in the material, and various other physical causes. A temperature discontinuity occurs in the region of the interface between two materials when heat passes through the interface (i.e., when phonons move from one material to the other). The thermal resistance boundary is also referred to as the interfacial thermal resistance or Kapitza resistance, which is a measure of the resistance of the interface to heat flow. Thermal resistance boundaries are also defined as the ratio of the temperature discontinuity at an interface to the heat flux flowing through the interface, and are caused by strong phonon reflections as phonons attempt to pass through the interface of one material with another. When a phonon moves from one material to another (such as, for example, from material a to material B), a portion of the phonon energy is reflected back to material a (i.e., reflected) and some energy is conducted to material B (i.e., conducted).

A higher thermal resistance boundary can be designed by selecting the materials that make up the object, or by creating an additional boundary through which phonons must pass. A higher thermal resistance boundary may slow the rate at which heat is transferred by conduction. In addition, by having several materials in the proper configuration, many boundaries can be created through which phonons must pass.

In addition to increasing the thermal boundary between surfaces, a closed air gap between two cells can also increase thermal resistance. This is because energy must be emitted and radiated from the layer into the air layer, and then re-radiated from the air layer to the second boundary in order to be transferred from one unit to another. In addition, the air itself (which occupies a volume) has a specific calorific value, which allows the air to absorb heat before it starts to re-transmit the heat to the second boundary. Properties due to increased air thickness (such as attenuation of thermal resistance) can be observed. In addition, the emissivity of the arrangement can also be designed by varying the thickness of the air gap.

The present technology is directed to solving problems associated with heat transfer in three-dimensional memories. A general example of a three-dimensional (3D) memory is shown in fig. 1. Specifically, FIG. 1 is an isometric view of a portion of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first-level memory cells 5 and the second-level memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. Above the first-layer memory cells 5 in the depth (Z) direction are a plurality of first bit lines 20 extending in the vertical (Y) direction, and below the second-layer memory cells 10 are a plurality of second bit lines 25 extending in the Y direction.

As also shown in fig. 1, the sequential structure of bit lines, memory cells, word lines, memory cells may be repeated in the Z-direction to create a stacked configuration. In the example of fig. 1, the first-tier stack may include first-tier memory cells 5, bit lines 20, and word lines 15, and the second-tier stack may include second-tier memory cells 10, bit lines 25, and word lines 15. Thus, although the first tier memory cells 5 and the second tier memory cells 10 each have their respective set of

bit lines

20 and 25, the first tier memory cells 5 and the second tier memory cells 10 may share the same set of word lines 15. Although the example of fig. 1 shows a 4-layer stacked configuration, in other examples, the stacked configuration may include any number of memory layers and other elements. In any case, an individual memory cell in the structure can be accessed by selectively activating the word line and bit line corresponding to that cell.

To selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown). The word line decoder is coupled to the word lines by word line contacts (not shown) and is used to decode word line addresses so that a particular word line is activated when that word line is addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts (not shown) and is used to decode the bit line address so that a particular bit line is activated when addressed. Thus, the stacked configuration of the memory may also include bit line contacts and decoders, and word line contacts and decoders for selectively activating bit lines and word lines in the stack. For example, the stacked configuration may be arranged as an array of elements, where each array includes a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders. The word line decoders and contacts, and the positioning of the bit line decoders and contacts are shown and discussed further with reference to FIG. 2.

Fig. 2 is a plan view of a portion of a three-dimensional cross-point memory of a prior configuration. The figure depicts the portion as viewed in the Z (depth) direction. In this example, the stacking configuration is a 2-layer stack. The stacked configuration includes multiple arrays of memory cells, including two

top cell arrays

60 and 61 and two

bottom cell arrays

65 and 66. Although individual memory cells are not shown in fig. 2, they are shown by fig. 1, for example, in a top array, the memory cells may be arranged as the first layer memory cells 5 shown in fig. 1, and in a bottom array, the memory cells may be arranged as the second layer memory cells 10 shown in fig. 1.

The portion includes word and bit lines, word and bit line contacts, and word and bit line decoders corresponding to the top and bottom cells. As shown, a plurality of word lines (e.g., word line 30) extend in the X (horizontal) direction and correspond to both the top and bottom cells. The portion also includes a plurality of top cell bit lines (e.g., bit lines 35) extending in the Y (vertical) direction and corresponding to the top cell array 60 of memory cells, and a plurality of bottom cell bit lines (e.g., bit lines 40) extending in the vertical direction and corresponding to the bottom cell array 65 of memory cells. The word lines, top cell bit lines, and bottom cell bit lines are typically formed from a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. Further, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

The word lines in fig. 2 are horizontally aligned for a given cell array. For example, as shown, word lines of the

cell arrays

60, 61, 65, and 66 are all horizontally aligned with each other along the X-direction. Each of these word lines is shown extending across the entire width of the respective cell array. The top cell bit lines of a given top cell array or the bottom cell bit lines of a given bottom cell array are vertically aligned. For example, the top cell bit line 35 is vertically aligned along the Y-direction, and the bottom cell bit line 40 is vertically aligned along the Y-direction. The top cell bit lines of the top cell array and the bottom cell bit lines of the overlapping bottom cell array (e.g., top cell bit line 35 and bottom cell bit line 40) are also horizontally aligned with each other, although they are shown slightly offset in fig. 2 to clearly illustrate the two layers. Each of these bit lines is shown extending across the entire length of the respective cell array.

The memory portion of fig. 2 includes a word line contact region 45, a top cell bit line contact region 50, and a bottom cell bit line contact region 55. The word line contact region 45 is elongated in the vertical direction while the top cell bit line contact region 50 and the bottom cell contact region 55 are elongated in the horizontal direction. The word line contact area 45 includes a plurality of word line contacts (e.g., contacts 45a) that are shown as dots surrounded by the word line contact area 45. The top bit line contact region 50 includes a plurality of word line contacts (e.g., contacts 50a) that are shown as points surrounded by the top cell bit line contact region 50. The bottom cell bit line contact region 55 includes a plurality of bottom cell bit line contacts (e.g., contacts 55a) that are considered to be points surrounded by the bottom cell bit line contact region 55.

The word line contacts and bit line contacts are connected to the middle of the respective word lines and bit lines. Thus, as shown, word line contact region 45 is located in the horizontal middle of word line 40, bottom cell bit line contact region 55 is located in the vertical middle of bottom cell bit line 40, and top cell bit line contact region 50 is located in the vertical middle of top cell bit line 35. Since the word lines of a given cell array are horizontally aligned, the word line contacts of the given cell array are also substantially aligned in the horizontal direction. Similarly, since the bit lines of a given cell array are vertically aligned, the bit line contacts of the given cell array are also substantially aligned in the vertical direction.

The word line contact region 45 also includes a plurality of word line decoders (not shown). The word line decoder generally conforms to the word line contact area and generally extends in a vertical direction. The word line decoder is coupled to a word line through a word line contact. The top cell bit line contact region 50 also includes a plurality of top cell bit line decoders (not shown). The top cell bit line decoder generally conforms to the top cell bit line contact region 50 and generally extends in a horizontal direction. A top cell bitline decoder is coupled to the top cell bitline through a top cell bitline contact. The bottom cell bit line contact region 55 also includes a plurality of bottom cell bit line decoders (not shown). The bottom cell bit line decoder generally conforms to the bottom cell bit line contact region 55 and generally extends in a horizontal direction. The bottom cell bit line decoder is coupled to the bottom cell bit line through a bottom cell bit line contact.

As can be seen from fig. 1, the prior art memory does not contain any material for preventing heat transfer between one cell and the next. Methods and systems capable of preventing heat transfer between storage units without interfering with memory operations are described below.

Referring to fig. 3A, 3B and 3C, thermal crosstalk can be observed between an active or perturbing cell (through which current is passed) and an inactive or perturbed cell. Although fig. 3A, 3B, and 3C are represented in two dimensions, they represent physical phenomena occurring in three dimensions.

Fig. 3A shows an active cell 305 (also referred to as a scrambling cell 305) and an inactive or disturbed cell 310, where the distance between the 3D cells is approximately 90 nanometers depending on the implementation. During normal operation of the memory cell, the scrambling unit 305 generates heat when current is passed through the scrambling unit 305. The heat generated by scrambling unit 305 is represented by field 315. The field 315 may represent a gradient or distribution of temperature. That is, the field 315 may represent a particular temperature at a particular physical space by mapping the space to a color that represents the temperature of the space. Alternatively, the field 315 may also be delineated by the proximity or density of lines to represent higher or lower temperatures at particular regions. Although field 315 is viewed in two dimensions in FIG. 3A, field 315 may be three-dimensional and extend outward from within perturbing cell 305 to a space surrounding cell 305. As can be seen in fig. 3A, heat generated from the scrambling from scrambling unit 305 is conducted across the intra-cell gap 320 to the victim unit 310.

Fig. 3B is a 45 nm anisotropy visualization of the heat transfer and temperature gradient generated by the perturbing unit. Fig. 3B shows a 3D cell structure scaled to a smaller pitch than fig. 3A. Compared to fig. 3A, the intra-cell distance between the disrupting unit and the disturbed unit is reduced, and, in turn, both the heat transferred to the disturbed unit and the temperature of the disturbed unit are increased. Thus, the reduced cell spacing and the increase in thermal effects to the victim unit (e.g., victim unit 330) affect the operational properties of the victim unit 340. The field 350 may represent a particular temperature at a particular physical space with the particular physical space mapped to a color gradient. As shown in fig. 3B, scrambling unit 330 affects victim unit 340 differently at different locations of victim unit 340. In fig. 3B, the disturbed cell 340 has a higher heat at one end of the cell than at the other end. This unequal distribution of temperature can affect the normal operation of the disturbed unit 340. For example, the expected resistance of the victim unit 340 may be unequal across the victim unit due to the heat.

Fig. 3C is a 45 nm isotropic visualization of the heat transfer and temperature gradient generated by the disrupting elements. An isotropic view is a view that treats all directions equally. Isotropic heat transfer occurs when heat is transferred at the same rate in all directions.

As can be seen from fig. 3A-3C, as the intra-cell distance is reduced, more heat is transferred between the cells. Further complicating this problem in three-dimensional memories is that, because the memory is stacked upon one another, the surface area and space from which heat is dissipated is reduced as compared to conventional substantially two-dimensional memories (in which heat can be dissipated to the ambient environment at a faster rate). For example, heat will not be removed quickly and efficiently from the intermediate memory layers of the three-dimensional memory as compared to a planar memory configuration. In addition, heat moving from one cell in the three-dimensional memory will propagate in all directions, heating all nearby cells.

Fig. 4 is a visual representation of the amount of current passing through a scrambling cell (e.g., scrambling cell 405) and the resistance of a victim cell (e.g., victim cell 410). FIG. 4 also shows a first word line 415, a second word line 420, a first bit line 425, and a second bit line 430. Current may pass through the word line and bit line, such as reset pulse 435. As can be seen from fig. 4, the victim cell resistance varies as a function of the current in the aggressor cell. The changing resistance of the victim unit can interfere with the normal operation of the victim unit. Fig. 4 shows that the resistance of the victim cell can change by an order of magnitude of 10 based on the increased current in the aggressor cell. The change in resistance of the victim unit (e.g., victim unit 410) occurs at least in part due to thermal energy generated by the jammer unit (e.g., jammer unit 405).

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sectional views of a three-dimensional cross-point memory according to an embodiment of the invention.

Fig. 5A shows a memory cell formed by deposition or stacking of materials. As can be seen in fig. 5A,

cells

510 and 520 are formed of similar materials and thus form parallel lines within the cell stack when viewed in two dimensions. Although not shown in fig. 5A, other components (such as those described above or known in the art) may be included in various configurations or combined with cells to implement an operable 3D cross-point memory.

Cells

510 and 520 may be created or stacked on an electrode (e.g., electrode 501).

Cells

510 and 520 may be made of various materials or elements, such as W, a-C, an Ovonic Threshold Switch (OTS), or PCM. For example,

cells

510 and 520 may be made up of several layers, such as, for example, layers 502, 503, 504, 505, and 506, which in turn may be made of elements such as W, a-C, an Ovonic Threshold Switch (OTS), or PCM. Fig. 5A illustrates the formation of a first thin niti (nit) (or oxynitride) encapsulation layer around the memory stack shown in fig. 5A. NIT is a commercially available alloy such as, for example, NIT 135. Any suitable material may be used to form the first layer 530. The first layer 530 may also be made of any suitable dielectric material. The dielectric material is selected to ensure that currents in the memory (e.g., cells 510 and 520) are not carried to undesired paths outside of those cells. Forming the first layer around the memory stack may be accomplished by a conformal coating technique. Conformal coating techniques provide technical advantages such as consistency of the coated material. However, the first layer may be formed around the memory stack using any suitable technique. In an exemplary embodiment, techniques such as Atomic Layer Deposition (ALD) may be used. Atomic layer deposition is a thin film deposition technique based on the sequential use of vapor deposition processes. Other variations of ALD techniques may be used to deposit the first thin layer.

Fig. 5B shows the formation of a second thin layer 540 around the first thin layer 530. The second thin layer 540 may be deposited by any suitable method, for example by using atomic layer deposition. However, any suitable deposition technique may be used. Layer 540 may be created from any suitable material, such as, but not limited to, silicon dioxide. In some examples, the layers may be made of different materials, while in other examples, some layers may be made of the same material.

Fig. 5C illustrates the formation of additional material, gap material 550, surrounding layer 540. The gap material 550 may be deposited by any suitable method, such as by using atomic layer deposition. However, any suitable deposition technique may be used. The gap material 540 may be created from any suitable material, such as, but not limited to, aluminum oxide or a high etch rate oxide. The gap material 550 may surround the layer 540 three-dimensionally, including but not limited to, the intra-cell space (e.g., the space between the cells 510 and 520).

Fig. 5D shows the deposition of metal (metal 590) at one end of cell 510 and cell 520 to form a word line. Any suitable metal may be selected as metal 590. For example, metal 590 may be deposited on top of the a-C electrodes of cell 510 and cell 520. Any material located beyond the a-C electrode may be removed using any suitable process in order to expose the a-C electrode so that metal 590 may be deposited on the a-C electrode. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar manner is suitable for removing excess material (e.g., a portion or all of

layers

530, 540, and 550). However, other suitable processes may be used to remove the excess material, such as, for example, shallow trench isolation. Therefore, materials must be selected for both processes to achieve planarization of cell 510 and cell 520, thereby exposing the a-C electrodes therein without damaging or otherwise modifying cell 510 or cell 520. The metal 590 may be deposited substantially perpendicular to the length of the

cells

510 and 520. The shape of the metal 590 may be planar (e.g., a rectangular piece of metal) and may extend beyond the

cells

510 and 520 and attach to a plurality of similar cells.

Fig. 5E is a top view of the layers of the cell. Fig. 5E illustrates the formation of an air gap. Fig. 5E also shows a number of units, such as unit 510, unit 520 and unit 521, unit 522, unit 523, unit 524, unit 525, unit 526 and unit 527. A word line may be added to a group of cells, such as, for example, to cell 522, cell 523, and cell 524. Word lines may also be added to cell 510, cell 522, and cell 525. Sacrificial materials (e.g., portions or all of

layers

520, 540, and gap material 550) located within the cells (i.e., e.g., between

cells

510 and 520, between

cells

510 and 522, between cells 525 and 526) may be selectively removed by an appropriate process. One such process is wet etching. Wet etching is a microfabrication technique. Wet etching is a material removal process by which liquid chemicals or etchants can be used to remove material. The wet etch may be isotropic (orientation independent) or anisotropic (orientation dependent). By using a wet etch, the sacrificial material (e.g., gap material 550) can thus be removed, creating air gaps in the intra-cell space, such as, for example, air gap 551, air gap 552, air gap 553, air gap 554, and air gap 555. The wet etch may create trenches or other geometries in the sacrificial material (e.g., the gap material 550).

Fig. 5F is a top view of the layers of the cell. Fig. 5F shows the formation of a buried air gap by oxide deposition. The process of oxide deposition may partially fill the trench, or other geometry created in the air gap. In this way, multiple air gaps can be created in the intra-cell space containing or enclosing the air gaps. In other words, the air gap may be closed and air pockets may be created between the sacrificial material and the material deposited by the oxide deposition. In this way, multiple air gaps, such as, for example, air gap 556, may be created.

The process described in fig. 5A-5F may be repeated again to create a stacked memory cell containing an intra-cell material layer. By stacking the electrodes, isolated memory cell pillars can be formed. By repeating the process described in fig. 5A-5F, each memory cell formed is thermally isolated from other memory cells within the memory cell stack. Thus, each cell may be surrounded by a plurality of air gaps.

One advantage of memory cells created as described above is reduced thermal cross-talk between cells. By increasing the thermal boundary resistance and creating multiple layers, thermal cross talk is reduced. Furthermore, by filling the gaps, additional mechanical support is provided to the entire three-dimensional memory structure, which is beneficial to reduce the size of the fabrication to smaller dimensions and to subsequent processing of the memory.

FIG. 6 depicts a method (method 600) according to an exemplary embodiment of the present disclosure. The method starts in step 605. In step 605, a memory cell may be formed by stack deposition on a substrate. The substrate may be a conductive material, such as an electrode. The memory cell may be formed by any suitable method, such as for example by atomic layer deposition. The memory cell may be formed to have an intra-cell gap. In step 610, a first layer may be formed over the memory cell. A first layer may be formed in three dimensions to surround and encapsulate the memory cells. The first layer may be formed of any suitable material, such as, for example, a dielectric material. In step 615, a second layer is deposited on top of and encapsulates the first layer. The second layer may be composed of any suitable material or combination of materials and deposited by any suitable method. In step 620, a gap material (e.g., gap material 550) may be deposited to encapsulate the second layer. The gap material may encapsulate the second layer in three dimensions. In step 625, the material located beyond the intra-cell gap and on top of the cell may be removed by any suitable technique. Material may be removed in a manner that allows a substantially flat and continuous surface to be created between the cells and the layers added in steps 605-620. In step 630, a substrate may be added where material was removed. The substrate may be added between memory cells (e.g., memory cell 510 and memory cell 520). In step 635, the sacrificial material added in the previous step may be removed by an appropriate method. One example of such a method is wet etching. In step 640, oxide may be deposited to surround the air pockets created by the wet etch. In the method, the air pocket may be enclosed and surround the storage unit. In step 645, steps 605-640 may be repeated as desired. The method ends at step 650.

Fig. 7A, 7B, 7C, 7D, 7E, 7F, 7G, 7H, and 7I are cross-sections of a three-dimensional cross-point memory according to an embodiment of the invention.

Fig. 7A shows a memory cell formed by deposition or stacking of materials. As can be seen in fig. 7A,

cells

710 and 720 are formed of similar materials, and thus form parallel lines within the cell stack when viewed in two dimensions. Although not shown in fig. 7A, other components (such as those described above or known in the art) may be included in various configurations or combined with cells to implement an operable 3D cross-point memory.

Cells

710 and 720 may be created or stacked on an electrode (e.g., electrode 701).

Cells

710 and 720 may be made of various materials or elements, such as W, a-C, an Ovonic Threshold Switch (OTS), or PCM. For example,

cells

710 and 720 may be made up of several layers, such as, for example, layers 702, 703, 704, 707, and 706, which in turn may be made of elements such as W, a-C, an Ovonic Threshold Switch (OTS), or PCM. FIG. 7A illustrates the formation of a first thin NIT encapsulation layer around the memory stack shown in FIG. 7A. NIT is a commercially available alloy such as, for example, NIT 135. Any suitable material may be used to form the first layer 730. The first layer 730 may also be made of any suitable dielectric material. The dielectric material is selected to ensure that currents in the memory (e.g., cells 710 and 720) are not carried to undesired paths outside of those cells. Forming the first layer around the memory stack may be accomplished by a conformal coating technique. Conformal coating techniques provide technical advantages such as consistency of the coated material. However, the first layer may be formed around the memory stack using any suitable technique. In an exemplary embodiment, techniques such as Atomic Layer Deposition (ALD) may be used. Atomic layer deposition is a thin film deposition technique based on the sequential use of vapor deposition processes. Other variations of ALD techniques may be used to deposit the first thin layer.

Fig. 7B shows the formation of a second layer 740 around the first thin layer 730. The second layer 740 may be a non-conformal oxide gap filler. Depending on the embodiment, the gap material 623 may be obtained by Atomic Layer Deposition (ALD) oxide, spin-on dielectric (SOD), or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap fillers include, but are not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), lead sulfide (PbS), and lead selenide (PbSe), as well as cobalt-based compounds and any combination thereof. The second layer 740 may be formed in a manner known as a break-loaf, i.e., the non-conformal gap may be thicker toward one end of the cells 710 and 720 (e.g., the deposition may be thicker closer to the layer 706). Thus, the second layer may be formed in three dimensions around layer 730, and the thickness of the layer may be non-uniform. The second layer 740 may be deposited using any suitable method.

Fig. 7C-1 shows the deposition of additional non-conformal oxide material 750 and partially surrounding the second layer 740. Material 750 may extend between layers 740, substantially bridging the gaps between layers 740 and forming a continuous surface. Material 750 may be made of any suitable material. Once the material 750 is deposited, the material 750 also causes intra-cell air gaps (e.g., air gap 751) between the cell 710 and the cell 720, and air gaps 752 adjacent to the cell 720. Fig. 7C-2 shows another view of depositing additional non-conformal oxide. Once the material 750 is deposited, the material 750 also causes intra-cell air gaps (e.g., air gap 751) between the cell 710 and the cell 720, and air gaps 752 adjacent to the cell 720.

Fig. 7D shows the exposed a-C electrode 705. Any suitable process may be used to remove any material beyond the electrode. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar manner is suitable for removing excess material (e.g., some or all of

layers

730, 740, and 750). Thus, the chemical mechanical process can create a substantially planar surface by removing material while preserving intra-cell air gaps, such as air gap 751 and air gap 752.

Fig. 7E-1 shows the deposition of metal 790 on top of one end of the cells (e.g., cell 710 and cell 720) to form the word line. For example, metal 790 may be deposited on top of the a-C electrodes of

cells

710 and 720. Any material located beyond the a-C electrode may be removed using any suitable process in order to expose the a-C electrode so that metal 790 may be deposited on the a-C electrode. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar manner is suitable for removing excess material (e.g., some or all of

layers

730, 740, and 750). However, other suitable processes may be used to remove the excess material, such as, for example, shallow trench isolation. Therefore, materials must be selected for both processes to achieve planarization of cell 510 and cell 520, thereby exposing the a-C electrodes therein without damaging or otherwise modifying cell 510 or cell 520. The metal 590 may be deposited substantially perpendicular to the length of the

cells

510 and 520 and attach to a plurality of similar cells.

Fig. 7E-2 shows a three-dimensional view of this technique. As shown in fig. 7E-2, it can be seen that the air gap extends in three dimensions. For example, the air gap 751 may extend in the x-direction.

Fig. 7E-3 is a top view of this technique. As shown in fig. 7E-3, it can be observed that there is an air gap 751 between

cells

710 and 720. Similarly, an air gap 752 adjacent to the cell 720 can be observed.

Fig. 7F shows a top view of this technique. Cell 7F shows several cells (e.g., cell 722, cell 723, cell 724, cell 725, cell 726, cell 727) and air gaps (e.g., air gap 756, air gap 755, and air gap 753). Additional individual cell pillars (e.g., cell 722, cell 723, and cell 724) may be formed by vertical wordline patterning, which forms parallel wordlines. Accordingly, the stack of materials (e.g., cell 710 and cell 720) may be further modified by any suitable technique to create additional individual pillar cells.

FIG. 8 depicts a method (method 800) according to an exemplary embodiment of the present disclosure. The method starts in step 805. In step 805, a memory cell may be formed by stack deposition on a substrate. The substrate may be a conductive material, such as an electrode. The memory cell may be formed by any suitable method, such as for example by atomic layer deposition. The memory cell may be formed to have an intra-cell gap. A first layer may be formed over the memory cell. A first layer may be formed in three dimensions to surround and encapsulate the memory cells in this step. The first layer may be formed of any suitable material, such as, for example, a dielectric material. In step 810, a second layer is deposited on top of and encapsulates the first layer. The second layer may be composed of any suitable material or combination of materials and deposited by any suitable method. The first layer may be a non-conformal oxide gapfill layer. The second layer may be deposited in a non-conformal manner, i.e. the deposition of the material may have a non-conformal thickness. In this way, the deposited material may be thicker on one side than the other, resulting in a smaller gap between the materials on one side. In step 815, a non-conformal oxide can be deposited on top of the existing layer, which can create a continuous layer of material at one end of the memory cell. This non-conformal oxide deposition may leave air gaps surrounded by the material deposited in step 805-815. The air gap may be an intra-cell gap. This process may occur such that the material also creates a continuous material bridge between the cells that extends at least along the length of the cells. For example, since the memory cells may be formed of different materials of different thicknesses, the materials may connect the various layers of the cells. In step 820, a technique such as chemical mechanical polishing or planarization may be used to remove material located beyond the cells. This step may also remove a portion of the electrode (e.g., the NIT layer of the electrode) such that the carbon electrode portions (a-C) of the cell are exposed. Since the material deposited in step 815 extends along the length of the electrodes, a portion of the material remains continuously connected after the process, and an intra-cell air gap remains formed after the material is removed. In step 820, a surface suitable for adding a wordline and that can expose a carbon portion of the cell can be created. In step 825, a word line may be deposited atop the surface created in step 820. The word line may be made of a metal material. The word line may allow electrical connectivity in the cell. Step 825 reserves the previously created air gap. In step 830, vertical wordline patterning may be performed to create individual pillar cells. Any suitable method may be used to create the vertical line pattern. Parallel word lines are formed by vertical line patterning. In addition, due to the non-conformal filler as described in the above step, air gaps may be formed in both directions around the cells (i.e., air gaps may exist between two cells, as well as in a direction perpendicular to that direction). In this way, a closed air gap can be created without affecting the usability of the memory cell. In step 835, steps 805-830 may be repeated as needed to stack or layer-by-layer the memory cells to create a 3D memory. The method ends at step 840.

Most of the foregoing alternatives are not mutually exclusive, but can be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. For example, the foregoing operations need not be performed in the exact order described. Rather, the various steps may be processed in a different order, such as an inverted order or concurrently. Steps may also be omitted unless otherwise noted. In addition, the provision of the examples described herein, as well as clauses phrased as "such as," "including," and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, these examples are intended to illustrate only one of many possible embodiments. Moreover, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional memory, comprising:

a first storage unit;

a second storage unit;

an electrode electrically connecting the first memory cell and the second memory cell;

an intra-cell space between the first storage unit and the second storage unit; and

a first layer that three-dimensionally, at least partially encapsulates the first memory cell, the second memory cell, and the electrode;

a first air gap surrounded three-dimensionally by at least the first layer; and

the first and second storage units are configured to be exposed on at least one surface.

2. The three-dimensional memory of claim 1, wherein the first layer is deposited using a chemical vapor deposition method.

3. The three-dimensional memory of claim 1, wherein the first layer is deposited using an atomic deposition method.

4. The three-dimensional memory of claim 1, further comprising a second layer at least partially and three-dimensionally surrounding the first layer.

5. The three-dimensional memory of claim 4, further comprising at least one additional layer.

6. The three-dimensional memory of claim 5, wherein the air gap is a vacuum.

7. The three-dimensional memory of claim 5, wherein the first layer, the second layer, and the at least one additional layer are comprised of a dielectric material.

8. The three-dimensional memory of claim 7, wherein the dielectric material is selected from the group consisting of: a nitride layer (NIT), aC or electrode layer, a phase change material, an ovonic threshold switch material (OTS), or tungsten (W) nanoporous silicon, Hydrogen Silicates (HSQ), Teflon-AF (polytetrafluoroethylene or PTFE), fluorinated silicon oxide (FSG), lead zirconate titanate (PZT), silicon nitride, tantalum pentoxide, aluminum oxide, zirconium dioxide, hafnium dioxide, and any combination thereof.

9. The three-dimensional memory of claim 2, wherein the first layer and the second layer are comprised of different materials.

10. The three-dimensional memory of claim 2, wherein the first layer and the second layer are comprised of a dielectric material.

11. A three-dimensional memory, comprising:

a top cell array of memory cells;

a bottom cell array of memory cells;

at least one electrode electrically connected to at least one of the top array of memory cells or the bottom array of memory cells; and

an in-memory space between the memory cells, wherein the in-memory space is filled with a plurality of layers that create a plurality of in-material interfaces; and

an air gap three-dimensionally surrounded by at least one of the plurality of layers.

12. The three-dimensional memory of claim 11, wherein the air gap is created and the memory space is partially filled.

13. A method of forming a three-dimensional memory, comprising:

providing a first storage unit;

providing a second storage unit;

providing an electrode electrically connecting the first memory cell and the second memory cell;

creating a first layer that three-dimensionally encapsulates the first memory cell, the second memory cell, and the electrode; and

creating an air gap, wherein the air gap is surrounded in three dimensions by at least the first layer; and

exposing the first memory cell and the second memory cell on at least one surface.

14. The method of claim 13, further comprising the steps of: the word lines are patterned to create a plurality of pillar cells.

15. The method of claim 14, further wherein the step of patterning the word line creates a plurality of air gaps around each pillar cell of the plurality of pillar cells.

16. The method of claim 15, further comprising: an encapsulation layer is provided.

17. The method of claim 13, further comprising the steps of:

creating a second layer that at least partially and three-dimensionally surrounds the first layer.

18. The method of claim 14, further comprising the steps of:

creating a plurality of layers such that the plurality of layers partially occupy the intra-cell space.

19. The method of claim 18, further comprising the steps of:

removing material between the intra-cell spaces beyond a top of the first storage cell or the second storage cell.

20. The method of claim 19, further comprising the steps of:

adding an electrode substantially on a surface exposed by removing material above a top of the first memory cell or the second memory cell.