CN112655094B - Recess liner confinement cell structure for 3D X point memory and method of manufacture - Google Patents

Abstract

A three-dimensional memory architecture includes a top cell array of memory cells, a bottom cell array of memory cells, a plurality of word lines and bit lines coupled to the array. The memory cell is a Phase Change Memory (PCM) cell that includes a recess liner confinement PCM material formed in a recess of a self-aligned liner electrode. The reduced contact area between the electrode and the PCM cell and the reduced cell material volume result in a reduced current required to program the cell. The larger distance between adjacent memory cells results in less thermal cross-talk. Having a PCM cell size that is smaller than the selector size allows for smaller current density requirements in the current selector (also referred to as a current limiter or current steering element) in the resistance-switching memory element.

Description

Recess liner confinement cell structure for 3D X point memory and method of manufacture

Technical Field

The present disclosure relates generally to three-dimensional electronic memories, and more particularly to reducing programming current and thermal cross-talk in adjacent memory cells.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and costly. Therefore, the storage density of the planar memory cell approaches the upper limit. A three-dimensional (3D) memory architecture may address density limitations in planar memory cells.

Phase Change Memory (PCM) is a non-volatile solid state memory technology that utilizes reversible, thermally assisted switching of phase change materials, such as chalcogenides, e.g., GST (germanium-antimony-tellurium), between states having different resistances. The basic memory cell ("cell") can be programmed to several different states or levels exhibiting different resistance characteristics. The programmable cell states may be used to represent different data values, allowing storage of information.

PCM cells are programmed or erased by thermal self-heating to induce an amorphous or crystalline state to represent 1 and 0. The programming current is proportional to the size and cross-sectional area of the PCM cell. In a single-level PCM device, each cell may be set to one of two states, a "set" state and a "reset" state, allowing one bit per cell to be stored. In the reset state, which corresponds to the completely amorphous state of the phase change material, the resistance of the cell is very high. By heating to a temperature above its crystallization point and then cooling, the phase change material can be transformed into a low resistance, fully crystalline state. The low resistance state provides the set state of the cell. If the cell is then heated to a high temperature above the melting point of the phase change material, the material returns to a fully amorphous reset state upon rapid cooling.

Due to the nature of thermal self-heating, cross-talk occurs when programming adjacent cells. Crosstalk is the interference between signals. As process technology shrinks, the spacing between adjacent interconnects shrinks. Switching on one signal may affect the other signal. In the worst case, this may cause the value of another element to change, or it may delay signal transitions that affect timing. This is classified as a signal integrity problem.

Furthermore, large programming current requirements are also suitable for large programming voltage requirements due to IR drop (ir=voltage=current x resistance). Reading and writing of data in PCM cells is achieved by applying appropriate voltages to the phase change material through a pair of electrodes associated with each cell. In a write operation, the resulting programming signal causes the phase change material to joule heat to an appropriate temperature to induce the desired cell state upon cooling. Reading of the PCM cell is performed using the cell resistance as a measure of the cell state. The applied read voltage causes a current to flow through the cell, which depends on the resistance of the cell. Thus, measurement of the cell current provides an indication of the programmed cell state. A sufficiently low read voltage is used for this resistance metric to ensure that the application of the read voltage does not interfere with the programmed cell state. Cell state detection may then be performed by comparing the resistance metric to a predefined reference level. The programming current (I) is typically on the order of 100-200 μA. If the Write Line (WL) and Bit Line (BL) in the cell encounter large resistances, the voltage drop can be quite large.

Accordingly, there remains a need for such memory cells that provide reduced programming current and reduced thermal cross-talk.

Disclosure of Invention

The following summary is included to provide a basic understanding of aspects and features of the present disclosure. This summary is not an extensive overview, and is therefore not intended to identify key or critical elements or to delineate the scope of the disclosure. Its sole purpose is to present concepts in a generalized format.

In one aspect, a novel recessed pad cell structure for a 3D X point memory is presented that allows for reduced programming current and reduced thermal cross-talk compared to prior art 3D X point memory cell structures. In the current new cell structure, each stack consists of vertical word lines and bit lines, with Phase Change Memory (PCM) in series with an Ovonic Threshold Switch (OTS) between the word lines and bit lines. The PCM memory cells and OTS select devices are self-aligned with the word lines and bit lines. The PCM memory cell is composed of a recess liner restriction cell formed in a bit line direction in a recess of the liner electrode.

In another aspect, a method is provided for forming a novel recessed liner confinement cell structure for a 3D X point memory that allows for reduced programming current and reduced thermal cross-talk compared to prior art 3D X point memory cell structures. The method includes forming a cross-point memory array having parallel Bit Lines (BL) and vertical Word Lines (WL). PCM memory cells in series with an Ovonic Threshold Switch (OTS) are formed at the intersection of WL and BL and are self-aligned. The recess liner confinement cell is formed by recessing the liner electrode and depositing PCM cell material in the recess, and planarizing by Chemical Mechanical Polishing (CMP).

In other aspects, a 3D X point memory die architecture includes a plurality of memory arrays (blocks) separated by small spaces. The memory array is comprised of a plurality of memory cells (PCM) with recessed pad limited memory cells and an Ovonic Threshold Switch (OTS).

According to one aspect, a three-dimensional memory having a recessed pad confinement cell structure includes: word lines and bit lines perpendicular to each other and coupled to at least one memory cell stack; a selector, a modified recessed liner confined phase change memory (rlcPCM) cell, a liner electrode, a first electrode, a second electrode, and a third electrode contained within the memory cell stack; an rlcPCM cell, a pad electrode disposed between the first electrode and the second electrode, and a selector disposed between the second electrode and the third electrode; the rlcPCM cell and the selector are confined between the word line and the bit line, and the rlcPCM is in series with the selector; a word line direction extending parallel to the word lines and a bit line direction extending parallel to the bit lines; wherein the rlcPCM cell and the selector are self-aligned with respect to the word line and the bit line; wherein the pad electrode further defines a recess, and the rlcPCM is formed in the bit line direction and in the recess of the pad electrode.

In some arrangements, both the rlcPCM cell and the pad electrode are disposed within the nitride layer, and the pad electrode is in a bottom position relative to the rlcPCM cell.

In some arrangements, the rlcPCM cell, the pad electrode, the selector, and the first, second, and third electrodes each have dimensions relative to the word line direction and the bit line direction; and the pad electrode and the rlpcm are smaller in size relative to the selector to provide a reduced required current to the rlpcm.

In some arrangements, the selector is an ovonic threshold switch and the cell stack further includes an encapsulation layer to protect the rlcPCM cell and the ovonic threshold switch.

In some arrangements, the three-dimensional memory includes additional memory cells in regions above or below the two-dimensional region defined by the word lines.

In some arrangements, the cell stack further includes a nitride layer, a tungsten layer, an oxide layer, a gap fill layer, and the first and second electrodes are carbon electrodes.

In some arrangements, the gap fill layer comprises a material selected from the group consisting of cobalt-based materials, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), and any combination thereof.

According to another aspect, a three-dimensional X-point memory die architecture with recessed pad confinement cell structure includes: a plurality of top arrays or blocks of phase change memory cells; a plurality of bottom arrays or blocks of phase change memory cells; a plurality of bit lines coupled to the top array and to the bottom array; a plurality of word lines including a set of top cell word lines coupled to a top array and a set of bottom cell word lines coupled to a bottom array; wherein the top arrays of memory cells are each separated by a first space defined by adjacent phase change memory cells and selectors with recessed liner restriction cells in the top arrays, and the bottom arrays of phase change memory cells are each separated by a second space defined by adjacent phase change memory cells and selectors with recessed liner restriction cells in the bottom arrays.

In some arrangements, a top word line and a bottom word line are coupled to the architecture.

In some arrangements, the top and bottom arrays of recessed pad confinement cells have a reduced size compared to the selectors disposed within each respective array.

In some arrangements, the selector is an ovonic threshold switch.

In yet another aspect, a method of forming a three-dimensional memory having a recessed liner confinement cell structure includes forming a cross-point memory array having a plurality of parallel bit lines and a plurality of vertical word lines; forming a recessed liner-limited phase change memory (rlcPCM) cell in series with an Ovonic Threshold Switch (OTS) select device at an intersection of a word line and a bit line; and wherein the rlcPCM cell is formed by recessing the liner electrode to form a recess, depositing a phase change memory cell material in the recess, and planarizing by Chemical Mechanical Planarization (CMP).

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considered with reference to the following description of exemplary embodiments and the accompanying drawings in which like reference numerals identify like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity.

However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

Fig. 1A and 1B are isometric views of existing portions and a single portion, respectively, of a three-dimensional cross-point memory.

Fig. 2A is an isometric view of a portion of a three-dimensional cross-point memory, and fig. 2B is a diagram showing abbreviations for layers in a cell stack.

Fig. 3A and 3B are plan views of a portion of a three-dimensional cross-point memory showing deposition of a nitride layer, and fig. 3C is a top view of fig. 3B.

Fig. 4A is a plan view of a portion of a three-dimensional cross-point memory showing pad electrode deposition followed by pad etching to form a pad electrode. Fig. 4B is a top view of fig. 4A. Fig. 4C is a plan view of a portion of the three-dimensional cross-point memory of fig. 4A showing recessing of the pad electrode and backfilling with PCM material. Fig. 4D is a top view of fig. 4C.

Fig. 5A and 5B are plan views of a three-dimensional cross-point memory showing bottom cell double patterning, wherein a first partial etch is used to etch through the top electrode and the memory cell, stopping on the middle electrode to form parallel lines, according to the embodiment of fig. 4A and 4B.

Fig. 6A and 6B are plan views of a three-dimensional cross-point memory according to the embodiment of fig. 5A and 5B, showing a bottom cell etch in which a second partial etch is used to etch to form parallel bottom cell bit lines, followed by packaging, gap filling and polishing.

Fig. 7A and 7B are plan views of a three-dimensional cross-point memory showing wordline metal deposition according to the embodiment of fig. 6A and 6B.

Fig. 8A and 8B are plan views of a three-dimensional cross-point memory showing bottom cell word line double patterning to form parallel lines, according to the embodiment of fig. 7A and 7B.

Fig. 9A and 9B are plan views of a three-dimensional cross-point memory showing packaging, gap filling and polishing cell stacks according to the embodiment of fig. 8A and 8B.

Fig. 10 is a plan view of a three-dimensional cross-point memory according to the embodiment of fig. 9A and 9B, showing a second stack of memory cell depositions on top of the stack shown in fig. 9A.

Detailed Description

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. One skilled in the relevant art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of the disclosure. It will be apparent to those skilled in the relevant art that the present disclosure may also be used in a variety of other applications.

It should be noted that references in the specification to "one embodiment," "an example embodiment," "some embodiments," etc., indicate that the embodiment described may include a particular feature, structure, or characteristic, but every embodiment may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases are not necessarily referring to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in connection with an embodiment, it is submitted that it is within the knowledge of one skilled in the relevant art to effect such feature, structure, or characteristic in connection with other embodiments whether or not explicitly described.

Generally, the terms may be understood, at least in part, from the usage in the context. For example, the term "one or more" as used herein, depending at least in part on the context, may be used to describe any feature, structure, or characteristic in a singular sense, or may be used to describe a feature, structure, or combination of features in a plural sense. Similarly, terms such as "a," "an," or "the" may also be construed to express singular usage or plural usage, depending at least in part on the context.

It should be readily understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … … means not only" directly on something "but also includes the meaning of" on something "with intermediate features or layers therebetween. Furthermore, "over … …" or "over … …" means not only "over" or "over" something, but may also include the meaning of "over" or "over" something (i.e., directly over something) without intermediate features or layers therebetween.

Further, spatially relative terms such as "under … …," "under … …," "lower," "over … …," "upper," and the like may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated. In addition to the orientations shown in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

As used herein, the term "substrate" may refer to any workpiece upon which it is desired to form or process a layer of material. Non-limiting examples include silicon, germanium, silicon dioxide, sapphire, zinc oxide, silicon carbide, aluminum nitride, gallium nitride, spinel, silicon carbide on silicon oxide, glass, gallium nitride, indium nitride, aluminum nitride, glass, combinations or alloys thereof, and other solid materials. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. In addition, the substrate may comprise a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, and the like. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafer.

As used herein, the term "layer" refers to a portion of material that includes regions having a thickness. The layers may extend over the entire underlying or overlying structure, or may have a range less than the range of the underlying or overlying structure. Further, the layer may be a region of uniform or non-uniform continuous structure having a thickness less than the thickness of the continuous structure. For example, the layers may be located between the top and bottom surfaces of the continuous structure or between any pair of lateral planes at the top and bottom surfaces. The layers may extend horizontally, vertically and/or along tapered surfaces. The substrate may be a layer, which may include one or more layers, and/or may have one or more layers thereon, and/or thereunder. The layer may comprise a plurality of layers. For example, the interconnect layer may include one or more conductive and contact layers (with contacts, interconnect lines, and/or vias formed therein) and one or more dielectric layers.

The term "horizontal" as used herein will be understood to be defined as a plane parallel to the plane or surface of the substrate, regardless of the orientation of the substrate. The term "vertical" will refer to a direction perpendicular to the horizontal as previously defined. Terms such as "above," "below," "bottom," "top," "side" (e.g., sidewall), "upper," "lower," "upper," "above," and "below" are defined with respect to a horizontal plane. The term "on … …" means that there is direct contact between the elements. The term "above … …" will allow for the insertion of an element.

As used herein, a material (e.g., a dielectric material or an electrode material) will be considered "crystalline" if it exhibits a crystallinity of greater than or equal to 30% (as measured by techniques such as X-ray diffraction (XRD)). Amorphous materials are considered amorphous materials.

As used herein, the terms "first," "second," and other ordinal terms are to be understood as merely providing a distinction and not to impose any particular interval or temporal order.

As used herein, the term "oxide" of an element will be understood to include additional components in addition to the element and oxygen, including but not limited to dopants or alloys. As used herein, the term "nitride" of an element will be understood to include additional components in addition to the element and nitrogen, including but not limited to dopants or alloys.

The technology is applied to the field of three-dimensional memories. A generalized previous example of a three-dimensional (3D) memory is shown in fig. 1A. In particular, FIG. 1A is an isometric view of a portion of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first layer memory cells 5 and the second layer memory cells are a plurality of word lines 15 extending in the X direction. Above the first layer of memory cells 5 are a plurality of first bit lines 20 extending in the Y direction, and below the second layer of memory cells are a plurality of second bit lines 25 extending in the Y direction. Further, as can be seen from the figure, the sequential structure of bit line-memory cell-word line-memory cell can be repeated in the Z-direction to achieve a stacked configuration. In any event, a single memory cell can be accessed by selectively activating the word line and bit line corresponding to that cell.

In fig. 1B, a single portion 100 of the cell structure of fig. 1A is shown. A top cell bit line 110 is shown connected to a top cell stack 150. The stack 150 is comprised of several layers, which will be described herein in the context of a modification of this standard stack 150. Perpendicular to the top cell bit line 110 are a top cell write line 130 and a bottom cell write line 140. Connected to the bottom cell write line 140 is a bottom cell stack 160. Parallel to the top cell bit line 110 is a bottom cell bit line 120. The bottom cell bit line 120 is coupled to the bottom cell stack 160. Similar to cell stack 150, cell stack 160 is also made of several layers. Fig. 1A and 1B illustrate the general structure of a 3D X point memory cell, which term is used herein to describe the improvement. Fig. 1A shows a portion viewed in the Z (depth) direction. The portion includes a plurality of word lines, such as word lines 130, 140, extending in the X (horizontal) direction, a plurality of top cell bit lines, such as bit lines 110, 120, extending in the Y (vertical) direction and corresponding to the top cell array of memory cells 150, and a plurality of bottom cell bit lines, such as bit lines 110, 120, extending in the vertical direction and corresponding to the bottom cell array of memory cells 160. The word lines, top cell bit lines, and bottom cell bit lines are typically formed according to a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. In addition, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

As described above, the adjacent cells may suffer from crosstalk problems. The present disclosure addresses this problem and the problem of reducing the current required by the memory cell. Reference is made to fig. 2A, which is a plan view of an exemplary three-dimensional cross-point bottom cell stack. Each stack is made up of several layers. The cell stack is similar in function and composition. For the description of the materials disclosed herein, like reference numerals for common elements in the various figures refer to like materials and functions of the illustrated and described elements.

In fig. 2A, a single portion 200 of the cell structure of an embodiment is shown. A bottom cell write line 210 is shown connected to a bottom cell stack 230. Perpendicular to the bottom cell write line 210 is a bottom cell bit line 220. Layer 201 is a nitride layer. Examples of such materials include metal nitrides such as TiN, tiAlN, taN, BN, metal oxide nitrides such as TiON, metal silicides such as PtSi, semiconductors such as silicon or germanium (doped or undoped), reduced metal oxides such as TiOx (x < 2 represents reduction), metals such as W, ni, co, or carbon-based materials. Typically, deposition may be accomplished by Chemical Vapor Deposition (CVD). In this method, a high quality, high performance solid material is prepared using a vacuum deposition method. In typical CVD, water (the substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Layers 202a, 202b and 206C are a-C or electrode layers. The electrodes may be formed of any convenient conductive material, typically a metallic material (e.g., pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material, such as silicon. According to embodiments, the electrode may be a carbon electrode or any other electrode known to a person skilled in the art. Layer 204 is a pad electrode. The pad electrode 204 may be formed of any convenient conductive material that may or may not be composed of the same (or substantially the same) elements. According to some embodiments, the pad electrode 204 may have a resistivity that is higher or lower than the resistivity of the electrode layers 202a, 202b, and 202 c. Layer 203 is a modified Phase Change Memory (PCM) cell or pit-limited PCM 203. As shown in fig. 2A, the recess-limited PCM 203 is recessed and/or limited in the nitride layer 201. PCM 203 is disposed between an electrode (e.g., electrode 202A) and a pad electrode 204 in the cell stack, as shown in fig. 2A. The memory cell 203 and the pad electrode 204 are disposed in or on the nitride layer 201. A selector or an Ovonic Threshold Switch (OTS) 205 is also provided between the two electrodes 202b, 202 c. Fig. 2B is a diagram illustrating abbreviations for the layers described herein. Furthermore, while the features described are particularly advantageous for multi-layer cells, in some embodiments, these features may also be advantageously applied in single layer cells.

As recognized using the present techniques described herein, existing configurations as illustrated in fig. 1A and 1B are inefficient in their use of memory regions (or "memory substrate planes"). This configuration is susceptible to crosstalk from neighboring cells, resulting in interference with the memory cells. Furthermore, as the number of cells increases, the power requirements increase significantly as the demand for additional memory increases. The new configurations disclosed provide improved memory cell density and bit line density and reduced cross talk and power required for memory cells. The new configuration includes PCMs 203, 503 that are reduced in size relative to the selectors and/or electrodes in their respective stacks. This reduced size and cross-sectional area can be seen, for example, starting from the process shown in fig. 3A and 3B to fig. 10.

Fig. 3A shows bottom cell stack deposition. Layer 301 may be a tungsten-based compound or a cobalt-based compound and serve as a conductor or the like. According to embodiments, the conductors may be made of other materials having conductive properties. Layers 202b and 202C are a-C or electrode layers. A selector or ovonic threshold switch (OTC) 205 is disposed between electrode layers 202b and 202 c. Layer 302 may be a substrate depending on the embodiment or represent a bottom bitline. In fig. 3B, the deposition of a nitride layer 201 covering the electrode 202B is shown. In this figure, a first etch is performed to etch parallel lines through nitride layer 201 and stop on electrode 202B to form nitride layers 201A and 201B. Depending on the embodiment, etching may be accomplished using hydrogen peroxide or ammonium hydroxide, for example. Other methods known to those skilled in the art may also be utilized. In fig. 3C, a top view of parallel lines of the formed nitride layer 201 is shown.

Fig. 4A shows a liner electrode material deposition step. The pad electrode material is disposed between parallel lines of nitride layers 201a, 201 b. A second etch is performed to etch the pad electrode material to form pad electrodes 404a, 404b, 404c. A nitride material is disposed between the pad electrodes 404a, 404b, 404c to form parallel lines of nitride layers 401a, 401b, and a Chemical Mechanical Polishing (CMP) process is performed to planarize the nitride pad electrode surface 410. Fig. 4B is a top view of the embodiment of fig. 4A, showing the resulting alternating parallel lines of nitride layers 401a, 201a, 401B, 201B and pad electrode layers 404A, 404B, 404c.

Fig. 4C shows the liner electrode recess and PCM deposition step. The pad electrodes 404a, 404b, 404c are recessed and backfilled with PCM material to form recessed pad confinement PCM layers 403a, 403b, 403c. As shown, the recess liner confinement PCM layers 403a, 403b, 403c are disposed between the nitride layers 401a, 201a, 401b, 201b, respectively. A Chemical Mechanical Polishing (CMP) process is performed to planarize the nitride recess liner confining PCM layer 420. Fig. 4D is a top view of the embodiment of fig. 4C.

Fig. 5A shows an electrodeposition step. As shown, an electrode layer 502 and nitride layer 501 hard mask is created. The electrodes may be formed of any convenient conductive material, typically a metallic material (e.g., pure metal or a metal compound, alloy or other mixture) or a doped semiconductor material, such as silicon. According to an embodiment, the electrode layer 502 may be a carbon electrode or any other electrode known to a person skilled in the art. The nitride layer 501 may be TiN, tiAlN, taN, BN, a metal oxide nitride such as TiON, a metal silicide such as PtSi, a semiconductor such as silicon or germanium (doped or undoped), a reduced metal oxide such as TiOx (x < 2 represents reduction), or a metal such as W, ni, co, or a carbon-based material.

Fig. 5B shows bottom cell double patterning. A first partial etch is performed to etch through the top electrode 202a and nitride recess liner confinement PCM 503 and stops on the electrode 202b to form parallel lines. Depending on the embodiment, the bottom cell double patterning with the first etch or partial etch may be accomplished, for example, using hydrogen peroxide or ammonium hydroxide or other methods known to those skilled in the art. Fig. 5B shows the deposition of nitride and oxide packages 501, 512 to cover stacks 1, 2, and 3, thereby protecting the exposed electrodes and nitride recess liners in each stack from confining the phase change memory cell. The encapsulation layer 510 may be composed of silicon nitride or other suitable material. Stacks 1, 2, and 3 may be further encapsulated with an oxide layer 512 comprising a substrate.

Fig. 6A shows a second etch to etch through the remaining electrodes 202b, 202c, bi-directional thermal switch 205 and conductor 207 to form parallel bottom cell bit lines. An encapsulation layer 610 is deposited covering stacks 1, 2 and 3 to protect the now exposed bi-directional thermal switch 205 in each stack. After encapsulation, gap filler 601 covers stacks 1, 2, and 3. The gap filler may be obtained by atomic layer deposition of oxide, spin On Dielectric (SOD) or flowable Chemical Vapor Deposition (CVD) oxide. Examples of gap fill materials include, but are not limited to, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), and cobalt-based compounds, and any combination thereof. Fig. 6B shows an oxide/nitride Chemical Mechanical Polishing (CMP) process for stacks 1, 2 and 3. The CMP process is stopped on the carbon electrode 202a as shown in fig. 6B.

Fig. 7A shows a word line metal and nitride metal deposition step. As shown in the X-direction, a metal layer 701 and a nitride layer 702 are produced. The metal layer 701 may be tungsten or any other conductive metal. The nitride layer 702 may be TiN, tiAlN, taN, BN, a metal oxide nitride such as TiON, a metal silicide such as PtSi, a semiconductor such as silicon or germanium (doped or undoped), a reduced metal oxide such as TiOx (x < 2 representing reduction), or a metal such as W, ni, co, or a carbon-based material. Typically, deposition may be accomplished by Chemical Vapor Deposition (CVD). In this process, a vacuum deposition method is used to prepare a high quality, high performance solid material. In typical CVD, a wafer (substrate) is exposed to one or more volatile precursors, which react and/or decompose on the substrate surface to produce the desired deposit. Fig. 5B is a cross-section taken along line 7B-7B from stack 1 of fig. 7A, showing the various layers in the Y-direction depicted in fig. 7A.

Fig. 8A and 8B illustrate bottom cell word line double patterning to form parallel bottom cell write lines perpendicular to the bit lines that are in contact with bottom cell top carbon electrode 202 a. As shown in fig. 8B, which is a cross-sectional view of fig. 8A in the direction 8B-8B, a first partial etch is performed to etch through the top electrode 202a, the recessed liner limiting PCM 203 and the liner electrode 204, and stops on the electrode 202B to form parallel lines. Depending on the embodiment, the etching may be accomplished using hydrogen peroxide or ammonium hydroxide, for example, or by other methods known to those skilled in the art.

Fig. 9A shows the deposition of nitride and oxide packages 501, 512 to cover stacks 1, 2, and 3, thereby protecting the exposed electrodes and nitride recess liners in each stack from confining the phase change memory cell. Encapsulation layer 910 may be comprised of silicon nitride or other suitable material. Stacks 1, 2, and 3 may be further encapsulated with an oxide layer 912 comprising a substrate. A bottom cell write line etch is then performed using a second etch to etch through the remaining electrodes 202b, 202c, bi-directional thermal switch 205 and conductor 301 to form a parallel bottom cell word line. Encapsulation layer 914 is deposited over stacks 1, 2, and 3 to protect the now exposed bi-directional thermal switch 205 in each stack. After encapsulation, gap filler 601 covers stacks 801, 802, and 803. The gap filler may be obtained by atomic layer deposition of oxide, spin On Dielectric (SOD) or flowable Chemical Vapor Deposition (CVD) oxide.

Fig. 7A and 7B illustrate the reduced critical dimensions of phase change memory cell 303 in both its X-direction and Y-direction. A dry or wet etched recessed PCM cell is shown completed for reducing its critical dimension in the other direction (i.e., the Y direction as shown in fig. 7B). Also, ammonium hydroxide or hydrogen peroxide may be used in the etching process. In these figures, PCM 303 has a reduced size in both the X and Y directions and is smaller relative to electrode 202 and/or selector (ovonic threshold switch) 205.

Fig. 8A and 8B illustrate the deposition of nitride and oxide packages 304, 401 followed by gap fill 402. Oxide Chemical Mechanical Polishing (CMP) is completed and stopped in conductor 501. Also according to embodiments, conductor 501 may be tungsten (W) or other conductive material.

Fig. 9 illustrates a second stack deposited and patterned for a memory cell having a recess and a reduced size new cell structure as described herein. A top portion 901 and a bottom portion 903 are shown, both having a reduced phase change memory cell 303 relative to electrode 202 and selector 205. Also, according to an embodiment, the reduced critical dimension of PCM 303 may be in the X-direction only, or in the Y-direction only, or in both the X-direction and the Y-direction. The top and bottom cell write lines separating the two stacks in fig. 9B illustrate the oxide/nitride Chemical Mechanical Polishing (CMP) process for stacks 801, 802, and 803. The CMP process is stopped on the conductor 701 as shown in fig. 9B.

Fig. 10 illustrates a second stack deposited and patterned for a memory cell having a new recessed liner confinement cell structure described herein with recesses and reduced dimensions. A top portion 1001 and a bottom portion 1003 are shown, both having a reduced phase change memory cell 203 relative to electrode 202a and selector 205. The top cell and bottom cell write lines separate the two stacks in fig. 9, as represented by portion 1002.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the above-described features may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation. As an example, the foregoing operations need not be performed in the exact order described above. Rather, the various steps may be processed in a different order, such as upside down or simultaneously. Unless otherwise indicated, steps may also be omitted. In addition, the provision of examples described herein and clauses expressed as "such as," "including," and the like should not be construed as limiting the claimed subject matter to a particular example; rather, these examples are intended to illustrate only one of many possible embodiments. Furthermore, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims (13)

1. A three-dimensional memory having a recessed liner confinement cell structure, comprising:

a word line and a bit line perpendicular to each other and coupled to at least one memory cell stack;

a selector, a modified recessed liner, a modified phase change memory rlcPCM cell, a liner electrode, a first electrode, a second electrode, and a third electrode contained within the memory cell stack;

the rlcPCM cell, and the pad electrode are disposed between the first electrode and the second electrode, and the selector is disposed between the second electrode and the third electrode; and

the rlcPCM cell and the selector are confined between the word line and the bit line, and the rlcPCM cell is in series with the selector.

2. The three-dimensional memory of claim 1, further comprising a word line direction extending parallel to the word line and a bit line direction extending parallel to the bit line, wherein the rlpcm cell and the selector are self-aligned with respect to the word line and the bit line; and wherein the pad electrode further defines a recess, and the rlcPCM is formed in the bit line direction and in the recess of the pad electrode.

3. The three-dimensional memory of claim 1, wherein both the rlc pcm cell and the pad electrode are disposed within a nitride layer, and the pad electrode is in a bottom position relative to the rlc pcm cell.

4. The three-dimensional memory of claim 2, wherein the rlcPCM cell, the pad electrode, the selector, and the first, second, and third electrodes each have dimensions relative to the word line direction and the bit line direction; and the pad electrode and the rlcPCM are smaller in size relative to the selector to provide a reduced required current to the rlcPCM.

5. The three-dimensional memory of claim 1, wherein the selector is an ovonic threshold switch and the cell stack further comprises an encapsulation layer to protect the rlc pcm cells and the ovonic threshold switch.

6. The three-dimensional memory of claim 1, further comprising additional memory cells in an area above or below a two-dimensional area defined by the word lines.

7. The three-dimensional memory of claim 1, wherein the cell stack further comprises a nitride layer, a tungsten layer, an oxide layer, a gap fill layer, and the first and second electrodes are carbon electrodes.

8. The three-dimensional memory of claim 7, wherein the gap-fill layer comprises a material selected from the group consisting of: cobalt-based materials, gallium arsenide (GaAs), indium gallium arsenide (InGaAs), gallium nitride (GaN), aluminum nitride (AlN), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), zinc sulfide (ZnS), lead sulfide (PbS), and lead selenide (PbSe), and any combination thereof.

9. A three-dimensional X-point memory die architecture with recessed pad confinement cell structure, comprising:

a plurality of top arrays or blocks of phase change memory cells;

a plurality of bottom arrays or blocks of phase change memory cells;

a plurality of bit lines coupled to the top array and to the bottom array;

a plurality of word lines including a set of top cell word lines coupled to the top array and a set of bottom cell word lines coupled to the bottom array; and

wherein the top arrays of memory cells are each separated by a first spacing defined by adjacent phase change memory cells and selectors with recessed liner restriction cells in the top arrays, and the bottom arrays of phase change memory cells are each separated by a second spacing defined by adjacent phase change memory cells and selectors with recessed liner restriction cells in the bottom arrays.

10. The three-dimensional architecture of claim 9, wherein the top word line and the bottom word line are coupled to the three-dimensional X-point memory die architecture.

11. The three-dimensional architecture of claim 9, wherein the top and bottom arrays of recessed pad-restraining elements have a reduced size compared to selectors disposed within each respective array.

12. The three-dimensional architecture of claim 9, wherein the selector is a bi-directional threshold switch.

13. A method of forming a three-dimensional memory having a recessed liner confinement cell structure, comprising:

forming a cross point memory array having a plurality of parallel bit lines and a plurality of vertical word lines;

self-aligned formation of a recessed pad in series with an Ovonic Threshold Switch (OTS) select device at the intersection of the word line and the bit line limits phase change memory rlcPCM cells; and is also provided with

Wherein the rlcPCM cell is formed by: the pad electrode is recessed to form a recess, and phase change memory cell material is deposited in the recess and planarized by chemical mechanical polishing.