CN112368771B

CN112368771B - Method for reducing thermal cross-talk in 3D cross-point memory arrays using laminated gap fill

Info

Publication number: CN112368771B
Application number: CN202080002919.8A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2023-06-23
Anticipated expiration: 2040-10-10
Also published as: CN112368771A; WO2022073221A1

Abstract

Systems, methods, and apparatus are described that are capable of reducing the amount of thermal crosstalk between cells in a three-dimensional array of memory cells through the use of laminates, which in turn allow for smaller scale fabrication of the memory cells.

Description

Method for reducing thermal cross-talk in 3D cross-point memory arrays using laminated gap fill

Technical Field

The present disclosure relates generally to three-dimensional electronic memories. More particularly, the present disclosure relates to the use of laminates in the geometry of a three-dimensional memory array to increase certain characteristics or attributes of the memory array or to reduce undesirable characteristics in the memory array.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, planar processing and fabrication techniques become challenging and expensive. Thus, the memory density of the planar memory cell approaches the upper limit. A three-dimensional (3D) memory architecture may address density limitations of planar memory cells.

Disclosure of Invention

In creating the techniques of the present invention, it has been recognized that while three-dimensional (3D or 3-D) memory architectures can address the density limitations of planar memory cells, 3D configuration presents new technical challenges. Other technical problems may arise as the pursuit of the desired features of 3D memory architecture (e.g., increased density of 3D cells, or reduced manufacturing size of cells).

One example of such a problem is thermal cross-talk between cells. Thermal cross-talk may occur when heat generated from one point or cell within a 3D cell array is transferred to an adjacent cell at another point or cell. During operation of the 3D memory architecture, heat generated from one cell can disrupt the normal or desired operation of the cell. The problem due to thermal cross-talk between cells becomes more and more pronounced as the size of the cells decreases. Due to the smaller intra-cell distance, smaller spacing or scaling when creating a 3D memory architecture increases the amount or speed of heat transfer between one cell and another. The ability to scale to smaller sizes while still having a functional 3D memory array is compromised due to thermal cross-talk.

Thus, there is a need for methods, systems, and apparatus that overcome the conventional methods of creating 3D memory arrays and allow for scaling of 3D memory arrays while making them operational despite thermal crosstalk.

In one embodiment of the present technology, a three-dimensional memory includes: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer three-dimensionally and at least partially encapsulating the first memory cell, the second memory cell, and the electrode such that the first memory cell and the second memory cell are exposed on at least one surface. In some exemplary embodiments, the electrodes and/or memory cells may be arranged vertically, while in other exemplary embodiments, the electrodes and/or memory cells may be arranged horizontally. In some examples, a combination of orientations is possible.

Other embodiments of the present technology may include, for example, any combination of the following: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer three-dimensionally and at least partially encapsulating the first memory cell, the second memory cell, and the electrode; configuring the first and second memory cells to be exposed on at least one surface; depositing a first layer using a chemical vapor deposition method; depositing a first layer using an atomic deposition method; a second layer at least partially and three-dimensionally surrounding the first layer; a plurality of additional layers, wherein the plurality of layers fully occupy the intra-cell space; constructing the first layer, the second layer, or the additional layer from a dielectric material; selecting the dielectric material from NiTi (NIT), tungsten (W), ovonic Threshold Switch (OTS), phase Change Memory (PCM), or a_c; constructing the first layer and the second layer from different materials; the first layer and the second layer are composed of a material selected to maximize the heat reflection value.

For example, other embodiments of the invention include methods that may include, for example, any combination of the following: providing a first storage unit; providing a second storage unit; providing an electrode electrically connecting the first memory cell and the second memory cell; creating a first layer that encapsulates the first memory cell, the second memory cell, and the electrode in three dimensions; exposing the first and second memory cells on at least one surface; creating a second layer that at least partially and three-dimensionally surrounds the first layer; creating a plurality of layers such that the plurality of layers partially occupy the intra-cell space; creating a plurality of layers such that the plurality of layers fully occupy the intra-cell space; removing material in the intra-cell space beyond the top of the first storage unit or the second storage unit; an electrode is added substantially over the surface exposed by removing material beyond the top of the first or second memory cell.

Drawings

The foregoing aspects, features and advantages of the present disclosure will be further understood when considered with reference to the following description of exemplary embodiments and the accompanying drawings in which like reference numerals denote like elements. In describing the exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be used for the sake of clarity. However, aspects of the present disclosure are not intended to be limited to the specific terminology used.

Fig. 1 is an isometric view of a portion of a prior art three-dimensional cross-point memory.

Fig. 2 is a plan view of a portion of a prior art three-dimensional cross-point memory.

Fig. 3A, 3B, and 3C are cross-sectional views of portions of a three-dimensional cross-point memory and an energy grid created by the memory of an embodiment.

Fig. 4 is a graph showing a relationship between a disturb current and a resistance of a memory cell.

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sections of a three-dimensional cross-point memory according to an embodiment of the present invention.

Fig. 6 depicts a method according to an exemplary embodiment of the present disclosure.

Detailed Description

Heat transfer occurs through three main physical phenomena of convection, conduction and radiation. Radiation is a method of energy transfer that does not rely on any contact between the heat source and the heated object. Conduction, on the other hand, is the transfer of heat between substances in direct contact with each other. The conductivity between objects in contact with each other depends on the specific physical characteristics of these objects. For example, conduction through an object depends on the thermal resistance of the material from which the object is made. In an electrical circuit, heat transfer may occur through any of these phenomena.

Conduction can also be conceptualized as occurring through phonons (phonons). Phonons are collective excitations in a periodic elastic arrangement of matter. Phonons are quasi-particles that can represent the vibrational characteristics of a material or various vibrational modes of an elastic material, and also describe the interaction of interacting particles of an elastic material. The heat in the dielectric material and the semiconductor is transferred mainly by phonons.

When the object is composed of more than one material, the overall thermal resistance of the material may be considered to be composed of the thermal resistances of the constituent materials. However, there is more than one material within the system or object that creates a thermal boundary resistance between these materials. Phonons may also undergo scattering in the material by interaction with defects, other phonons, grain boundaries, different isotopes in the material, and various other physical reasons. A temperature discontinuity may occur in the region where two materials interface when heat passes through the interface between the two materials (i.e., when phonons move from one material to the other). Thermal resistance boundaries are also known as interfacial thermal resistance or Kapitza resistance, which is a measure of the resistance of an interface to heat flow. Thermal resistance boundaries are also defined as the ratio of the temperature discontinuity at an interface to the heat flux flowing through the interface and are caused by strong phonon reflection as phonons attempt to pass through the interface of one material with another. When phonons move from one material to another (such as, for example, from material a to material B), a portion of the phonon energy is reflected back to material a (i.e., reflected) and some of the energy is conducted to material B (i.e., conducted).

By selecting the materials that make up the object, or by creating additional boundaries through which phonons must pass, a higher thermal resistance boundary can be designed. The higher thermal resistance boundary may slow the rate at which heat is transferred by conduction. In addition, by having several materials in the proper configuration, many boundaries can be created through which phonons must pass.

The technology of the present invention relates to solving the problems associated with heat transfer in three-dimensional memories. A general example of a three-dimensional (3D) memory is shown in fig. 1. Specifically, FIG. 1 is an isometric view of a portion of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first-layer memory cells 5 and the second-layer memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. Above the first-layer memory cells 5 in the depth (Z) direction are a plurality of first bit lines 20 extending in the vertical (Y) direction, and below the second-layer memory cells 10 are a plurality of second bit lines 25 extending in the Y direction.

As also shown in fig. 1, the sequential structure of the bit lines, memory cells, word lines, memory cells may be repeated in the Z-direction to create a stacked configuration. In the example of fig. 1, the first layer stack may include the first layer memory cells 5, the bit lines 20, and the word lines 15, and the second layer stack may include the second layer memory cells 10, the bit lines 25, and the word lines 15. Thus, although the first tier memory cells 5 and the second tier memory cells 10 each have their respective set of

bit lines

20 and 25, the first tier memory cells 5 and the second tier memory cells 10 may share the same set of word lines 15. Although the example of fig. 1 shows a 4-layer stacked configuration, in other examples, the stacked configuration may include any number of memory cell layers and other elements. In any event, the individual memory cells in the structure can be accessed by selectively activating the word line and bit line corresponding to the cell.

To selectively activate the word lines and bit lines, the memory includes a word line decoder and a bit line decoder (not shown). A word line decoder is coupled to the word lines through word line contacts (not shown) and is used to decode word line addresses so that a particular word line is activated when addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts (not shown) and is used to decode the bit line addresses so that a particular bit line is activated when addressed. Thus, the stacked configuration of the memory may also include bit line contacts and decoders, and word line contacts and decoders for selectively activating the bit lines and word lines in the stack. For example, the stacked configuration may be arranged as an array of elements, where each array includes a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders. The positioning of the word line decoders and contacts, and the bit line decoders and contacts, is shown and further discussed with reference to fig. 2.

Fig. 2 is a plan view of a portion of a three-dimensional cross-point memory of a prior configuration. The figure depicts the portion as viewed in the Z (depth) direction. In this example, the stacked configuration is a 2-layer stack. The stacked configuration includes multiple arrays of memory cells, including two

top cell arrays

60 and 61 and two

bottom cell arrays

65 and 66. Although individual memory cells are not shown in fig. 2, they are shown by fig. 1, for example, in a top array, the memory cells may be arranged as the first tier memory cells 5 shown in fig. 1, and in a bottom array, the memory cells may be arranged as the second tier memory cells 10 shown in fig. 1.

The portion includes word lines and bit lines corresponding to the top and bottom cells, word line and bit line contacts, and word line and bit line decoders. As shown, a plurality of word lines (e.g., word line 30) extend in the X (horizontal) direction and correspond to both the top and bottom cells. The portion also includes a plurality of top cell bit lines (e.g., bit lines 35) extending in the Y (vertical) direction and corresponding to the top cell array 60 of memory cells, and a plurality of bottom cell bit lines (e.g., bit lines 40) extending in the vertical direction and corresponding to the bottom cell array 65 of memory cells. The word lines, top cell bit lines, and bottom cell bit lines are typically formed of a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. In addition, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

The word lines in fig. 2 are horizontally aligned for a given cell array. For example, as shown, the word lines of the

cell arrays

60, 61, 65, and 66 are all horizontally aligned with each other in the X direction. Each of these word lines is shown extending across the entire width of the respective cell array. The top cell bit line of a given top cell array or the bottom cell bit line of a given bottom cell array is vertically aligned. For example, top cell bit line 35 is vertically aligned in the Y-direction and bottom cell bit line 40 is vertically aligned in the Y-direction. The top cell bit lines of the top cell array and the bottom cell bit lines of the overlapping bottom cell array (e.g., top cell bit line 35 and bottom cell bit line 40) are also horizontally aligned with each other, although they are shown slightly offset in fig. 2 to clearly show the two layers. Each of these bit lines is shown as extending across the entire length of the respective cell array.

The memory portion of fig. 2 includes a word line contact region 45, a top cell bit line contact region 50, and a bottom cell bit line contact region 55. Word line contact region 45 is elongated in a vertical direction, while top cell bit line contact region 50 and bottom cell contact region 55 are elongated in a horizontal direction. The word line contact region 45 includes a plurality of word line contacts (e.g., contact 45 a), which are shown as points surrounded by the word line contact region 45. The top cell bit line contact region 50 includes a plurality of word line contacts (e.g., contacts 50 a), which are shown as points surrounded by the top cell bit line contact region 50. The bottom cell bit line contact region 55 includes a plurality of bottom cell bit line contacts (e.g., contacts 55 a), which are shown as points surrounded by the bottom cell bit line contact region 55.

The word line contacts and the bit line contacts are connected to the middle portions of the respective word lines and bit lines. Thus, as shown, word line contact region 45 is located in the horizontal middle of word line 40, bottom cell bit line contact region 55 is located in the vertical middle of bottom cell bit line 40, and top cell bit line contact region 50 is located in the vertical middle of top cell bit line 35. Since the word lines of a given cell array are aligned horizontally, the word line contacts of the given cell array are also substantially aligned in the horizontal direction. Similarly, because the bit lines of a given cell array are vertically aligned, the bit line contacts of a given cell array are also substantially aligned in the vertical direction.

The word line contact region 45 also includes a plurality of word line decoders (not shown). The word line decoder generally conforms to the word line contact area and extends generally in a vertical direction. The word line decoder is coupled to the word line through a word line contact. The top cell bit line contact area 50 also includes a plurality of top cell bit line decoders (not shown). The top cell bit line decoder generally conforms to the top cell bit line contact area 50 and extends generally in a horizontal direction. The top cell bit line decoder is coupled to the top cell bit line through a top cell bit line contact. The bottom cell bit line contact area 55 also includes a plurality of bottom cell bit line decoders (not shown). The bottom cell bit line decoder generally conforms to the bottom cell bit line contact area 55 and extends generally in a horizontal direction. The bottom cell bit line decoder is coupled to the bottom cell bit line through a bottom cell bit line contact.

As can be seen from fig. 1, the prior art memory does not contain any material for preventing heat transfer between one cell and the next. Methods and systems are described below that can prevent heat transfer between memory cells without interfering with memory operation.

Referring to fig. 3A, 3B, and 3C, thermal crosstalk can be observed between active or disturbing cells through which current is transferred and inactive or disturbed cells. Although fig. 3A, 3B, and 3C are shown in two dimensions, they represent physical phenomena occurring in three dimensions.

Fig. 3A shows an active cell 305 (also referred to as a jammer cell 305) and an inactive or victim cell 310, wherein the distance between the 3D cells is approximately 90 nanometers. During normal operation of the memory cell, the disrupting unit 305 generates heat when current passes through the disrupting unit 305. The heat generated by the disrupting unit 305 is represented by field 315. The field 315 may represent a gradient or distribution of temperature. That is, the field 315 may represent a particular temperature at a particular physical space by mapping the space to a color that represents the temperature of the space. Alternatively, the field 315 may also be depicted by the proximity or density of lines to represent higher or lower temperatures at a particular region. Although field 315 is viewed in two dimensions in fig. 3A, field 315 may be three-dimensional and extend outward from within disturbing cell 305 to the space surrounding cell 305. As can be seen in fig. 3A, heat generated from the scrambling of scrambling unit 305 is conducted across intra-cell gap 320 to disturbed unit 310.

Fig. 3B is 45 nm anisotropic visualization of heat transfer and temperature gradients generated by the disrupting elements. Fig. 3B shows the 3D cell structure scaled to a smaller pitch than fig. 3A. The intra-cell distance between the scrambling unit and the victim unit is reduced compared to fig. 3A, and in turn, both the heat transferred to the victim unit and the temperature of the victim unit are increased. Thus, the reduced cell pitch and the increase in thermal effects on the victim cell (e.g., the jammer cell 330) affect the operational properties of the victim cell 340. The field 350 may represent a particular temperature at a particular physical space if the particular physical space is mapped to a color gradient. As shown in fig. 3B, scrambling unit 330 affects victim unit 340 differently at different locations of victim unit 340. In fig. 3B, the victim unit 340 has a higher heat at one end of the unit than the other. Such unequal distribution of temperature may affect the normal operation of the disturbed cell 340. For example, the expected resistance of the victim unit 340 may not be equal throughout the victim unit due to the heat.

Fig. 3C is a 45 nm isotropic visualization of heat transfer and temperature gradient generated by the disrupting elements. An isotropic view is a view that treats all directions equally. Isotropic heat transfer occurs when heat is transferred in all directions at the same rate.

As can be seen from fig. 3A-3C, as the intra-cell distance decreases, more heat is transferred between cells. Further complicating this problem in three-dimensional memories, because the memory is stacked one on top of the other, the surface area and space from which heat is dissipated is reduced compared to conventional generally two-dimensional memories, in which heat can be dissipated to the surrounding environment at a faster rate. For example, compared to a planar memory configuration, heat will not be quickly and efficiently removed from the intermediate memory layer of the three-dimensional memory. In addition, heat moving from one cell in the three-dimensional memory will propagate in all directions, heating all nearby cells.

Fig. 4 is a visual representation between the amount of current passing through a scrambling unit (e.g., scrambling unit 405) and the resistance of a victim unit (e.g., victim unit 410). Fig. 4 also shows a first word line 415, a second word line 420, a first bit line 425, and a second bit line 430. The current may pass through the word line and bit line, such as reset pulse 435. As can be seen from fig. 4, the disturbed cell resistance varies as a function of the current in the disturbed cell. The varying resistance of the victim unit may prevent the normal operation of the victim unit. Fig. 4 shows that the resistance of the victim cell can change by an order of magnitude of 10 based on the increased current within the victim cell. The change in resistance of the victim unit (e.g., victim unit 410) occurs at least in part due to thermal energy generated by the jammer unit (e.g., jammer unit 405).

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sectional views of a three-dimensional cross-point memory according to an embodiment of the present invention. Fig. 5A illustrates a memory cell formed by deposition or stacking of materials. As can be seen in fig. 5A,

cells

510 and 520 are formed of similar materials and thus form parallel lines within the cell stack when viewed in two dimensions. Although not shown in fig. 5A, other components (e.g., those described above or known in the art) or in combination with the cells may be included in various configurations to implement an operable 3D cross-point memory. The

cells

510 and 520 may be created or stacked on an electrode (e.g., electrode 501). The

units

510 and 520 may be made of various materials or elements, such as W, a-C, ovonic Threshold Switches (OTS) or PCM. For example, the

units

510 and 520 may be composed of several layers, such as

layers

502, 503, 504, 505, and 506, for example, which in turn may be made of elements such as W, a-C, ovonic Threshold Switches (OTS), or PCM.

Fig. 5B illustrates forming a first thin NiTi (NIT) encapsulation layer around the memory cell stack shown in fig. 5A. NIT is a commercially available alloy such as, for example, NIT135. Any suitable material may be used to form the first layer 530. The first layer 530 may also be made of any suitable dielectric material. The dielectric material is selected to ensure that current in the memory (e.g., cells 510 and 520) is not carried to undesired paths outside those cells. Forming the first layer around the memory stack may be achieved by a conformal coating technique. Conformal coating techniques provide technical advantages such as uniformity of the material being coated. However, the first layer may be formed around the memory stack using any suitable technique. In an exemplary embodiment, a technique such as Atomic Layer Deposition (ALD) may be used. Atomic layer deposition is a thin film deposition technique based on the sequential use of vapor deposition processes. Other variations of ALD techniques may be used to deposit the first thin layer.

Fig. 5C illustrates forming a second layer 540 around the first layer 530. The second thin layer 540 may be deposited by any suitable method, such as by using atomic layer deposition. However, any suitable deposition technique may be used. Layer 540 may be created from any suitable material, such as, but not limited to, silicon dioxide.

Fig. 5D shows the formation of additional layers, such as, for example, layers 541, 542, 543, 544, 545, and 546, around the second thin layer. Each layer may be added to the previous layer in succession (e.g., layer 544 may be added after layer 543 is added). Layers 540-546 may be created from any suitable material including, but not limited to, silicon dioxide, NIT, siC, and the like. In some examples, the layers may be made of different materials, while in other examples, some layers may be made of the same material. Any suitable dielectric material may be selected to form each layer. Suitable materials will be able to resist deformation at the operating temperature and current of the cell while retaining suitable characteristics (e.g., appropriate thermal boundary resistance) to increase thermal isolation of the cell. It is also possible to select a material pair having a high thermal boundary resistance. Each layer may be configured to be selectively thick. For example, each layer may be configured to a thickness of only a few atoms. The process of adding additional layers may continue until the intra-cell space, e.g., the space between

cells

510 and 520, is filled. The material used may be, for example, a dielectric material. However, there may be a small gap between the last layers (such as, for example, layers 545 and 546).

By adding each layer (such as, for example, adding layer 545 after layer 544 has been formed), an additional interface or thermal boundary is created. Thus, at least as many thermal boundaries as the number of layers added can be created. By designing the number of layers added and selecting materials that create a larger thermal resistance boundary, each cell can be more effectively thermally isolated from surrounding cells. At smaller sizes, and as the intra-cell gap decreases, heat transfers more rapidly between cells. Thus, the additional thermal isolation allows scaling the fabrication of the memory cells to each smaller size.

In addition, by using layers (e.g., layers 541-546) to fill the intra-cell gaps with a laminate material, additional mechanical benefits may be realized. For example, the addition of laminates may be better mechanically supported during cell and 3D cross-point memory array fabrication processes.

As shown in the figures, the deposition of material is accomplished in a vertical line pattern, i.e., each layer is deposited substantially parallel to the surface preceding the layer. For example, layer 530 is substantially parallel to the surfaces of electrode 501, cell 510, and cell 520. And thereby creates layer 540 substantially parallel to layer 530. The layers may appear to form an angle of substantially 90 degrees at the tip when viewed in cross-section.

FIG. 5E shows the cell stack after additional layers are formed and portions of layers (e.g., layers 541-546) are selectively removed. In an exemplary embodiment, the presence of layers (e.g., layers 541-546) or portions that otherwise extend beyond the length of any of the cells (e.g., cell 510 or cell 520) may be removed so that each does not extend beyond the length of any of the cells. In other words, the layers (e.g., layers 541-546) are made flush with the cells (e.g., cell 510 or cell 520). Any suitable process for removing material located beyond the length of the unit (e.g., unit 510 or unit 520) may be used. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar fashion is suitable for removing excess material from the layers (e.g., layers 541-546). However, other suitable processes may be used to remove excess material, such as shallow trench isolation, for example. Therefore, the materials must be selected for both processes.

Fig. 5F shows the cell stack after the removal process described above, and another electrode is added to form the next stack of memory cells. The additional electrode 590 is added flush with the existing cells (e.g., cells 510 and 520) and the additional layers filling the space within the cells (e.g., layers 541-546). The next electrode (e.g., electrode 590) may be added parallel or perpendicular to the existing electrode (501).

The process described in fig. 5A-5F may be repeated again to create a stacked memory cell containing material layers within the cell. By stacking the electrodes, isolated memory cell pillars can be formed. By repeating the process described in fig. 5A-5F, each memory cell formed is thermally isolated from other memory cells within the stack of memory cells.

One advantage of the memory cells created as described above is reduced thermal cross-talk between cells. By increasing the thermal boundary resistance and creating multiple layers, thermal cross-talk is reduced. Furthermore, by filling the gaps, additional mechanical support is provided to the overall three-dimensional memory structure, which is beneficial for reducing the size of the fabrication to smaller pitches and for subsequent processing of the memory.

Fig. 6 depicts a method (method 600) according to an exemplary embodiment of the present disclosure. The method starts in step 610. In step 610, a memory cell may be formed by stacked deposition on a substrate. The substrate may be a conductive material, such as an electrode. The memory cells may be formed by any suitable method, such as, for example, by atomic layer deposition. The memory cell may be formed with an intra-cell gap. In step 620, a first layer may be formed on the memory cell. The first layer may be formed in three dimensions to surround and encapsulate the memory cells. The first layer may be formed from any suitable material, such as, for example, a dielectric material. In step 630, a second layer is deposited atop the first layer and encapsulates the first layer. The second layer may be composed of any suitable material or combination of materials and deposited by any suitable method. In step 640, an additional layer may be deposited to encapsulate the second layer. Additional layers may be added as needed to fill in the intra-cell gaps between the memory cells. Each additional layer encapsulates a previous layer. The addition of each layer may occur in three dimensions. In step 650, the material located beyond the intra-cell gap and atop the cell may be removed by any suitable technique. The material may be removed in a manner that allows a substantially flat and continuous surface to be created between the cells and the layers added in steps 610-650. In step 660, a substrate may be added at the location where the material is removed. In step 670, steps 610-660 may be repeated as needed. The method ends at step 680.

Most of the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. For example, the foregoing operations need not be performed in the exact order described above. Rather, the various steps may be processed in a different order, such as in reverse order or simultaneously. Unless otherwise stated, steps may also be omitted. In addition, the provision of examples described herein and phrases such as "such as," "including," and the like should not be construed to limit the subject matter of the claims to particular examples; rather, these examples are intended to illustrate only one embodiment of many possible embodiments. Furthermore, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional cross-point memory comprising:

a first storage unit;

a second storage unit;

an electrode electrically connecting the first memory cell and the second memory cell;

an intra-cell space between the first storage unit and the second storage unit; and

a first layer and a second layer, the first layer three-dimensionally, at least partially encapsulating the first memory cell, the second memory cell, and the electrode, and the second layer at least partially and three-dimensionally surrounding the first layer,

a plurality of additional layers at least partially and three-dimensionally surrounding the second layer, wherein the plurality of additional layers occupy the entire intra-cell space,

wherein the first layer, the second layer and the plurality of additional layers are deposited using an atomic deposition process,

wherein the first layer, the second layer, and the plurality of additional layers create a plurality of material internal interfaces, an

Wherein the first and second memory cells are configured to be exposed on at least one surface.

2. The three-dimensional cross-point memory of claim 1 wherein the first layer, the second layer, and the plurality of additional layers are comprised of a dielectric material.

3. The three-dimensional cross-point memory of claim 2 wherein the first and second memory cells are selected from NiTi, a C, PCM, OTS, or W.

4. The three-dimensional cross-point memory of claim 1 wherein the first layer and the second layer are composed of different materials.

5. A three-dimensional cross-point memory comprising:

a top cell array of memory cells;

a bottom cell array of memory cells;

at least one electrode electrically connected to at least one of the top array of memory cells or the bottom array of memory cells; and

an in-memory space between the memory cells, wherein the in-memory space is filled with a plurality of layers that three-dimensionally, at least partially encapsulate the memory cells and the at least one electrode, and the plurality of layers create a plurality of material internal interfaces,

wherein the memory space is completely filled by the plurality of layers,

wherein the plurality of layers comprises a first layer, a second layer and a plurality of additional layers, the second layer at least partially and three-dimensionally surrounding the first layer, and the plurality of additional layers at least partially and three-dimensionally surrounding the second layer, and

wherein the first layer, the second layer, and the plurality of additional layers are deposited using an atomic deposition process.

6. A method of forming a three-dimensional cross-point memory, comprising:

providing a first storage unit;

providing a second storage unit;

providing an electrode electrically connecting the first memory cell and the second memory cell;

creating a first layer and a second layer, the first layer three-dimensionally encapsulating the first memory cell, the second memory cell, and the electrode, and the second layer at least partially and three-dimensionally surrounding the first layer;

creating a plurality of additional layers at least partially and three-dimensionally surrounding the second layer, wherein the plurality of additional layers occupy the entire intra-cell space; and

exposing the first memory cell and the second memory cell on at least one surface,

wherein the first layer, the second layer, and the plurality of additional layers are deposited using an atomic deposition process, and

wherein the first layer, the second layer, and the plurality of additional layers create a plurality of material internal interfaces.

7. The method of claim 6, further comprising the step of:

and removing the material between the intra-cell spaces beyond the top of the first storage unit or the second storage unit.

8. The method of claim 7, further comprising the step of:

an electrode is added substantially over the surface exposed by removing material beyond the top of the first or second memory cell.