WO2024098366A1

WO2024098366A1 - A multi-stack three-dimensional phase-change memory and methods for making the same

Info

Publication number: WO2024098366A1
Application number: PCT/CN2022/131316
Authority: WO
Inventors: Jun Liu
Original assignee: Yangtze Advanced Memory Industrial Innovation Center Co., Ltd
Priority date: 2022-11-11
Filing date: 2022-11-11
Publication date: 2024-05-16

Abstract

A multi-stack three-dimensional (3D) phase-change memory (PCM) array having multiple levels of word lines and bit lines, a word line decoder, and a bit line decoder on a first die, another decoder on a second die, with the first die and the second die hybrid-bonded face-to-face. In some implementations, bit lines are coupled from their undersides to their first-die bit line decoders, while first word lines are coupled from their undersides to first-die word line decoders, and second word lines are coupled from their upper sides to second-die word line decoders. In other implementations, first bit lines are coupled from their undersides to first-die bit line decoders, and first word lines are coupled from their undersides to first-die word line decoders, while second bit lines are coupled from their upper sides to second-die bit line decoders, and second word lines are coupled from their upper sides to second-die word line decoders.

Description

A MULTI-STACK THREE-DIMENSIONAL PHASE-CHANGE MEMORY AND METHODS FOR MAKING THE SAME

BACKGROUND

The present disclosure relates to three-dimensional (3D) phase-change memory (PCM) devices and fabrication methods thereof.

Planar memory cells are scaled to smaller sizes by improving process technology, circuit design, programming algorithms, and fabrication process. However, as feature sizes of the memory cells approach a lower limit, planar process and fabrication techniques become challenging and costly. As a result, memory density for planar memory cells approaches an upper limit.

A 3D memory architecture can address the density limitation of planar memory cells. 3D memory architectures include a memory array and peripheral devices for controlling signals to and from the memory array. For example, phase-change memory (PCM) can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. Arrays of PCM cells can be vertically stacked in 3D to form a 3D PCM.

SUMMARY

A 3D PCM architecture for increased bit density is disclosed herein. Further, a 3D PCM array with eight vertically stacked levels of PCM cells, and having multiple levels of word lines and multiple levels of bit lines within the 3D PCM array, at least one word line decoder, and at least one bit line decoder disposed on a first die, at least one other decoder disposed on a second die, and the first die and the second die hybrid-bonded to each other in a face-to-face arrangement is disclosed herein.

The 3D PCM array may be arranged such that word line contacts and bit line contacts are located within a region defined by the area of the 3D PCM array.

In some implementations, the bit lines, at each of the multiple levels of bit lines, are coupled from their respective undersides to their respective bit line decoders on the first die, while a first portion of the word lines are coupled from their undersides to their respective word line decoders on the first die, and a second portion of the word lines are coupled from their upper sides to their respective word line decoders on the second die.

In other implementations, a first portion of the bit lines are coupled from their respective undersides to their respective bit line decoders on the first die, and a first portion of the word lines are coupled from their undersides to their respective word line decoders on the first die, while, a second portion of the bit lines are coupled from their respective upper sides to their respective bit line decoders on the second die and a second portion of the word lines are coupled from their upper sides to their respective word line decoders on the second die.

In one illustrative implementation in accordance with the present disclosure, a three-dimensional (3D) phase-change memory (PCM) includes a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die. The 3D PCM further includes a second die having at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die. In order to maintain a high level of bit density it is desirable to place the bit line contacts and word line contacts within an area defined by the PCM array, i.e., placing the bit line contacts and the word line contacts on their respective bit lines and word lines without having to extend the bit lines and/or word lines beyond the boundary of the PCM array. However, the arrangement of the word lines, bit lines, and PCM cell stacks in an eight-stack 3D PCM array (described in more detail below) introduces routing challenges in terms of reaching all the bit lines and word lines with connections to their respective decoders. Still referring to this one illustrative implementation, the first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines. Additionally, each of the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines have an upper side and an underside, the first bit lines, second bit lines, third bit lines, fourth bit lines, and fifth bit lines, are coupled, by one or more bit line contacts, between their respective undersides and their associated bit line decoder on the first die, the first word lines and the second word lines are coupled, by one or more word line contacts, between their respective undersides and their associated word line decoder on the first die, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die; and the first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other.

In another illustrative implementation in accordance with the present disclosure, a 3D PCM, includes a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die, and a second die having at least one bit line decoder, at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die. In this illustrative implementation, the first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other. In this illustrative implementation, the first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack is disposed between the plurality of fourth word lines and a plurality of fifth bit lines, and the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines each have an upper side and an underside. And, in this illustrative implementation, the first bit lines, second bit lines, and third bit lines, are coupled between their respective undersides and their associated bit line decoder on the first die, by at least bit line contacts, the fourth bit lines and the fifth bit lines are coupled between their respective upper sides and their associated bit line decoder on the second die, by at least bit line contacts, and the first word lines and the second word lines are coupled between their respective undersides and their associated word line decoder on the first die, by at least word line contacts, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die, by at least word line contacts.

In still another illustrative implementation in accordance with the present disclosure, a 3D PCM, includes a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die. This illustrative implementation further includes a second die having at least one bit line decoder, at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die. The first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines. In this illustrative implementation, the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines each have an upper side and an underside, the first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other. Further, the first bit lines, second bit lines, and third bit lines, are coupled between their respective undersides and their associated bit line decoder on the first die, by at least bit line contacts, the fourth bit lines and the fifth bit lines are coupled between their respective upper sides and their associated bit line decoder on the second die, by at least bit line contacts, and the first word lines and the second word lines are coupled between their respective undersides and their associated word line decoder on the first die, by at least bit line contacts, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die, by at least word line contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated herein and form a part of the specification, illustrate implementations of the present disclosure and, together with the description, further serve to explain the principles of the present disclosure and to enable a person skilled in the pertinent art to make and use the present disclosure.

FIG. 1 is a perspective view of an illustrative 3D PCM device having a cross-point arrangement.

FIG. 2A is a block diagram of an illustrative 3D PCM device having a cross-point arrangement.

FIG. 2B is a plan view of the illustrative 3D PCM device having a cross-point arrangement in FIG. 2A.

FIG. 2C is a perspective view of the illustrative 3D PCM device having a cross-point arrangement in FIG. 2A.

FIG. 3A is a block diagram of an illustrative 3D PCM memory device, in accordance with the present disclosure.

FIG. 3B is a plan view of the illustrative 3D PCM memory device in FIG. 3A, according to some implementations of the present disclosure.

FIG. 3C is a perspective view of the illustrative 3D PCM memory device in FIG. 3A, in accordance with the present disclosure.

FIG. 4A is a perspective view of another illustrative 3D PCM memory device, in accordance with the present disclosure.

FIG. 4B is a perspective view of still another illustrative 3D PCM memory device, in accordance with the present disclosure.

FIGs. 5A–5L show an illustrative fabrication process for forming a 3D PCM memory device, in accordance with the present disclosure.

FIG. 6 is a flowchart of an illustrative method for forming a 3D PCM memory device, in accordance with the present disclosure.

FIG. 7 is a schematic stick-figure illustration of a previous 3D PCM array architecture having bit line decoder circuitry and word line decoder circuitry on the same die as the 3D PCM array, and thereby occupying an area that could otherwise be used for memory cells.

FIG. 8A is a block diagram illustrating a first die having bit line decoder circuitry, an array of PCM cells, and a hybrid bonding layer; and a second die having word line decoder circuitry and another hybrid bonding layer, oriented in a face-to-face arrangement prior to hybrid bonding.

FIG. 8B is a block diagram illustrating the first die and second die of FIG. 8A, after hybrid bonding to each other.

FIG. 9 is a cross-sectional view of an example first die, including bit line decoder circuitry, a 3D PCM cell array disposed above the bit line decoder circuitry, and a first hybrid bonding layer disposed on a topside thereof.

FIG. 10A is a cross-sectional view of an example second die in a partially fabricated state, including word line decoder circuitry and array circuitry.

FIG. 10B is a cross-sectional view of an example second die including the word line decoder circuitry, array circuitry, second bonding layer, and second bonding contacts.

FIG. 11 is a cross-sectional view of an example multi-die 3D PCM memory product having a PCM array on one die, and the word line decoder associated with the PCM array on a different die.

FIG. 12A is a cross-sectional view, in the Y-direction, of an 8-stack PCM array, in accordance with a first example implementation.

FIG. 12B is a cross-sectional view, in the X-direction, of an 8-stack PCM array, in accordance with the first example implementation.

FIG. 13A is a cross-sectional view, in the Y-direction, of an 8-stack PCM array, in accordance with a second example implementation.

FIG. 13B is a cross-sectional view, in the X-direction, of an 8-stack PCM array, in accordance with the second example implementation.

FIG. 14A is a cross-sectional view, in the Y-direction, of an 8-stack PCM array, in accordance with a third example implementation.

FIG. 14B is a cross-sectional view, in the X-direction, of an 8-stack PCM array, in accordance with the third example implementation.

The present disclosure will be described with reference to the accompanying drawings.

DETAILED DESCRIPTION

In order to achieve efficient area utilization, various implementations of the present disclosure may incorporate several architectural approaches for designing and manufacturing three-dimensional phase-change memory, or 3D PCM. First, unlike conventional 3D PCMs, which are implemented on a single die, implementations in accordance with the present disclosure use a multi-die approach. In this way, for example, a first portion of the required word line decoders, and a first portion of the required bit line decoders can be fabricated on the first die along with the 8-stack 3D PCM arrays, and a second portion of the required word line decoders and a second portion of the required bit line decoders can be fabricated on the second die. In this way, enough die area, between the first die and the second die, is provided to fit all the required word line decoders and all the required bit line decoders for a plurality of tightly packed 8-stack 3D PCM arrays.

The first die, with the 8-stack PCM arrays together with first portion of the word line decoders and the first portion of the bit line decoders, and the second die with the second portion of the word line decoders and second portion of the bit line decoder are hybrid-bonded together allowing, at least, the outputs of the second portion of the word line decoders and the second portion of the bit line decoders to reach the word lines of the 8-stack 3D PCM arrays.

Second, unlike conventional 3D PCMs, in which bit lines extend laterally outward away from the 3D PCM array in order to connect with a contact to the bit line decoder, both the bit lines and the word lines are contacted to their respective decoders within the area defined by the 3D PCM array, i.e., there is no need for the bit lines to extend laterally away from the 3D PCM array to connect with the bit line decoders.

Third, implementing an 8-stack 3D PCM results in multiple levels of overlapping bit lines and word lines, thus creating routing challenges for connecting all the word lines and bit lines to their respective bit line decoders and word line decoders without having to extend any of the bit lines or word lines outside of the area defined by the 3D PCM array. Implementations in accordance with the present disclosure provide solutions to the routing challenges of 8-stack 3D PCM arrays.

A 3D PCM architecture is disclosed herein having at least one 3D PCM array with word lines and bit lines on a first die, and a word line decoder on a second die, the first die and the second die hybrid-bonded to each other in a face-to-face arrangement. By eliminating the word line decoder circuitry from the first die and implementing the word line decoder circuitry on the second die, the layout of the 3D PCM array may be rearranged so as to increase the bit density of the array while still providing an electrical connection path between word lines in the array (on the first die) and the output terminals of the word line decoder circuitry (on the second die) . Thus, as compared to previous 3D PCM arrays that have been implemented on a single die, implementations in accordance with the present disclosure may use the die area made available by elimination of the word line decoder circuitry to increase the number of memory cells per unit area in the 3D PCM of the first die. In accordance with the present disclosure, the bit density of the 3D PCM of the first die may thereby be increased.

Various illustrative examples and implementations are presented herein to facilitate the understanding of the structures of, and methods for producing, a 3D PCM in accordance with the present disclosure. Illustrative descriptions of PCM cells, PCM arrays, and hybrid-bonding are provided, and the disclosed structures and methods are used in further describing various implementations of an 8-stack 3D PCM in accordance with the present disclosure.

This Detailed Description includes information on the structure and fabrication of example 3D phase-change memory cells, and example hybrid bonding layer structures. This Detailed Description further includes descriptions and drawings of the structure of illustrative implementations that include an 8-stack 3D PCM, a bonding layer arrangement, a face-to-face hybrid-bonding (wafer-to-wafer, or die-to-die) method, and an arrangement of bit line contacts and word line contacts, for improved area efficiency and memory cell density. In various implementations, the word line decoder circuitry is implemented on a different die than the memory array, and structures are provided on each die to interconnect the output terminals of a word line decoder circuit on one die to the word lines in the memory array on a different die.

In this way, the layout of PCM-based memory arrays, in accordance with the present disclosure, may be altered, as compared to PCM-based memory arrays where the bit line decoders and word line decoders are both present on the same die. By eliminating the need for die area dedicated to the implementation of word line decoders, memory array efficiency may be increased. And, in some implementations, because address lines that are normally input to the word line decoders are not required to be routed in the memory array portion of the die, interconnect routing congestion may be reduced. Thus, interconnect routing may be simplified.

Although specific configurations and arrangements are discussed, it should be understood that this is done for illustrative purposes only. A person skilled in the pertinent art will recognize that other configurations and arrangements can be used without departing from the spirit and scope of the present disclosure. It will be apparent to a person skilled in the pertinent art that the present disclosure can also be employed in a variety of other applications.

It is noted that references in the specification to “one implementation, ” “an implementation, ” “an example implementation, ” “some implementations, ” etc., indicate that the implementation described may include a particular feature, structure, or characteristic, but every implementation may not necessarily include the particular feature, structure, or characteristic. Moreover, such phrases do not necessarily refer to the same implementation. Further, when a particular feature, structure or characteristic is described in connection with an implementation, it would be within the knowledge of a person skilled in the pertinent art to effect such feature, structure or characteristic in connection with other implementations whether or not explicitly described.

In general, terminology may be understood at least in part from usage in context. For example, the term “one or more” as used herein, depending at least in part upon context, may be used to describe any feature, structure, or characteristic in a singular sense or may be used to describe combinations of features, structures or characteristics in a plural sense. Similarly, terms, such as “a, ” “an, ” or “the, ” again, may be understood to convey a singular usage or to convey a plural usage, depending at least in part upon context. In addition, the term “based on” may be understood as not necessarily intended to convey an exclusive set of factors and may, instead, allow for existence of additional factors not necessarily expressly described, again, depending at least in part on context.

It should be readily understood that the meaning of “on, ” “above, ” and “over” in the present disclosure should be interpreted in the broadest manner such that “on” not only means “directly on” something but also includes the meaning of “on” something with an intermediate feature or a layer therebetween, and that “above” or “over” not only means the meaning of “above” or “over” something but can also include the meaning it is “above” or “over” something with no intermediate feature or layer therebetween (i.e., directly on something) .

Further, spatially relative terms, such as “beneath, ” “below, ” “lower, ” “above, ” “upper, ” and the like, may be used herein for ease of description to describe one element or feature’s relationship to another element (s) or feature (s) as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may likewise be interpreted accordingly.

As used herein, the term “substrate” refers to a material onto which subsequent material layers are added. The substrate itself can be patterned. Materials added on top of the substrate can be patterned or can remain unpatterned. Furthermore, the substrate can include a wide array of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made from an electrically non-conductive material, such as a glass, a plastic, or a sapphire wafer.

As used herein, the term “layer” refers to a material portion including a region with a thickness. A layer can extend over the entirety of an underlying or overlying structure or may have an extent less than the extent of an underlying or overlying structure. Further, a layer can be a region of a homogeneous or inhomogeneous continuous structure that has a thickness less than the thickness of the continuous structure. For example, a layer can be located between any pair of horizontal planes between, or at, a top surface and a bottom surface of the continuous structure. A layer can extend horizontally, vertically, and/or along a tapered surface. A substrate can be a layer, can include one or more layers therein, and/or can have one or more layers thereupon, thereabove, and/or therebelow. A layer can include multiple layers. For example, an interconnect layer can include one or more conductor and contact layers (in which interconnect lines and/or via contacts are formed) and one or more dielectric layers.

As used herein, the term “contact structure” refers to a vertically-oriented, and vertically-aligned stack of contacts and/or vias, where that stack is used to provide an electrically conductive path through a plurality of layers. Further, as used herein, the term “contact structure” also refers to a vertically-oriented stack of contacts and/or vias, that also includes at least one layer of horizontally-oriented, electrically-conductive interconnect.

As used herein, the term “nominal/nominally” refers to a desired, or target, value of a characteristic or parameter for a component or a process operation, set during the design phase of a product or a process, together with a range of values above and/or below the desired value. The range of values can be due to slight variations in manufacturing processes or tolerances. As used herein, the term “about” indicates the value of a given quantity that can vary based on a particular technology node associated with the subject semiconductor device. Based on the particular technology node, the term “about” can indicate a value of a given quantity that varies within, for example, 10–30%of the value (e.g., ±10%, ±20%, or ±30%of the value) .

As used herein, the term “3D memory device” refers to a semiconductor device with memory cells that can be arranged vertically on a laterally-oriented substrate so that the number of memory cells can be scaled up in the vertical direction with respect to the substrate. As used herein, the term “vertical/vertically” means nominally perpendicular to the lateral surface of a substrate.

Description of a Stacked 3D Phase-Change Memory Array

APCM may use the difference between the resistivity of the amorphous phase and the crystalline phase of phase-change materials (e.g., chalcogenide alloys) based, at least in part, on heating and quenching of the phase-change materials electrothermally. The phase-change material in a PCM cell may be located between two electrodes, and electrical currents can be applied to switch the material (or at least a fraction of the material that blocks the current path) repeatedly between the two phases to store data. PCM cells may be vertically stacked in 3D to form a 3D PCM.

3D PCMs may include 3D cross-point memory arrays, which store data based on a change in resistance of the bulk material property (e.g., in a high-resistance state or a low-resistance state) , in conjunction with a stackable cross-point data access array to be bit-addressable. For example, FIG. 1 shows a perspective view of an illustrative 3D cross-point memory device 100. 3D PCM cross-point memory device 100 has a transistor-less, cross-point architecture that positions memory cells at the intersections of perpendicular conductors. 3D PCM cross-point memory device 100 includes a plurality of parallel lower bit lines 102 in a first common plane, and a plurality of parallel upper bit lines 104 in a second common plane located above lower bit lines 102. 3D PCM cross-point memory device 100 also includes a plurality of parallel word lines 106 in a third common plane vertically between lower bit lines 102 and upper bit lines 104. As shown in FIG. 1, each lower bit line 102 and each upper bit line 104 extend laterally along the bit line direction in the plan view (parallel to the wafer plane) , and each word line 106 extends laterally along the word line direction in the plan view. Each word line 106 is perpendicular to each lower bit line 102 and each upper bit line 104.

It is noted that x, y, and z axes are shown in FIG. 1. The x and y axes illustrate two orthogonal directions in the wafer plane. The x-direction is the word line direction, and the y-direction is the bit line direction. It is also noted that z axis is also included in FIG. 1 and further illustrates the spatial relationship of the components in 3D PCM cross-point memory device 100. The substrate (not shown) of 3D PCM cross-point memory device 100 includes two lateral surfaces extending laterally in the x-y plane: a top surface on the front side of the wafer, and a bottom surface on the backside opposite to the front side of the wafer. The z axis is perpendicular to both the x and y axes. As used herein, whether one component (e.g., a layer or a device) is “on, ” “above, ” or “below” another component (e.g., a layer or a device) of a semiconductor device (e.g., 3D PCM cross-point memory device 100) is determined relative to the substrate of the semiconductor device in the z-direction (the vertical direction perpendicular to the x-y plane) when the substrate is positioned in the lowest plane of the semiconductor device in the z-direction. The same notion for describing the spatial relationship is applied throughout the present disclosure.

As shown in FIG. 1, 3D PCM cross-point memory device 100 includes a plurality of memory cells 108 each disposed at an intersection of lower or

upper bit line

102 or 104 and respective word line 106. Each memory cell 108 includes at least a PCM element 110 and a selector 112 stacked vertically. Each memory cell 108 stores a single bit of data and can be written or read by varying the voltage applied to respective selector 112, which replaces the need for transistors. Each memory cell 108 is accessed individually by a current applied through the top and bottom conductors in contact with each memory cell 108, e.g., respective word line 106 and lower or

upper bit line

102 or 104. Memory cells 108 in 3D PCM cross-point memory device 100 are arranged in a memory array.

In existing 3D PCM cross-point memory, the bit line contacts to the upper and lower bit lines are arranged at both sides outside of the memory array in the plan view. Because the 3D PCM cross-point memory is composed of a number of memory arrays surrounded by bit line contacts, the bit line contact regions occupy a significant portion of the device area, which reduces array efficiency. For example, FIG. 2A is a block diagram of an illustrative 3D PCM cross-point memory device 200, FIG. 2B is a plan view of the illustrative 3D PCM cross-point memory device 200 in FIG. 2A, and FIG. 2C shows a perspective view of the illustrative 3D PCM cross-point memory device 200 of FIG. 2A.

As shown in FIG. 2A, 3D PCM cross-point memory device 200 includes two memory arrays A and B 202 each including an array of 3D PCM cross-point memory cells. For each memory array 202, bit line contacts are disposed in two bit line contact regions (BL CT) 204 surrounding and outside of memory array 202. That is, two bit line contact regions 204 are arranged at both sides of respective memory array 202 in the bit line direction (the y-direction) , but do not overlap memory array 202 in the plan view. As a result, dedicated bit line contact regions 204 occupy a significant portion of the device area in the bit line direction, thereby reducing array efficiency and complicating the interconnect routing scheme. 3D PCM cross-point memory device 200 also includes word line contacts in a word line contact region (WL CT) 206 at the middle of respective memory array 202 in the word line direction (the x-direction) .

Referring to FIG. 2B, each bit line 208 (either a lower bit line or an upper bit line) extends beyond and outside of memory array 202 in the bit line direction. At one or both ends of each bit line 208 outside of memory array 202, a bit line extension 210 having a critical dimension greater than that of bit line 208 is formed to place a bit line contact 212 with a relaxed critical dimension compared with bit line 208. That is, the critical dimension of bit line contact 212 is greater than that of bit line 208, which further increases the size of bit line contact region 204 and reduces the array efficiency. For example, as shown in FIG. 2C, as each bit line 208 extends laterally in either bit line direction outside of memory array 202, the critical dimension thereof is increased to form respective bit line extension 210. Bit line contacts 212 with a relaxed critical dimension, e.g., greater than that of bit line 208, are disposed below and in contact with each bit line extension 210, i.e., extending downwards in the same vertical direction.

Various implementations in accordance with the present disclosure provide an improved interconnect scheme for 3D PCM memory devices, e.g., 3D PCM cross-point memory device, and fabrication method thereof. The bit line contacts can be formed within the planar boundary of the memory array region, which eliminates the need for dedicated bit line contact regions outside of the planar boundary of the memory array region, thereby increasing memory array efficiency and simplifying the interconnect routing. In some implementations, the bit line contacts are disposed inclusively between the memory cells in the plan view, i.e., overlapping the memory array. In some implementations, the critical dimension of the bit line contacts is not greater than the critical dimension of the corresponding bit line. That is, the critical dimension of the bit line contacts is no longer relaxed compared with critical dimension of the bit lines, and the bit line contact size can be shrunk to further save contact area. To form bit line contacts with non-relaxed critical dimension, in-situ polymer deposition and etching scheme may be used.

FIG. 3A shows a block diagram of an illustrative 3D PCM memory device 300. 3D PCM memory device 300, such as a 3D PCM cross-point memory device, may include a plurality of memory arrays A and B 302 each including an array of 3D PCM cells disposed in a memory array region. For each

memory array

302, 3D PCM memory device 300 may also include bit line contacts disposed in two bit line contact regions (BL CT) 304 at two ends of the memory array region in the bit line direction, i.e., the y-direction. Different from 3D PCM cross-point memory device 200 in FIG. 2A in which the bit line contacts are outside of the memory array regions, at least some of the bit line contacts in 3D PCM memory device 300 are disposed within the memory array regions. As shown in FIG. 3A, each bit line contact region 304 completely overlaps respective memory array 302. That is, each of the bit line contacts in bit line contact region 304 is disposed within the memory array region. For each

memory array

302, 3D PCM memory device 300 may further include a word line contact region (WL CT) 306 at the middle of the memory array region in the word line direction, i.e., the x-direction. The word line contacts of 3D PCM memory device 300 may be disposed in word line contact region 306. In some implementations, each of the word line contacts is disposed within the memory array region. By arranging both word line contact region 306 and bit line contact regions 304 within the memory array region of respective memory array 302, contact area can be reduced, and the memory array efficiency can be improved.

FIG. 3B is a plan view of illustrative 3D PCM memory device 300 of FIG. 3A. As shown in FIG. 3B, 3D PCM memory device 300 may further include a plurality of bit lines 308. Each bit line 308 extends across the memory array region of memory array 302 in the bit line direction (the y-direction) . Different from bit lines 208 in 3D PCM cross-point memory device 200 that extend beyond and outside of memory array 302, bit lines 308 in 3D PCM memory device 300 are disposed within the memory array region of memory array 302. Unlike 3D PCM cross-point memory device 200 including bit line extensions 210 with relaxed critical dimension on which bit line contacts 212 are formed, 3D PCM memory device 300 includes bit line contacts 310 in contact with respective bit lines 308 directly. Each bit line contact 310 may be disposed in bit line contact region 304 within the memory array region of memory array 302. In some implementations, the critical dimension of each bit line contact 310 is not greater than the critical dimension of each bit line 308. That is, the critical dimension of bit line contacts 310 is no longer relaxed compared with bit lines 308, in accordance with the present disclosure. Thus, the bit line contact size can be shrunk to further save contact area. It is understood that although each bit line 308 is in contact with two bit line contacts 310 in two bit line contact regions 304, respectively, as shown in FIG. 3B, one or more of bit lines 308 may be in contact with only one bit line contact 310 in either one of two bit line contact regions 304 in some other implementations.

FIG. 3C is a perspective view of illustrative 3D PCM memory device 300 of FIG. 3A. As shown in FIG. 3C, 3D PCM memory device 300 may further include a plurality of word lines 312. Each word line 312 extends across the memory array region of memory array 302 in the word line direction (the x-direction) . That is, word lines 312 and bit lines 308 of 3D PCM memory device 300, such as a 3D PCM cross-point memory device, may be perpendicularly-arranged conductors in a cross-point structure.

In some implementations, 3D PCM memory device 300 includes a lower bit line 308A and an upper bit line 308B parallel to one another. For example, each of lower bit line 308A and upper bit line 308B may extend laterally across memory array 302 in the bit line direction (y-direction) . Lower bit line 308A and upper bit line 308B have the same critical dimension, e.g., the same width in the x-direction. In one example, the critical dimension of lower bit line 308A and upper bit line 308B may be about 20 nm, and the pitch of lower bit line 308A and upper bit line 308B may be about 40 nm. 3D PCM memory device 300 also includes parallel word lines 312 in the same plane between lower bit line 308A and upper bit line 308B in the z-direction. Each of word lines 312 is perpendicular to lower bit line 308A and upper bit line 308B. In one example, the critical dimension, e.g., the width in the y-direction, of word lines 312 may be about 20 nm, and the pitch of word lines 312 is about 40 nm.Lower bit lines 308A, upper bit line 308B, and word lines 312 may include conductive materials including, but not limited to, tungsten (W) , cobalt (Co) , copper (Cu) , aluminum (Al) , polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each of lower bit lines 308A, upper bit line 308B, and word lines 312 includes a metal, such as tungsten.

3D PCM memory device 300 includes a plurality of lower memory cells 314A each disposed at an intersection of lower bit line 308A and a respective one of word lines 312, and a plurality of upper memory cells 314B each disposed at an intersection of upper bit line 308B and a respective one of word lines 312. Each

memory cell

314A or 314B may be accessed individually by a current applied through respective word line 312 and

bit line

308A or 308B in contact with

memory cell

314A or 314B. Each of lower and

upper memory cells

314A and 314B can include stacked a PCM element 322, a selector 318, and a plurality of

electrodes

316, 320, and 324. PCM element 322 can utilize the difference between the resistivity of the amorphous and the crystalline phase in phase-change materials based on heating and quenching of the phase-change materials electrothermally. Electrical currents can be applied to switch the phase-change material (or at least a fraction of it that blocks the current path) of PCM element 322 repeatedly between the two phases to store data. A single bit of data can be stored in each

memory cell

314A or 314B and can be written or read by varying the voltage applied to respective selector 318, which eliminates the need for transistors. In some implementations, three

electrodes

316, 320, and 324 are disposed below selector 318, between selector 318 and PCM element 322, and above PCM element 322, respectively. It is understood that the relative positions of selector 318 and PCM element 322 may be switched in other implementations.

Selector 318 and PCM element 322 may be in a double-stacked storage/selector structure. The materials of PCM element 322 include chalcogenide-based alloys (chalcogenide glass) , such as GST (Ge-Sb-Te) alloy, or any other suitable phase-change materials. The materials of selector 318 may include any suitable ovonic threshold switch (OTS) materials, such as Zn _xTe _y, Ge _xTe _y, Nb _xO _y, Si _xAs _yTe _z, etc. It is understood that the structure, configuration, and materials of memory array 302 are not limited to the example in FIG. 3C and may include any suitable structure, configuration, and materials.

Electrodes

316, 320, and 324 may include conductive materials including, but not limited to, W, Co, Cu, Al, carbon, polysilicon, doped silicon, silicides, or any combination thereof. In some implementations, each of

electrodes

316, 320, and 324 includes carbon, such as amorphous carbon.

As shown in FIG. 3C, 3D PCM memory device 300 may further include a lower bit line contact 310A below and in contact with lower bit line 308A, and an upper bit line contact 310B above and in contact with upper bit line 308B. Lower bit line contact 310A extends downwards, and upper bit line contact 310B extends upwards. That is, lower and upper

bit line contacts

310A and 310B can extend vertically in opposite directions. Lower bit line contact 310A and upper bit line contact 310B may include conductive materials including, but not limited to, W, Co, Cu, Al, polysilicon, doped silicon, silicides, or any combination thereof. Each of lower bit line contact 310A and upper bit line contact 310B includes a metal, such as tungsten. Thus, lower bit line contact 310A and upper bit line contact 310B are electrically connected to lower bit line 308A and upper bit line 308B, respectively, for individually addressing respective lower memory cell 314A or upper memory cell 314B.

As described above,

bit line contacts

310A and 310B can have a non-relaxed critical dimension, i.e., shrunk contact size, to further efficiently use the chip space. In some implementations, the critical dimension (e.g., the diameter) of at least one of lower bit line contact 310A and upper bit line contact 310B is not greater than the critical dimension (e.g., the width in the x-direction) of corresponding lower bit line 308A or upper bit line 308B. In one example, the critical dimension of at least one of lower bit line contact 310A and upper bit line contact 310B may be the same as the critical dimension of corresponding lower bit line 308A or upper bit line 308B. In another example, the critical dimension of at least one of lower bit line contact 310A and upper bit line contact 310B may be smaller than the critical dimension of corresponding lower bit line 308A or upper bit line 308B. In some implementations, the critical dimension of at least one of lower and upper

bit line contacts

310A and 310B is not greater than about 60 nm, such as not greater than 60 nm. In some implementations, the critical dimension of at least one of lower and upper

bit line contacts

310A and 310B is between about 10 nm and about 30 nm, such as between 10 nm and 30 nm (e.g., 10 nm, 11 nm, 12 nm, 13 nm, 14 nm, 15 nm, 16 nm, 17 nm, 18 nm, 19 nm, 20 nm, 21 nm, 22 nm, 23 nm, 24 nm, 25 nm, 26 nm, 27 nm, 28 nm, 29 nm, 30 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some implementations, the critical dimension of each of lower and upper

bit line contacts

310A and 310B is not greater than the critical dimension of each of lower and

upper bit lines

308A and 308B. In some implementations, the critical dimension of both

bit lines

308A and 308B and bit

line contacts

310A and 310B is about 20 nm, such as 20 nm.

In some implementations, at least one of lower and upper

bit line contacts

310A and 310B has the same pitch as corresponding lower bit line 308A or upper bit line 308B. In some implementations, the pitch is not greater than about 80 nm, such as not greater than 80 nm.In some implementations, the pitch is between about 20 nm and about 60 nm, such as between 20 nm and 60 nm (e.g., 20 nm, 22 nm, 24 nm, 26 nm, 28 nm, 30 nm, 32 nm, 34 nm, 36 nm, 38 nm, 40 nm, 42 nm, 44 nm, 46 nm, 48 nm, 50 nm, 52 nm, 54 nm, 56 nm, 58 nm, 60 nm, any range bounded by the lower end by any of these values, or in any range defined by any two of these values) . In some implementations, the pitch of each of lower and upper

bit line contacts

310A and 310B is not greater than the pitch of each of lower and

upper bit lines

308A and 308B. In some implementations, the pitch of both

bit lines

308A and 308B and bit

line contacts

310A and 310B is about 40 nm, such as 40 nm. By having

bit line contacts

310A and 310B with non-relaxed critical dimension and pitch,

bit line contacts

310A and 310B may be in contact with

bit lines

308A and 308B directly, as opposed to being in contact with bit line extensions (e.g., 210 as shown in FIG. 2C) .

At least one of lower bit line contact 310A and upper bit line contact 310B is disposed inclusively between lower and

upper memory cells

314A and 314B of memory array 302 in the plan view (parallel to the wafer plane) . As used herein, a

bit line contact

310A or 310B is disposed “inclusively between”

memory cells

314A and 314B of memory array 302 (i) when the

bit line contact

310A or 310B overlaps at least one of

memory cells

314A and 314B in the plan view, or (ii) when the

bit line contact

310A or 310B is disposed between

memory cells

314A and 314B in the plan view. As shown in FIG. 3C, since

memory cells

314A and 314B are arranged at the intersections of word lines 312 and

bit lines

308A and 308B and each

bit line contact

310A or 310B is in contact with

respective bit line

308A or 308B, the

outermost memory cells

314A and 314B of memory array 302 in the bit line direction (the y-direction) define a range (between the boundaries “a” and “b” ) in which lower bit line contact 310A and/or upper bit line contact 310B may be disposed. In the example of FIG. 3C, both lower bit line contact 310A and upper bit line contact 310B overlap

outermost memory cells

314A and 314B, respectively. That is, each

bit line contact

310A or 310B is disposed within the memory array region of memory array 302. It is understood that lower bit line contact 310A and/or upper bit line contact 310B may be disposed in any position inclusively between

memory cells

314A and 314B in the plan view (e.g., anywhere between the boundaries “a” and “b” in FIG. 3C) . In some implementations, at least one of lower bit line contact 310A and upper bit line contact 310B is disposed between lower and

upper memory cells

314A and 314B of memory array 302 in the plan view, i.e., not overlapping with

memory cell

314A or 314B in the plan view.

Although in FIG. 3C, each of lower and upper

bit line contacts

310A and 310B is disposed inclusively between lower and

upper memory cells

314A and 314B of memory array 302 in the plan view, it is understood that one of the lower bit line contact and upper bit line contacts may be disposed outside of the memory array in the plan view in some other implementations. In other words, the lower bit line contact or the upper bit line contact is disposed inclusively between the lower and upper memory cells in the plan view. For example, FIG. 4A shows a perspective view of another illustrative 3D PCM memory device 400, and FIG. 4B shows a perspective view of still another illustrative 3D PCM memory device 401. 3D PCM memory device 400 is similar to 3D PCM memory device 300 in FIG. 3C except for the upper bit line and upper bit line contact.

As shown in FIG. 4A, upper bit line 402B extends laterally beyond memory array 302 in the bit line direction (the y-direction) , and upper bit line contact 404B in contact with upper bit line 402B is not disposed inclusively between lower and

upper memory cells

314A and 314B of memory array 302 in the plan view, according to some implementations. That is, lower bit line contact 310A is disposed within the memory array region of memory array 302, while upper bit line contact 404B is disposed outside of the memory array region of memory array 302, according to some implementations. In some implementations, lower bit line contact 310A and upper bit line contact 404B extend towards the same direction, e.g., downwards as shown in FIG. 4A, such that

bit line contacts

310A and 404B can be padded-out from the same side of 3D PCM memory device 400. Although upper bit line 402B extends beyond memory array 302 in FIG. 4A, it is understood that the critical dimension of upper bit line 402B may not increase, i.e., not forming an upper bit line extension, and the critical dimension (e.g., the diameter) of upper bit line contact 404B may not be greater than the critical dimension (e.g., the width in the x-direction) of upper bit line 402B as described above in detail.

Referring to FIG. 4B, 3D PCM memory device 401 is similar to 3D PCM memory device 300 except for the lower bit line and lower bit line contact. The structures, functions, and materials of the same components that have been described above with respect to 3D PCM memory device 300 are not repeated for ease of description. As shown in FIG. 4B, lower bit line 406A extends laterally beyond memory array 302 in the bit line direction (the y-direction) , and lower bit line contact 408A in contact with lower bit line 406A is not disposed inclusively between lower and

upper memory cells

314A and 314B of memory array 302 in the plan view, according to some implementations. That is, upper bit line contact 310B is disposed within the memory array region of memory array 302, while lower bit line contact 408A is disposed outside of the memory array region of memory array 302, according to some implementations. In some implementations, lower bit line contact 408A and upper bit line contact 310B extend towards the same direction, e.g., upwards as shown in FIG. 4B, such that

bit line contacts

408A and 310B can be padded-out from the same side of 3D PCM memory device 400. Although lower bit line 406A extends beyond memory array 302 in FIG. 4B, it is understood that the critical dimension of lower bit line 406A may not increase, i.e., not forming a lower bit line extension, and the critical dimension (e.g., the diameter) of lower bit line contact 408A may not be greater than the critical dimension (e.g., the width in the x-direction) of lower bit line 406A as described above in detail.

FIGs. 5A–5L show an Illustrative fabrication process for forming a 3D PCM memory device, in accordance with the present disclosure. FIG. 6 is a flowchart of an illustrative method 600 for forming a 3D PCM memory device, in accordance with the present disclosure. Examples of the 3D PCM memory device depicted in FIGs. 5A–5L and 6 include 3D PCM memory device 400 (see FIG. 4A) . FIGs. 5A–5L and 6 will be described together. The operations of method 600 are not exhaustive, and other operations may be performed as well before, after, or between any of the illustrated operations. Further, some of the operations may be performed concurrently, or in a different order than shown in FIG. 6.

Referring to FIG. 6, method 600 starts at operation 602, in which a lower bit line contact and a lower bit line in contact with the lower bit line contact are formed. Forming the lower bit line contact may include in-situ polymer deposition and etching, such that a critical dimension of the lower bit line contact is not greater than a critical dimension of the lower bit line. In some implementations, to form the lower bit line, a layer of conductor is deposited, the layer of conductor is double patterned, and the double-patterned layer of conductor is etched. The layer of conductor can include tungsten. In some implementations, the critical dimension of the lower bit line contact is not greater than the critical dimension of the lower bit line. For example, the critical dimension is not greater than about 60 nm, such as between about 10 nm and about 30 nm. The lower bit line contact may have the same pitch as the lower bit line. For example, the pitch is not greater than about 80 nm.

Referring to FIG. 5A, a plurality of lower bit line contacts 504 are formed through a dielectric layer 502. To form the lower bit line contacts 504, dielectric layer 502 having a dielectric material, such as silicon oxide, can be first formed by one or more thin film deposition processes including, but not limited to, chemical vapor deposition (CVD) , physical vapor deposition (PVD) , atomic layer deposition (ALD) , or any combination thereof. The contact holes (not shown) of lower bit line contacts 504 with non-relaxed critical dimension and pitch as described above in detail can be etched through dielectric layer 502 using in-situ polymer deposition and etching to control the dimension of the contact holes. For example, a plasma etching process may be modified such that polymer deposition (e.g., accumulation of a fluorocarbon polymer layer) occurs during plasma etching to control etch rate (also known as “polymerization” ) . Plasma etching may then be performed in the same plasma etcher to etch back and eventually remove the polymer layer. The in-situ polymer deposition and etching may further reduce the critical dimension of lower bit line contacts 504 after patterning in order to achieve shrunk contact size that may not be easily achieved by photolithography. For example, the critical dimension of the contact holes of lower bit line contacts 504 may be between about 50 nm and about 60 nm after photolithography and may be further reduced to about 20 nm and about 30 nm after in-situ polymer deposition and etching. After the formation of the contact holes, lower bit line contacts 504 can be formed by depositing one or more conductive materials, such as tungsten, to fill the contact holes using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. Lower bit line contacts 504 can be further planarized by chemical mechanical polishing (CMP) and/or etching such that the upper ends (the top surfaces) of lower bit line contacts 504 are flush with the top surface of dielectric layer 502.

Referring to FIG. 5A, a conductor layer 508 is formed on dielectric layer 502 and in contact with lower bit line contacts 504. A metal layer, such as a tungsten layer, may be deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. As described below in detail with respect to FIG. 5B, conductor layer 508 is then double patterned, and the double-patterned conductor layer 508 is etched to form lower bit lines 536 above and in contact with lower bit line contacts 504, respectively.

Method 600 proceeds to operation 604, as shown in FIG. 6, in which a plurality of lower memory cells are formed above and in contact with the lower bit line. Each of the lower memory cells can include stacked a PCM element, a selector, and a plurality of electrodes. In some implementations, the lower bit line contact is disposed inclusively between the lower memory cells in the plan view. To form the plurality of lower memory cells, layers of a first conductor, an OTS material, a second conductor, a chalcogenide-based alloy, and a third conductor are subsequently deposited to form a memory stack, and the memory stack is subsequently etched in two perpendicular directions. Each of the first, second, and third conductors can include amorphous carbon. In some implementations, to subsequently etch the memory stack, the memory stack is double patterned in a first direction of the two perpendicular directions, the double-patterned memory stack is etched in the first direction to form a first gap, the first gap is filled with a dielectric material, the etched memory stack is double patterned in a second direction of the two perpendicular directions, the double-patterned, etched memory stack is etched in the second direction to form a second gap, and the second gap is filled with the dielectric material.

Still referring to FIG. 5A, a lower memory stack 506 is formed on conductor layer 508. In some implementations, to form lower memory stack 506, a first conductor layer 510, an OTS material layer 512, a second conductor layer 514, a chalcogenide-based alloy layer 516, and a third conductor layer 518 are subsequently deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. For example, each of first, second, and third conductor layers 510, 514, and 518 may include amorphous carbon, OTS material layer 512 may include Zn _xTe _y, Ge _xTe _y, Nb _xO _y, Si _xAs _yTe _z, etc., and chalcogenide-based alloy layer 516 may include GST alloy. It is understood that the sequence of depositing OTS material layer 512 and chalcogenide-based alloy layer 516 may be switched in some implementations. In some implementations, a dielectric layer 520 is formed on lower memory stack 506 by depositing dielectric materials, such as silicon nitride, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Referring to FIG. 5B, lower memory stack 506 and conductor layer 508 therebelow and dielectric layer 520 thereabove (see FIG. 5A) are etched in the bit line direction (the y-direction) . Lower memory stack 506, conductor layer 508, and dielectric layer 520 may be double patterned first in the bit line direction. For example, an etching mask (not shown) is patterned on dielectric layer 520 by photolithography, development, and etching. The etching mask can be a photoresist mask, or a hard mask patterned based on a photolithography mask. Double patterning may include, but is not limited to, litho-etch-litho-etch (LELE) pitch-splitting or self-aligned double patterning (SADP) , to control the critical dimensions of lower bit lines 536 and lower memory cells 538 (see FIG. 5G) to be formed. In some implementations, double-patterned lower memory stack 506, conductor layer 508, and dielectric layer 520 are etched in the bit line direction to form parallel first gaps 522 in the bit line direction. Lower memory stack 506, conductor layer 508, and dielectric layer 520 can be etched through by one or more wet etching and/or dry etching processes, such as deep reactive-ion etching (DRIE) , using the double-patterned etching mask to simultaneously form parallel first gaps 522. Parallel lower bit lines 536 extending along the bit line direction are thereby formed, which are above and in contact with lower bit line contacts 504. Etched memory stacks 524 are thereby formed as well, separated by first gaps 522.

Referring to FIG. 5C, first gaps 522 are filled with a dielectric material 526, such as, but not limited to, silicon oxide. In some implementations, dielectric material 526 is deposited into first gaps 522 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof, followed by planarization processes, such as CMP and/or etching. For example, silicon oxide may be deposited into first gaps 522 using ALD, followed by CMP, to fill first gaps 522.

Referring to FIG. 5D, a plurality of word line contacts 528 are formed on dielectric layer 502. Word line contacts 528 may be formed first by patterning, followed by in-situ polymer deposition and etching, and one or more thin film deposition processes such as CVD, PVD, or ALD. The upper ends (the top surface) of word line contacts 528 can be planarized using CMP to be flush with the top surface of etched memory stacks 524. During the planarization processes, dielectric layer 520 (see FIG. 5C) and the top portion of dielectric material 526 are removed to expose the top surface of third conductor layers 518 of etched memory stacks 524.

Method 600 proceeds to operation 606, in which a plurality of parallel word lines in the same plane are formed above, and in contact with, the lower memory cells. Each of the word lines may be perpendicular to the lower bit line. To form the word lines, a layer of conductor is deposited, the layer of conductor is double patterned, and the double-patterned layer of conductor is etched.

Referring to FIG. 5E, a conductor layer 530 is formed on etched memory stacks 524 and dielectric materials 526 and in contact with the upper ends of word line contacts 528. A metal layer, such as a tungsten layer, may be deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Referring to FIG. 5F, conductor layer 530 is then double patterned in the word line direction (the x-direction) to form etching masks 532 extending along the word line direction. Etching masks 532 can be patterned on conductor layer 530 by photolithography, development, and etching. Etching masks 532 can be photoresist masks or hard masks patterned based on a photolithography mask. Double patterning may include, but is not limited to, LELE pitch-splitting or SADP, to control the critical dimensions of lower word lines 534 and lower memory cells 538 (see FIG. 5G) to be formed. The double patterning process in FIG. 5F is performed in the word line direction, which is perpendicular to the bit line direction in which the double patterning process in FIG. 5B is performed.

Referring to FIG. 5G, conductor layer 530 (see FIG. 5F) and etched memory stacks 524 therebelow are etched in the word line direction (the x-direction) to form second gaps 537 in the word line direction. The etching stops at lower bit lines 536, such that lower bit lines 536 remain intact. Conductor layer 530 and etched memory stacks 524 can be etched through by one or more wet etching and/or dry etching processes, such as DRIE, using etching masks 532 to simultaneously form parallel second gaps 537. Parallel lower word lines 534 extending along the word line direction are thereby formed to be above and in contact with word line contacts 528, according to some implementations. Lower memory cells 538 are thereby formed as well at intersections of lower bit lines 536 and lower word lines 534, respectively. Each lower memory cell 538 may include first conductor layer 510 (as the first electrode) , OTS material layer 512 (as the selector) , second conductor layer 514 (as the second electrode) , chalcogenide-based alloy layer 516 (as the PCM element) , and third conductor layer 518 (as the third electrode) . Lower memory cells 538 are above and in contact with lower bit lines 536. Lower memory cells 538 may be patterned (e.g., by the double patterning process in FIG. 5F) , such that each lower bit line contact 504 is disposed inclusively between lower memory cells 538 in the plan view.

Although not shown, second gaps 537 may be filled with a dielectric material, such as silicon oxide. In some implementations, the dielectric material is deposited into second gaps 537 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof, followed by planarization processes, such as CMP and/or etching. For example, silicon oxide may be deposited into second gaps 537 using ALD, followed by CMP, to fill second gaps 537.

Method 600 proceeds to operation 608 in which a plurality of upper memory cells are formed above and in contact with the word lines. Each of the upper memory cells can include stacked a PCM element, a selector, and a plurality of electrodes. Each of the upper memory cells can be in contact with a respective one of the word lines. To form the plurality of upper memory cells, layers of a first conductor, an OTS material, a second conductor, a chalcogenide-based alloy, and a third conductor are subsequently deposited to form a memory stack, and the memory stack is subsequently etched in two perpendicular directions. Each of the first, second, and third conductors can include amorphous carbon. In some implementations, to subsequently etch the memory stack, the memory stack is double patterned in a first direction of the two perpendicular directions, the double-patterned memory stack is etched in the first direction to form a first gap, the first gap is filled with a dielectric material, the etched memory stack is double patterned in a second direction of the two perpendicular directions, the double-patterned, etched memory stack is etched in the second direction to form a second gap, and the second gap is filled with the dielectric material.

Referring to FIG. 5H, a conductor layer 542 is formed on lower word lines 534, and an upper memory stack 540 is formed on conductor layer 542. In some implementations, to form upper memory stack 540, a first conductor layer 544, an OTS material layer 546, a second conductor layer 548, a chalcogenide-based alloy layer 550, and a third conductor layer 552 are subsequently deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof. For example, each of first, second, and third conductor layers 544, 548, and 552 may include amorphous carbon, OTS material layer 546 may include Zn _xTe _y, Ge _xTe _y, Nb _xO _y, Si _xAs _yTe _z, etc., and chalcogenide-based alloy layer 550 may include GST alloy. It is understood that the sequence of depositing OTS material layer 546 and chalcogenide-based alloy layer 550 may be switched in some implementations. A dielectric layer 554 is formed on upper memory stack 540 by depositing dielectric materials, such as silicon nitride, using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Referring to FIG. 5I, upper memory stack 540 and conductor layer 542 therebelow (see FIG. 5H) and dielectric layer 554 thereabove are etched in the word line direction (the x-direction) . Upper memory stack 540, conductor layer 542, and dielectric layer 554 may be double patterned first in the word line direction. For example, an etching mask (not shown) is patterned on dielectric layer 554 by photolithography, development, and etching. The etching mask can be a photoresist mask, or a hard mask patterned based on a photolithography mask. Double patterning may include, but is not limited to, LELE pitch-splitting or SADP, to control the critical dimensions of upper word lines 534 and upper memory cells 562 (see FIG. 5L) to be formed. In some implementations, double-patterned upper memory stack 540, conductor layer 542, and dielectric layer 554 are etched in the word line direction to form parallel first gaps 556 in the word line direction. Upper memory stack 540, conductor layer 542, and dielectric layer 554 can be etched through by one or more wet etching and/or dry etching processes, such as DRIE, using the double-patterned etching mask to simultaneously form parallel first gaps 556. Parallel upper word lines 543 extending along the word line direction are thereby formed to be above and in contact with lower word line 534, according to some implementations. Etched memory stacks 541 are thereby formed as well, separated by first gaps 556. It is understood that in some implementations, conductor layer 542 and resulting upper word lines 543 may be omitted, such that the word lines include only lower word lines 534, but not upper word lines 543.

Although not shown, first gaps 556 may be filled with a dielectric material, such as silicon oxide. In some implementations, the dielectric material is deposited into first gaps 556 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof, followed by planarization processes, such as CMP and/or etching. For example, silicon oxide may be deposited into first gaps 556 using ALD, followed by CMP, to fill first gaps 556.

In some implementations, an upper bit line contact is formed prior to the formation of upper memory cells. Forming the upper bit line contact can include in-situ polymer deposition and etching, such that a critical dimension of the upper bit line contact is not greater than a critical dimension of the upper bit line. For example, the critical dimension is not greater than about 60 nm, such as between about 10 nm and about 30 nm. In some implementations, the upper bit line contact has the same pitch as the upper bit line. For example, the pitch is not greater than about 80 nm.

Referring to FIG. 5J, a plurality of upper bit line contacts 558 are formed. In some implementations, upper bit line contacts 558 are formed first by patterning, followed by in-situ polymer deposition and etching. The contact holes (not shown) of upper bit line contacts 558 with non-relaxed critical dimension and pitch as described above in detail can be etched using in-situ polymer deposition and etching to control the dimension of the contact holes. For example, a plasma etching process may be modified such that polymer deposition (e.g., accumulation of a fluorocarbon polymer layer) occurs during plasma etching to control etch rate (also known as “polymerization” ) . Plasma etching may then be performed in the same plasma etcher to etch back and eventually remove the polymer layer. The in-situ polymer deposition and etching can further reduce the critical dimension of upper bit line contacts 558 after patterning in order to achieve shrunk contact size that may not be easily achieved by photolithography. After the formation of the contact holes, upper bit line contacts 558 can be formed by depositing one or more conductive materials, such as tungsten, to fill the contact holes using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof. The upper ends (the top surface) of upper bit line contacts 558 can be planarized using CMP to be flush with the top surface of etched memory stacks 541. During the planarization processes, dielectric layer 554 (shown in FIG. 5I) and the top portion of dielectric materials (not shown) filing first gaps 556 are removed to expose the top surface of third conductor layers 552.

Method 600 proceeds to operation 610, as shown in FIG. 6, in which an upper bit line is formed above and in contact with the upper memory cells. The upper bit line can be perpendicular to each of the word lines. In some implementations, to form the upper bit line, a layer of conductor is deposited, the layer of conductor is double patterned, and the double-patterned layer of conductor is etched.

Referring to FIG. 5K, a conductor layer 564 is formed on etched memory stacks 541 and the dielectric materials (not shown) filling first gaps 556 (see FIG. 5J) . Conductor layer 564 is above and in contact with upper bit line contacts 558 and etched memory stacks 541 (see FIG. 5J) , according to some implementations. In some implementations, a metal layer, such as a tungsten layer, is deposited using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, or any combination thereof.

Conductor layer 564 is then double patterned in the bit line direction (the y-direction) to form etching masks 568 extending along the bit line direction. Etching masks 568 can be patterned on conductor layer 564 by photolithography, development, and etching. Etching masks 568 can be photoresist masks or hard masks patterned based on a photolithography mask. Double patterning can include, but not limited to, LELE pitch-splitting or SADP, to control the critical dimensions of upper bit lines 560 and upper memory cells 562 (see FIG. 5L) to be formed. The double patterning process in FIG. 5K is performed in the bit line direction.

Referring to FIG. 5L, conductor layer 564 (see FIG. 5K) and etched memory stacks 541 therebelow are etched in the bit line direction (the y-direction) to form second gaps 570 in the bit line direction. The etching stops at upper word lines 543, such that upper word lines 543 remain intact, according to some implementations. Conductor layer 564 and etched memory stacks 541 can be etched through by one or more wet etching and/or dry etching processes, such as DRIE, using etching masks 568 (see FIG. 5K) to simultaneously form parallel second gaps 570. Parallel upper bit lines 560 extending along the bit line direction are thereby formed to be above and in contact with upper bit line contacts 558, according to some implementations. Upper memory cells 562 are thereby formed as well at intersections of upper bit lines 560 and upper word lines 543, respectively. Each upper memory cell 562 can include first conductor layer 544 (as the first electrode) , OTS material layer 546 (as the selector) , second conductor layer 548 (as the second electrode) , chalcogenide-based alloy layer 550 (as the PCM element) , and third conductor layer 552 (as the third electrode) . Upper bit lines 560 are also above and in contact with upper memory cells 562, according to some implementations. The top surface of each upper memory cell 562 is flush with the top surface (the upper ends) of upper bit line contacts 558.

Although not shown, second gaps 570 may be filled with a dielectric material, such as silicon oxide. The dielectric material may be deposited into second gaps 570 using one or more thin film deposition processes including, but not limited to, CVD, PVD, ALD, electroplating, electrodeless plating, any other suitable deposition process, or any combination thereof, followed by planarization processes, such as CMP and/or etching. For example, silicon oxide may be deposited into second gaps 570 using ALD, followed by CMP.

As described above, upper bit line contacts 558 are formed prior to the formation of upper memory cells 562. Thus, upper bit line contacts 558 (see as shown in FIG. 5L) , which extend downwards, are not formed inclusively between upper memory cells 562 in the plan view. In some implementations, the upper bit line contacts may be formed after the formation of upper memory cells 562, such that the upper bit line contacts can be formed inclusively between upper memory cells 562 in the plan view. For example, method 600 may optionally proceed to operation 612, in which an upper bit line contact is formed above and in contact with the upper bit line. In some implementations, the upper bit line contact is disposed inclusively between the upper memory cells in the plan view. In some implementations, forming the upper bit line contact includes in-situ polymer deposition and etching, such that a critical dimension of the upper bit line contact is not greater than a critical dimension of the upper bit line. For example, the critical dimension is not greater than about 60 nm, such as between about 10 nm and about 30 nm. In some implementations, the upper bit line contact has the same pitch as the upper bit line. For example, the pitch is not greater than about 80 nm. The details of forming the upper bit line contacts are substantially similar to those of forming lower bit line contacts 504 described above with respect to FIG. 5A. Once formed, the upper bit line contacts are above and in contact with upper bit lines 560 and are also inclusively between upper memory cells 562 in the plan view.

Description of a Multi-Die 3D PCM Architecture

Having described the structure and formation of 3D PCM cells above, multi-die implementations are now described, that provide improved bit density by way of greater array efficiency, as compared to previous architectures for 3D phase-change memories. By providing electrical pathways to the 3D PCM array from bit line decoders and word line decoders that are disposed below the 3D PCM array on a first die, and further providing electrical pathways from bit line decoders and word line decoders that are disposed above the 3D PCM array, and located on another die that is face-to-face hybrid-bonded with the first die, routing congestion is reduced or eliminated, thereby enabling closer packing of the PCM cells.

FIG. 7 is a schematic stick-figure illustration of a previous 3D PCM array architecture having bit line decoder circuitry and word line decoder circuitry on the same die as the 3D PCM array, and thereby occupying area that could otherwise be used for memory cells. Referring to FIG. 7, word lines 702 are shown running horizontally, and bit lines 704 are shown running vertically. At each location where a word line 702 crosses a bit line 704 a PCM cell is disposed. The locations of various bit line contacts are indicated by black dots on bit lines. Still referring to the previous 3D PCM array architecture of FIG. 7, a word line contact area 706 (within the dashed line box) is shown. It is noted that no bit lines are placed in word line contact area 706, thus there are no word line/bit line overlaps at which a PCM cell can be formed. Thus, the layout efficiency of this previous 3D PCM array architecture is limited.

FIG. 8A is a block diagram illustrating a first die having bit line decoder circuitry, an array of PCM cells, and a hybrid-bonding layer; and a second die having word line decoder circuitry and another hybrid-bonding layer, oriented in a face-to-face arrangement prior to hybrid bonding. FIG. 8A illustrates an intermediate stage of fabricating an implementation in accordance with the 3D PCM architecture of the present disclosure.

Still referring to FIG. 8A, a first die 802 is provided. First die 802 includes at least bit line decoder circuitry 806, and a 3D PCM array 808 disposed above at least bit line decoder circuitry 806. Further, a first hybrid-bonding layer 810 is disposed above the 3D PCM array 808, and prior to undergoing a hybrid bonding operation, first hybrid-bonding layer 810 is the topside layer of first die 802. First hybrid-bonding layer 810 is a dielectric layer with a plurality of electrically conductive bonding contacts disposed therein. In some implementations, the bonding contacts include at least copper.

Still referring to FIG. 8A, a second die 804 is provided, and shown in an inverted orientation, such that its topside surface is facing the topside surface of first die 802. Second die 804 includes at least word line decoder circuitry 814, and a second hybrid-bonding layer 812. Second hybrid-bonding layer 812 is a dielectric layer with a plurality of electrically conductive bonding contacts disposed therein. In some implementations, the bonding contacts include at least copper.

FIG. 8B is a block diagram illustrating the first die and second die of FIG. 8A, after hybrid bonding to each other. Referring to FIGs. 8A–8B, first die 802 and second die 804 are hybrid bonded to each other to form a multi-die device 816. Hybrid bonding of first die 802 and second die 804 brings first hybrid-bonding layer 810 and second hybrid-bonding layer 812 into contact with each other so as to attach first die 802 and second die 804 to each other and form a hybrid bonding layer 820. As will be appreciated, in some implementations, such hybrid bonding may be achieved by die-to-die hybrid bonding. In other implementations, such hybrid bonding may be achieved by wafer-to-wafer hybrid bonding. Typically, after wafer-to-wafer hybrid bonding, a separation operation may be performed to separate the hybrid-bonded dice from the wafers (but not from each other) . Such a separation operation may be referred to as singulation.

Still referring to FIG. 8B, hybrid bonding not only mechanically attaches first die 802 and second die 804 to each other, it also creates a plurality of electrical pathways between first die 802 and second die 804. These electrical pathways are formed because the electrically conductive first hybrid-bonding contacts disposed in the first hybrid-bonding layer, and the electrically conductive second hybrid-bonding contacts disposed in the second hybrid-bonding layer are in physical contact as a result of the hybrid bonding operation. In this way, electrical signals may pass in either direction between first die 802 and second die 804 of the multi-die device 816.

FIG. 9 is a cross-sectional view of an example first die 902, including bit line decoder circuitry, a 3D PCM cell array disposed above the bit line decoder circuitry, and a first hybrid-bonding layer disposed on a topside thereof. Essentially, this cross-sectional view is a more detailed version of first die 802 that is shown in block diagram form in FIG. 8A. In FIG. 9, the three major sections of first die 802, i.e., bit

line decoder circuitry

806, 3D PCM array 808 disposed above at least bit line decoder circuitry 806, and first hybrid-bonding layer 810 disposed above 3D PCM array 808, are shown but represented by component illustrations rather than by blocks. However, FIG. 9 also shows a detail not illustrated in FIG. 8A, that is, the first hybrid-bonding contacts. As mentioned above, subsequent to hybrid bonding, the first hybrid-bonding contacts are in physical contact with the second hybrid-bonding contacts and thus allow electrical continuity throughout multi-die device 816.

FIGs. 10A-10B illustrate, respectively, a cross-sectional view of an example second die 1002 in a partially fabricated state, including word line decoder circuitry and array circuitry; and a cross-sectional view of an example second die 1004, the fabrication of which is complete. That is, second die 1004 of FIG. 10B is the second die 1002 after back-end-of line (BEOL) processing.

Essentially, the cross-sectional view of FIG. 10B is a more detailed version of example second die 804 shown in block diagram form in FIG. 8A. Fully fabricated example second die 1004 shows the word line decoder 816, and hybrid-bonding layer 812 represented by component illustrations rather than in block diagram form. However, FIG. 10B also shows a detail not illustrated in FIG. 8A, that is, the second hybrid-bonding contacts. As mentioned above, subsequent to hybrid bonding, the first hybrid-bonding contacts are in physical contact with the second hybrid-bonding contacts and thus allow electrical continuity throughout multi-die device 816.

FIG. 11 is a cross-sectional view of an example multi-die 3D PCM device 1100 having a PCM array on one die, and the word line decoder associated with the PCM array on a different die. FIG. 11 shows example first die 902 of FIG. 9 hybrid-bonded to example second die 1004. By placing word line decoder circuitry on a different die from the one in which a 3D PCM array and its associated bit line decoders are disposed, implementations in accordance with the present disclosure may pack a plurality of 3D PCM arrays more closely together than with previous 3D PCM architectures. Thus, implementations of the 3D PCM architecture in accordance with the present disclosure provide improved array efficiency and greater bit density.

FIGs. 12A –14B collectively show three different illustrative implementations of an 8-stack 3D PCM array. These three implementations all share a common arrangement of bit lines and word lines in the 8-stack 3D PCM array. However, these implementations differ in the placement of bit line and word line decoders relative to the 8-stack 3D PCM array, and further differ in the arrangement of contact structures for routing the connections between the bit lines and the bit line decoders, and the connections between the word lines and the word line decoders.

FIGs. 12A-12B illustrate an implementation in which a bit line decoder and a word line decoder are disposed on a first die with the 8-stack 3D PCM array disposed above the decoders on the first die, another word line decoder is disposed on a second die that is hybrid-bonded to the first die, all the bit lines are coupled to the bit line decoders of the first die, some of the word lines are coupled to the word line decoder of the first die, and the rest of the word lines are coupled to the word line decoder of the second die.

FIGs. 13A-13B illustrate another implementation in which a bit line decoder and a word line decoder are disposed on a first die with the 8-stack 3D PCM array disposed above the decoders on the first die, another bit line decoder and another word line decoder are disposed on a second die that is hybrid-bonded to the first die, three of the five bit lines in the 8-stack 3D PCM array are coupled to the bit line decoder of the first die, while other two bit lines are coupled to the bit line decoder of the second die, and two of the four word lines in the 8-stack 3D PCM array are coupled to the word line decoder of the first die, while other two word lines are coupled to the word line decoder of the second die.

FIGs. 14A-14B illustrate yet another implementation in which a bit line decoder and a word line decoder are disposed on a first die with the 8-stack 3D PCM array disposed above the decoders on the first die, another bit line decoder and another word line decoder are disposed on a second die that is hybrid-bonded to the first die, two of the five bit lines in the 8-stack 3D PCM array are coupled to the bit line decoder of the first die, while the other three bit lines are coupled to the bit line decoder of the second die, and two of the four word lines in the 8-stack 3D PCM array are coupled to the word line decoder of the first die, while other two word lines are coupled to the word line decoder of the second die.

FIG. 12A is a cross-sectional representation, in the X-direction, of an example implementation of an 8-stack 3D PCM array, showing the spatial relationship between the first bit lines, first word lines, second bit lines, second word lines, third bit lines, third word lines, fourth bit lines, fourth word lines, and fifth bit lines, together with the contact structures between the bit lines and the bit line decoders of both the first die and the second die. Likewise, FIG. 12A also shows the contact structures between the word lines and the word line decoders of both the first die and the second die. For the sake of clarity, and ease of understanding, details of the first, second, third, fourth, fifth, sixth, seventh, and eighth 3D PCM cell stacks themselves, are not shown in FIG. 12A. However, the locations of those 3D PCM cell stacks are indicated by labelling in FIG. 12A.

Referring to FIG. 12A, a plurality of first bit lines 1202 are shown. Cross-sections of a plurality of first word lines 1204 are shown. First word lines 1204 are disposed above first bit lines 1202, and are arranged perpendicularly to first bit lines 1202. A plurality of second bit lines 1206 are shown disposed above first word lines 1204, and are arranged perpendicularly to first word lines 1204. Cross-sections of a plurality of second word lines 1208 are shown disposed above second bit lines 1206. Second word lines 1208 are arranged perpendicularly to second bit lines 1206. A plurality of third bit lines 1210 are shown disposed above second word lines 1208. Third bit lines 1210 are arranged perpendicularly to second word lines 1208. Cross-sections of a plurality of third word lines 1212 are shown disposed above third bit lines 1210. Third word lines 1212 are arranged perpendicularly to third bit lines 1210. A plurality of fourth bit lines 1214 are shown disposed above third word lines 1212, and are arranged perpendicularly to third word lines 1212. Cross-sections of a plurality of fourth word lines 1216 are shown disposed above fourth bit lines 1214. A plurality of fifth bit lines 1218 are shown disposed above fourth word lines 1216, and are arranged perpendicularly to fourth word lines 1216. Various implementations in accordance with the present disclosure have this 8-stack arrangement of bit lines and word lines in common, but may have alternative placements of bit line decoders and/or word line decoders, and alternative contact structures for electrically coupling the bit lines and word lines to a corresponding bit line decoder or word line decoder.

In accordance with the present disclosure, to facilitate 3D PCM arrays achieving efficient area utilization, bit line contacts should connect with the bit lines of an array within an area defined by the 3D PCM array. Likewise, word line contacts should connect with the word lines of an array within the area defined by the 3D PCM array. In other words, neither the bit lines nor the word lines should extend outwardly from the array of PCM cells to provide room for the formation of contacts or contact structures.

In this illustrative implementation, as shown in Fig. 12A, the electrical path between the second bit lines and the bit line decoders on the first die passes through: (1) the level of the second PCM cell stack, (2) the level of first word lines 1204, (3) the level of the first PCM cell stack, (4) the level of first bit lines 1202, and (5) contacts at the same level as the bit line contacts of first bit lines 1202.

Still referring to the illustrative implementation of Fig. 12A, the electrical path between the third bit lines and the bit line decoders on the first die passes through: (1) the level of the fourth PCM cell stack, (2) the level of second word lines 1208, (3) the level of the third PCM cell stack, (4) the level of second bit lines 1206, (5) the level of the second PCM cell stack, (6) the level of first word lines 1204, (7) the level of the first PCM cell stack, (8) first bit lines 1202 (i.e., not just the level of first bit lines 1202) , and (9) bit line contacts of first bit lines 1202.

Still referring to the illustrative implementation of Fig. 12A, the electrical path between the fourth bit lines and the bit line decoders on the first die passes through: (1) the level of the sixth PCM cell stack, (2) the level of the third word lines 1212, (3) the level of fifth PCM cell stack, (4) the level of the third bit lines 1210, (5) the level of the fourth PCM cell stack, (6) the level of second word lines 1208, (7) the level of the third PCM cell stack, (8) the level of second bit lines 1206, (9) the level of the second PCM cell stack, (10) the level of first word lines 1204, (11) the level of the first PCM cell stack, (12) first bit lines 1202 (i.e., not just the level of first bit lines 1202) , and (13) bit line contacts of first bit lines 1202.

Still referring to the illustrative implementation of Fig. 12A, the electrical path between the fifth bit lines and the bit line decoders on the first die passes through: (1) the level of the eighth PCM cell stack, (2) the level of the fourth word lines 1216, (3) the level of the seventh PCM cell stack, (4) the level of the fourth bit lines, (5) the level of the sixth PCM cell stack, (6) the level of the third word lines 1212, (7) the level of fifth PCM cell stack, (8) the level of the third bit lines 1210, (9) the level of the fourth PCM cell stack, (10) the level of second word lines 1208, (11) the level of the third PCM cell stack, (12) the level of second bit lines 1206, (13) the level of the second PCM cell stack, (14) the level of first word lines 1204, (15) the level of the first PCM cell stack, (16) first bit lines 1202 (i.e., not just the level of first bit lines 1202) , and (17) bit line contacts of first bit lines 1202.

FIG. 12B is a cross-sectional representation, in the Y-direction, of an example implementation of an 8-stack 3D PCM array, showing the spatial relationship between the bit lines and word lines, together with the contact structures of this implementation of an 8-stack 3D PCM array. Like with FIG. 12A, for ease of understanding, the details of the first, second, third, fourth, fifth, sixth, seventh, and eighth PCM cell stacks are not shown in FIG. 12B.

Referring to FIG. 12B, cross-sections of the plurality of first bit lines 1202 are shown. The plurality of first word lines 1204 are disposed above first bit lines 1202, and are arranged perpendicularly to first bit lines 1202. Cross-sections of the plurality of second bit lines 1206 are shown disposed above first word lines 1204, and are arranged perpendicularly to first word lines 1204. A plurality of second word lines 1208 are shown disposed above second bit lines 1206. Second word lines 1208 are arranged perpendicularly to second bit lines 1206. Cross-sections of the plurality of third bit lines 1210 are shown disposed above second word lines 1208. Third bit lines 1210 are arranged perpendicularly to second word lines 1208. A plurality of third word lines 1212 are shown disposed above third bit lines 1210, and arranged perpendicular thereto. Cross-sections of the plurality of fourth bit lines 1214 are shown disposed above third word lines 1212.

In this illustrative implementation, as shown in FIG. 12B, an example of the electrical paths between the word line decoders and a word line is the electrical path between the word line decoders and second word lines 1208, which passes, at least, through: (1) the level of first bit lines 1202, (2) the level of the first PCM cell stack, (3) the level of the first word lines 1204, (4) the level of the second cell stack, (5) the level of the second bit lines 1206, and (6) the level of the third cell stack.

The alternative implementations shown in FIGs. 13A-14B share the same arrangement of bit lines, word lines, and cell stacks in their respective 3D PCM arrays as the illustrative implementation represented by FIGs. 12A-12B. The differences being the number and location of the bit line contacts and placement of the bit line and word line decoders as described above.

Some Implementations

In one illustrative implementation, a three-dimensional (3D) phase-change memory (PCM) , includes a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die. This illustrative implementation further includes a second die having at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die. The first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines. Each of the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines are electrically conductive, and each have an upper side and an underside. The first bit lines, second bit lines, third bit lines, fourth bit lines, and fifth bit lines, are coupled, by one or more bit line contacts, between their respective undersides and their associated bit line decoder on the first die. The first word lines and the second word lines are coupled, by one or more word line contacts, between their respective undersides and their associated word line decoder on the first die, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die. The first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other.

In some implementations, the first cell stack, the second cell stack, the third cell stack, the fourth cell stack, the fifth cell stack, the sixth cell stack, the seventh cell stack, and the eighth cell stack of each 3D PCM array, are each a two-dimensional array of 3D PCM cells.

In some implementations, each of the bit line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.

In some implementations, each of the word line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.

In some implementations, the second die has a pad-out dielectric layer disposed on a backside thereof, and the pad-out dielectric layer has a plurality of recesses therein.

Some implementations may further include a plurality of electrically conductive pads, wherein each one of the plurality of electrically conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad-out dielectric layer.

In some implementations, at least one pad of the plurality of electrically conductive pads is electrically coupled to one or more circuits on the second die by a through-silicon via.

In another illustrative implementation, a 3D PCM includes a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die. And also includes a second die having at least one bit line decoder, at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die. The first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines. The first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines each have an upper side and an underside. The first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other. The first bit lines, second bit lines, and third bit lines, are coupled between their respective undersides and their associated bit line decoder on the first die, by at least bit line contacts. The fourth bit lines and the fifth bit lines are coupled between their respective upper sides and their associated bit line decoder on the second die, by at least bit line contacts. The first word lines and the second word lines are coupled between their respective undersides and their associated word line decoder on the first die, by at least word line contacts, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die, by at least word line contacts.

Some implementations further include a plurality of electrically conductive pads, wherein each one of the plurality of electrically conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad-out dielectric layer.

In some implementations, at least one pad of the plurality of electrically conductive pads is electrically coupled to circuitry on the second die by a through-silicon via.

In yet another illustrative implementation, a 3D PCM includes a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die. And also includes a second die having at least bit line decoder, at least one word line decoder, and a second hybrid-bonding layer, where the second hybrid-bonding layer disposed on a top side of the second die. The first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines. The first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines each have an upper side and an underside. The first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other. In this illustrative implementation, the first bit lines, and second bit lines, are coupled between their respective undersides and their associated bit line decoder on the first die, by at least bit line contacts, the third bit lines, fourth bit lines and the fifth bit lines are coupled between their respective upper sides and their associated bit line decoder on the second die, by at least bit line contacts, the first word lines and the second word lines are coupled between their respective undersides and their associated word line decoder on the first die, by at least bit line contacts, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die, by at least word line contacts.

In some implementations, the second die has a pad-out dielectric layer disposed on a backside thereof, and the pad-out dielectric layer has a plurality of recesses therein. And, some implementations may further include a plurality of electrically conductive pads, wherein each one of the plurality of electrically conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad-out dielectric layer.

The foregoing description of the specific implementations will so reveal the general nature of the present disclosure that others can, by applying knowledge within the skill of the art, readily modify and/or adapt for various applications of such specific implementations, without undue experimentation, and without departing from the general concept of the present disclosure. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed implementations, based on the teaching and guidance presented herein. It is to be understood that the phraseology or terminology herein is for the purpose of description and not of limitation, such that the terminology or phraseology of the present specification is to be interpreted by the skilled artisan in light of the teachings and guidance.

Implementations of the present disclosure have been described above with the aid of functional building blocks illustrating the implementation of specified functions and relationships thereof. The boundaries of these functional building blocks have been arbitrarily defined herein for the convenience of the description. Alternate boundaries can be defined so long as the specified functions and relationships thereof are appropriately performed.

The Summary and Abstract sections may set forth one or more but not all implementations of the present disclosure as contemplated by the inventor (s) , and thus, are not intended to limit the present disclosure and the appended claims in any way.

The breadth and scope of the present disclosure should not be limited by any of the above-described illustrative implementations, but should be defined only in accordance with the subjoined claims and their equivalents.

Claims

A three-dimensional (3D) phase-change memory (PCM) , comprising:

a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die; and

a second die having at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die;

wherein the first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines;

wherein each of the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines have an upper side and an underside;

wherein the first bit lines, second bit lines, third bit lines, fourth bit lines, and fifth bit lines, are coupled, by one or more bit line contacts, between their respective undersides and their associated bit line decoder on the first die;

wherein the first word lines and the second word lines are coupled, by one or more word line contacts, between their respective undersides and their associated word line decoder on the first die, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die; and

wherein the first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other.
The 3D PCM of claim 1, wherein the first cell stack, the second cell stack, the third cell stack, the fourth cell stack, the fifth cell stack, the sixth cell stack, the seventh cell stack, and the eighth cell stack of each 3D PCM array, are each a two-dimensional array of 3D PCM cells.
The 3D PCM of claim 1, wherein each of the bit line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.
The 3D PCM of claim 1, wherein each of the word line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.
The 3D PCM of claim 1, wherein the second die has a pad-out dielectric layer disposed on a backside thereof, and the pad-out dielectric layer has a plurality of recesses therein.
The 3D PCM of claim 5, further comprising:

a plurality of electrically conductive pads, wherein each one of the plurality of electrically conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad-out dielectric layer.
The 3D PCM of claim 6, wherein at least one pad of the plurality of electrically conductive pads is electrically coupled to one or more circuits on the second die by a through-silicon via.
A three-dimensional (3D) phase-change memory (PCM) , comprising:

a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die; and

a second die having at least one bit line decoder, at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die;

wherein the first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines;

wherein the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines each have an upper side and an underside;

wherein the first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other;

wherein the first bit lines, second bit lines, and third bit lines, are coupled between their respective undersides and their associated bit line decoder on the first die, by at least bit line contacts;

wherein the fourth bit lines and the fifth bit lines are coupled between their respective upper sides and their associated bit line decoder on the second die, by at least bit line contacts; and

wherein the first word lines and the second word lines are coupled between their respective undersides and their associated word line decoder on the first die, by at least word line contacts, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die, by at least word line contacts.
The 3D PCM of claim 8, wherein the first cell stack, the second cell stack, the third cell stack, the fourth cell stack, the fifth cell stack, the sixth cell stack, the seventh cell stack, and the eighth cell stack of each 3D PCM array, are each a two-dimensional array of 3D PCM cells.
The 3D PCM of claim 8, wherein each of the bit line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.
The 3D PCM of claim 10, wherein each of the word line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.
The 3D PCM of claim 8, wherein the second die has a pad-out dielectric layer disposed on a backside thereof, and the pad-out dielectric layer has a plurality of recesses therein.
The 3D PCM of claim 12, further comprising:

a plurality of electrically conductive pads, wherein each one of the plurality of electrically conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad-out dielectric layer.
The 3D PCM of claim 6, wherein at least one pad of the plurality of electrically conductive pads is electrically coupled to circuitry on the second die by a through-silicon via.
A three-dimensional (3D) phase-change memory (PCM) , comprising:

a first die having a plurality of 3D PCM arrays, each 3D PCM array having a first cell stack, a second cell stack above the first cell stack, a third cell stack above the second cell stack, a fourth cell stack above the third cell stack, a fifth cell stack above the fourth cell stack, a sixth cell stack above the fifth cell stack, a seventh cell stack above the sixth cell stack, an eighth cell stack above the seventh cell stack, at least one bit line decoder, at least one word line decoder, and a first hybrid-bonding layer, the first hybrid-bonding layer disposed on a top side of the first die; and

a second die having at least bit line decoder, at least one word line decoder, and a second hybrid-bonding layer, the second hybrid-bonding layer disposed on a top side of the second die;

wherein the first cell stack of each 3D PCM array is disposed between a plurality of first bit lines and a plurality of first word lines, the second cell stack of each 3D PCM array is disposed between the plurality of first word lines and a plurality of second bit lines, the third cell stack of each 3D PCM array is disposed between the plurality of second bit lines, and a plurality of second word lines, the fourth cell stack of each 3D PCM array is disposed between the plurality of second word lines, and a plurality of third bit lines, the fifth cell stack of each 3D PCM array is disposed between the plurality of third bit lines and a plurality of third word lines, the sixth cell stack of each 3D PCM array is disposed between the plurality of third word lines and a plurality of fourth bit lines, the seventh cell stack of each 3D PCM array is disposed between the plurality of fourth bit lines and a plurality of fourth word lines, and the eighth cell stack of each 3D PCM array is disposed between the plurality of fourth word lines and a plurality of fifth bit lines;

wherein the first bit lines, second bit lines, third bit lines, fourth bit lines, fifth bit lines, first word lines, second word lines, third word lines, and fourth word lines each have an upper side and an underside;

wherein the first die and the second die are hybrid-bonded to each other in a face-to-face orientation such that at least a portion of a plurality of first hybrid-bonding contacts and at least a portion of a plurality of second hybrid-bonding contacts are electrically connected to each other;

wherein the first bit lines, second bit lines, and third bit lines, are coupled between their respective undersides and their associated bit line decoder on the first die, by at least bit line contacts;

wherein the fourth bit lines and the fifth bit lines are coupled between their respective upper sides and their associated bit line decoder on the second die, by at least bit line contacts;

wherein the first word lines and the second word lines are coupled between their respective undersides and their associated word line decoder on the first die, by at least bit line contacts, and the third word lines and the fourth word lines are coupled between their respective upper sides and their associated word line decoder on the second die, by at least word line contacts.
The 3D PCM of claim 15, wherein the first cell stack, the second cell stack, the third cell stack, the fourth cell stack, the fifth cell stack, the sixth cell stack, the seventh cell stack, and the eighth cell stack of each 3D PCM array, are each a two-dimensional array of 3D PCM cells.
The 3D PCM of claim 15, wherein each of the bit line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.
The 3D PCM of claim 17, wherein each of the word line contacts associated, respectively, with each 3D PCM array, are located within an area defined by the respective 3D PCM array.
The 3D PCM of claim 15, wherein the second die has a pad-out dielectric layer disposed on a backside thereof, and the pad-out dielectric layer has a plurality of recesses therein.
The 3D PCM of claim 19, further comprising:

a plurality of electrically conductive pads, wherein each one of the plurality of electrically conductive pads is disposed within a corresponding recess of the plurality of recesses in the pad-out dielectric layer.