CN112368771A

CN112368771A - Method for reducing thermal crosstalk in 3D cross-point memory arrays using lamination gap filling

Info

Publication number: CN112368771A
Application number: CN202080002919.8A
Authority: CN
Inventors: 刘峻
Original assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Current assignee: Yangtze River Advanced Storage Industry Innovation Center Co Ltd
Priority date: 2020-10-10
Filing date: 2020-10-10
Publication date: 2021-02-12
Anticipated expiration: 2040-10-10
Also published as: WO2022073221A1; CN112368771B

Abstract

Systems, methods, and apparatus are described that are capable of reducing the amount of thermal crosstalk between cells in a three-dimensional array of memory cells through the use of a laminate material, which in turn allows for smaller scaled fabrication of memory cells.

Description

Method for reducing thermal crosstalk in 3D cross-point memory arrays using lamination gap filling

Technical Field

The present disclosure relates generally to three-dimensional electronic memories. More particularly, the present disclosure relates to the use of laminates in the geometry of three-dimensional memory arrays to increase certain characteristics or properties of the memory array or to reduce undesirable characteristics in the memory array.

Background

Planar memory cells are scaled to smaller dimensions by improving process technology, circuit design, programming algorithms, and manufacturing processes. However, as the feature size of the memory cell approaches the lower limit, the planar processes and fabrication techniques become challenging and expensive. Therefore, the memory density of the planar memory cell approaches the upper limit. Three-dimensional (3D) memory architectures can address the density limitations of planar memory cells.

Disclosure of Invention

In creating the techniques of the present invention, it has been recognized that while three-dimensional (3D or 3-D) memory architectures can address the density limitations of planar memory cells, 3D configurations can present new technical challenges. Other technical problems arise as the desired features of 3D memory architectures are pursued (e.g., increased density of 3D cells, or reduction in the fabrication size of the cells).

One example of such a problem is thermal cross-talk between cells. Thermal crosstalk occurs when heat generated from one point or cell within a 3D cell array is transferred to an adjacent cell at another point or cell. During operation of a 3D memory architecture, heat generated from one cell can disturb the normal or desired operation of the cell. The problems due to thermal cross-talk between cells become more and more pronounced as the cell size decreases. Because of the smaller inter-cell distance, smaller spacing or scaling when creating a 3D memory architecture increases the amount or speed of heat transfer between one cell and another. Due to thermal crosstalk, the ability to scale to smaller sizes while still having a functional 3D memory array is compromised.

Accordingly, there is a need for methods, systems, and devices that can overcome conventional methods of creating 3D memory arrays and allow scaling of 3D memory arrays while making them operable despite thermal crosstalk.

In one embodiment of the present technology, a three-dimensional memory includes: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer that three-dimensionally and at least partially encapsulates the first memory cell, the second memory cell, and the electrode such that the first memory cell and the second memory cell are exposed on at least one surface. In some exemplary embodiments, the electrodes and/or the memory cells may be vertically arranged, and in other exemplary embodiments, the electrodes and/or the memory cells may be horizontally arranged. In some examples, combinations of orientations are possible.

Other embodiments of the present technology may include, for example, any combination of: a first storage unit; a second storage unit; an electrode electrically connecting the first memory cell and the second memory cell; an intra-cell space between the first storage unit and the second storage unit; a first layer that three-dimensionally and at least partially encapsulates the first memory cell, the second memory cell, and the electrode; configuring the first storage unit and the second storage unit to be exposed on at least one surface; depositing a first layer using a chemical vapor deposition process; depositing a first layer using an atomic deposition method; a second layer at least partially and three-dimensionally surrounding the first layer; a plurality of additional layers, wherein the plurality of layers completely occupy the intra-cellular space; forming the first layer, the second layer, or the additional layer from a dielectric material; selecting the dielectric material from NiTi (NIT), tungsten (W), Ovonic Threshold Switch (OTS), Phase Change Memory (PCM) or a _ C; forming the first layer and the second layer from different materials; the first and second layers are constructed of materials selected to maximize heat reflection values.

For example, other embodiments of the invention include methods that may include, for example, any combination of: providing a first storage unit; providing a second storage unit; providing an electrode electrically connecting the first memory cell and the second memory cell; creating a first layer that three-dimensionally encapsulates the first memory cell, the second memory cell, and the electrode; exposing the first and second memory cells on at least one surface; creating a second layer that at least partially and three-dimensionally surrounds the first layer; creating a plurality of layers such that the plurality of layers partially occupy the intra-cell space; creating a plurality of layers such that the plurality of layers completely occupy the intra-cellular space; removing material within the intra-cell space beyond a top of the first storage cell or the second storage cell; adding an electrode substantially over a surface exposed by removing material beyond a top of the first memory cell or the second memory cell.

Drawings

The foregoing aspects, features and advantages of the disclosure will be further understood when considered in conjunction with the following description of exemplary embodiments and the accompanying drawings, in which like reference numerals refer to like elements. In describing exemplary embodiments of the present disclosure illustrated in the drawings, specific terminology may be employed for the sake of clarity. However, aspects of the disclosure are not intended to be limited to the specific terminology used.

FIG. 1 is an isometric view of a portion of a three-dimensional cross-point memory of the prior art.

Figure 2 is a plan view of a portion of a three-dimensional cross-point memory of the prior art.

Fig. 3A, 3B, and 3C are cross-sectional views of portions of a three-dimensional crosspoint memory and an energy grid created by the memory of an embodiment.

Fig. 4 is a graph showing a relationship between the disturbance current and the resistance of the memory cell.

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sections of a three-dimensional cross-point memory according to an embodiment of the invention.

Fig. 6 depicts a method according to an exemplary embodiment of the present disclosure.

Detailed Description

Heat transfer occurs through three major physical phenomena, convection, conduction, and radiation. Radiation is a method of energy transfer that does not rely on any contact between the heat source and the heated object. Conduction, on the other hand, is the transfer of heat between substances that are in direct contact with each other. The conductivity between objects in contact with each other depends on the specific physical properties of these objects. For example, conduction through an object depends on the thermal resistance of the material constituting the object. In the circuit, heat transfer may occur through any of these phenomena.

Conduction can also be conceptualized as occurring through phonons. Phonons are collective excitations in the periodic elastic arrangement of matter. Phonons are quasi-particles that can represent the vibrational characteristics of a material or various vibrational modes of an elastic material, and also describe the interaction of interacting particles of the elastic material. Heat in dielectric materials and semiconductors is transmitted primarily through phonons.

When an object is composed of more than one material, the overall thermal resistance of the material may be considered to be composed of the thermal resistances of the constituent materials. However, the presence of more than one material within a system or object creates a thermal boundary resistance between these materials. Phonons may also undergo scattering in materials by interacting with defects, other phonons, grain boundaries, different isotopes in the material, and various other physical causes. Temperature discontinuities occur in the area where two materials interface when heat passes through the interface between the two materials (i.e., when phonons move from one material to the other). The thermal resistance boundary is also referred to as the interfacial thermal resistance or Kapitza resistance, which is a measure of the resistance of the interface to heat flow. Thermal resistance boundaries are also defined as the ratio of the temperature discontinuity at an interface to the heat flux flowing through the interface, and are caused by strong phonon reflections as phonons attempt to pass through the interface of one material with another. When a phonon moves from one material to another (such as, for example, from material a to material B), a portion of the phonon energy is reflected back to material a (i.e., reflected) and some energy is conducted to material B (i.e., conducted).

A higher thermal resistance boundary can be designed by selecting the materials that make up the object, or by creating an additional boundary through which phonons must pass. A higher thermal resistance boundary may slow the rate at which heat is transferred by conduction. In addition, by having several materials in the proper configuration, many boundaries can be created through which phonons must pass.

The present technology is directed to solving problems associated with heat transfer in three-dimensional memories. A general example of a three-dimensional (3D) memory is shown in fig. 1. Specifically, FIG. 1 is an isometric view of a portion of a three-dimensional cross-point memory. The memory comprises a first layer of memory cells 5 and a second layer of memory cells 10. Between the first-level memory cells 5 and the second-level memory cells 10 are a plurality of word lines 15 extending in the horizontal (X) direction. Above the first-layer memory cells 5 in the depth (Z) direction are a plurality of first bit lines 20 extending in the vertical (Y) direction, and below the second-layer memory cells 10 are a plurality of second bit lines 25 extending in the Y direction.

As also shown in fig. 1, the sequential structure of bit lines, memory cells, word lines, memory cells may be repeated in the Z-direction to create a stacked configuration. In the example of fig. 1, the first-tier stack may include first-tier memory cells 5, bit lines 20, and word lines 15, and the second-tier stack may include second-tier memory cells 10, bit lines 25, and word lines 15. Thus, although the first tier memory cells 5 and the second tier memory cells 10 each have their respective set of

bit lines

20 and 25, the first tier memory cells 5 and the second tier memory cells 10 may share the same set of word lines 15. Although the example of fig. 1 shows a 4-layer stacked configuration, in other examples, the stacked configuration may include any number of memory cell layers and other elements. In any case, an individual memory cell in the structure can be accessed by selectively activating the word line and bit line corresponding to that cell.

To selectively activate the word lines and bit lines, the memory includes word line decoders and bit line decoders (not shown). The word line decoder is coupled to the word lines by word line contacts (not shown) and is used to decode word line addresses so that a particular word line is activated when that word line is addressed. Similarly, a bit line decoder is coupled to the bit lines through bit line contacts (not shown) and is used to decode the bit line address so that a particular bit line is activated when addressed. Thus, the stacked configuration of the memory may also include bit line contacts and decoders, and word line contacts and decoders for selectively activating bit lines and word lines in the stack. For example, the stacked configuration may be arranged as an array of elements, where each array includes a set of memory cells, and corresponding sets of bit lines, word lines, bit line and word line contacts, and bit line and word line decoders. The word line decoders and contacts, and the positioning of the bit line decoders and contacts are shown and discussed further with reference to FIG. 2.

Fig. 2 is a plan view of a portion of a three-dimensional cross-point memory of a prior configuration. The figure depicts the portion as viewed in the Z (depth) direction. In this example, the stacking configuration is a 2-layer stack. The stacked configuration includes multiple arrays of memory cells, including two

top cell arrays

60 and 61 and two

bottom cell arrays

65 and 66. Although individual memory cells are not shown in fig. 2, they are shown by fig. 1, for example, in a top array, the memory cells may be arranged as the first layer memory cells 5 shown in fig. 1, and in a bottom array, the memory cells may be arranged as the second layer memory cells 10 shown in fig. 1.

The portion includes word and bit lines, word and bit line contacts, and word and bit line decoders corresponding to the top and bottom cells. As shown, a plurality of word lines (e.g., word line 30) extend in the X (horizontal) direction and correspond to both the top and bottom cells. The portion also includes a plurality of top cell bit lines (e.g., bit lines 35) extending in the Y (vertical) direction and corresponding to the top cell array 60 of memory cells, and a plurality of bottom cell bit lines (e.g., bit lines 40) extending in the vertical direction and corresponding to the bottom cell array 65 of memory cells. The word lines, top cell bit lines, and bottom cell bit lines are typically formed from a 20nm/20nm line/space (L/S) pattern and are formed on a silicon substrate. Further, the memory may employ Complementary Metal Oxide Semiconductor (CMOS) technology.

The word lines in fig. 2 are horizontally aligned for a given cell array. For example, as shown, word lines of the

cell arrays

60, 61, 65, and 66 are all horizontally aligned with each other along the X-direction. Each of these word lines is shown extending across the entire width of the respective cell array. The top cell bit lines of a given top cell array or the bottom cell bit lines of a given bottom cell array are vertically aligned. For example, the top cell bit line 35 is vertically aligned along the Y-direction, and the bottom cell bit line 40 is vertically aligned along the Y-direction. The top cell bit lines of the top cell array and the bottom cell bit lines of the overlapping bottom cell array (e.g., top cell bit line 35 and bottom cell bit line 40) are also horizontally aligned with each other, although they are shown slightly offset in fig. 2 to clearly illustrate the two layers. Each of these bit lines is shown extending across the entire length of the respective cell array.

The memory portion of fig. 2 includes a word line contact region 45, a top cell bit line contact region 50, and a bottom cell bit line contact region 55. The word line contact region 45 is elongated in the vertical direction while the top cell bit line contact region 50 and the bottom cell contact region 55 are elongated in the horizontal direction. The word line contact area 45 includes a plurality of word line contacts (e.g., contacts 45a), which are shown as dots surrounded by the word line contact area 45. The top cell bit line contact region 50 includes a plurality of word line contacts (e.g., contacts 50a) that are shown as points surrounded by the top cell bit line contact region 50. The bottom cell bit line contact region 55 includes a plurality of bottom cell bit line contacts (e.g., contacts 55a) that are shown as dots surrounded by the bottom cell bit line contact region 55.

The word line contacts and bit line contacts are connected to the middle of the respective word lines and bit lines. Thus, as shown, word line contact region 45 is located in the horizontal middle of word line 40, bottom cell bit line contact region 55 is located in the vertical middle of bottom cell bit line 40, and top cell bit line contact region 50 is located in the vertical middle of top cell bit line 35. Since the word lines of a given cell array are horizontally aligned, the word line contacts of the given cell array are also substantially aligned in the horizontal direction. Similarly, since the bit lines of a given cell array are vertically aligned, the bit line contacts of the given cell array are also substantially aligned in the vertical direction.

The word line contact region 45 also includes a plurality of word line decoders (not shown). The word line decoder generally conforms to the word line contact area and generally extends in a vertical direction. The word line decoder is coupled to a word line through a word line contact. The top cell bit line contact region 50 also includes a plurality of top cell bit line decoders (not shown). The top cell bit line decoder generally conforms to the top cell bit line contact region 50 and generally extends in a horizontal direction. A top cell bitline decoder is coupled to the top cell bitline through a top cell bitline contact. The bottom cell bit line contact region 55 also includes a plurality of bottom cell bit line decoders (not shown). The bottom cell bit line decoder generally conforms to the bottom cell bit line contact region 55 and generally extends in a horizontal direction. The bottom cell bit line decoder is coupled to the bottom cell bit line through a bottom cell bit line contact.

As can be seen from fig. 1, the prior art memory does not contain any material for preventing heat transfer between one cell and the next. Methods and systems capable of preventing heat transfer between storage units without interfering with memory operations are described below.

Referring to fig. 3A, 3B and 3C, thermal crosstalk can be observed between an active or perturbing cell (through which current is passed) and an inactive or perturbed cell. Although fig. 3A, 3B, and 3C are represented in two dimensions, they represent physical phenomena occurring in three dimensions.

Fig. 3A shows an active cell 305 (also referred to as a scrambling cell 305) and an inactive or disturbed cell 310, where the distance between the 3D cells is approximately 90 nanometers. During normal operation of the memory cell, the scrambling unit 305 generates heat when current is passed through the scrambling unit 305. The heat generated by scrambling unit 305 is represented by field 315. The field 315 may represent a gradient or distribution of temperature. That is, the field 315 may represent a particular temperature at a particular physical space by mapping the space to a color that represents the temperature of the space. Alternatively, the field 315 may also be delineated by the proximity or density of lines to represent higher or lower temperatures at particular regions. Although field 315 is viewed in two dimensions in FIG. 3A, field 315 may be three-dimensional and extend outward from within perturbing cell 305 to a space surrounding cell 305. As can be seen in fig. 3A, heat generated from the scrambling from scrambling unit 305 is conducted across the intra-cell gap 320 to the victim unit 310.

Fig. 3B is a 45 nm anisotropy visualization of the heat transfer and temperature gradient generated by the perturbing unit. Fig. 3B shows a 3D cell structure scaled to a smaller pitch than fig. 3A. Compared to fig. 3A, the intra-cell distance between the disrupting unit and the disturbed unit is reduced, and, in turn, both the heat transferred to the disturbed unit and the temperature of the disturbed unit are increased. Thus, the reduced cell spacing and the increase in thermal effects to the victim cell (e.g., jammer cell 330) affect the operational properties of victim cell 340. The field 350 may represent a particular temperature at a particular physical space with the particular physical space mapped to a color gradient. As shown in fig. 3B, scrambling unit 330 affects victim unit 340 differently at different locations of victim unit 340. In fig. 3B, the disturbed cell 340 has a higher heat at one end of the cell than at the other end. This unequal distribution of temperature can affect the normal operation of the disturbed unit 340. For example, the expected resistance of the victim unit 340 may be unequal across the victim unit due to the heat.

Fig. 3C is a 45 nm isotropic visualization of the heat transfer and temperature gradient generated by the disrupting elements. An isotropic view is a view that treats all directions equally. Isotropic heat transfer occurs when heat is transferred at the same rate in all directions.

As can be seen from fig. 3A-3C, as the intra-cell distance is reduced, more heat is transferred between the cells. Further complicating this problem in three-dimensional memories is that, because the memory is stacked upon one another, the surface area and space from which heat is dissipated is reduced as compared to conventional substantially two-dimensional memories (in which heat can be dissipated to the ambient environment at a faster rate). For example, heat will not be removed quickly and efficiently from the intermediate memory layers of the three-dimensional memory as compared to a planar memory configuration. In addition, heat moving from one cell in the three-dimensional memory will propagate in all directions, heating all nearby cells.

Fig. 4 is a visual representation of the amount of current passing through a scrambling cell (e.g., scrambling cell 405) and the resistance of a victim cell (e.g., victim cell 410). FIG. 4 also shows a first word line 415, a second word line 420, a first bit line 425, and a second bit line 430. Current may pass through the word line and bit line, such as reset pulse 435. As can be seen from fig. 4, the victim cell resistance varies as a function of the current in the aggressor cell. The changing resistance of the victim unit can interfere with the normal operation of the victim unit. Fig. 4 shows that the resistance of the victim cell can change by an order of magnitude of 10 based on the increased current in the aggressor cell. The change in resistance of the victim unit (e.g., victim unit 410) occurs at least in part due to thermal energy generated by the jammer unit (e.g., jammer unit 405).

Fig. 5A, 5B, 5C, 5D, 5E, and 5F are cross-sectional views of a three-dimensional cross-point memory according to an embodiment of the invention. Fig. 5A shows a memory cell formed by deposition or stacking of materials. As can be seen in fig. 5A,

cells

510 and 520 are formed of similar materials and thus form parallel lines within the cell stack when viewed in two dimensions. Although not shown in fig. 5A, other components (such as those described above or known in the art) may be included in various configurations or combined with cells to implement an operable 3D cross-point memory.

Cells

510 and 520 may be created or stacked on an electrode (e.g., electrode 501).

Cells

510 and 520 may be made of various materials or elements, such as W, a-C, an Ovonic Threshold Switch (OTS), or PCM. For example,

cells

510 and 520 may be made up of several layers, such as, for example, layers 502, 503, 504, 505, and 506, which in turn may be made of elements such as W, a-C, an Ovonic Threshold Switch (OTS), or PCM.

Fig. 5B illustrates the formation of a first thin niti (nit) encapsulation layer around the memory cell stack shown in fig. 5A. NIT is a commercially available alloy such as, for example, NIT 135. Any suitable material may be used to form the first layer 530. The first layer 530 may also be made of any suitable dielectric material. The dielectric material is selected to ensure that currents in the memory (e.g., cells 510 and 520) are not carried to undesired paths outside of those cells. Forming the first layer around the memory stack may be accomplished by a conformal coating technique. Conformal coating techniques provide technical advantages such as consistency of the coated material. However, the first layer may be formed around the memory stack using any suitable technique. In an exemplary embodiment, techniques such as Atomic Layer Deposition (ALD) may be used. Atomic layer deposition is a thin film deposition technique based on the sequential use of vapor deposition processes. Other variations of ALD techniques may be used to deposit the first thin layer.

Fig. 5C shows the formation of a second thin layer 540 around the first thin layer 530. The second thin layer 540 may be deposited by any suitable method, for example by using atomic layer deposition. However, any suitable deposition technique may be used. Layer 540 may be created from any suitable material, such as, but not limited to, silicon dioxide.

Fig. 5D shows the formation of additional layers, such as, for example, layers 541, 542, 543, 544, 545, and 546, around the second thin layer. Each layer may be added sequentially to a previous layer (e.g., layer 544 may be added after layer 543 is added). Layers 540-546 may be created from any suitable material, including but not limited to silicon dioxide, NIT, SiC, and the like. In some examples, the layers may be made of different materials, while in other examples, some layers may be made of the same material. Any suitable dielectric material may be selected to form each layer. Suitable materials will be able to resist deformation at the operating temperature and current of the cell while retaining suitable characteristics (e.g., appropriate thermal boundary resistance) to increase thermal isolation of the cell. It is also possible to select pairs of materials with high thermal boundary resistance. Each layer may be configured to be selectively thick. For example, each layer may be configured to be only a few atoms thick. The process of adding additional layers may continue until the space within the cell, such as the space between

cells

510 and 520, is filled. The material used may be, for example, a dielectric material. However, there may be a small gap between the last layers (such as, for example, layers 545 and 546).

By adding each layer (such as, for example, adding layer 545 after layer 544 has been formed), additional interfaces or thermal boundaries are created. Thus, at least as many thermal boundaries as the number of layers added can be created. By designing the number of layers added and selecting materials that produce a larger thermal resistance boundary, each cell can be more effectively thermally isolated from the surrounding cells. At smaller sizes, and as the intra-cell gap decreases, heat transfers more rapidly between cells. Thus, the additional thermal isolation allows scaling of the fabrication of the memory cells to each smaller size.

In addition, additional mechanical benefits may be realized by filling the intra-cell gap with a laminate material using layers (e.g., layers 541-546). For example, the addition of a laminate material may provide better mechanical support during the cell and 3D cross-point memory array fabrication process.

As shown in the figures, the deposition of the material is done in a vertical line patterning, i.e. each layer is deposited substantially parallel to the surface in front of the layer. For example, layer 530 is substantially parallel to the surfaces of electrode 501, cell 510, and cell 520. Thereby creating layer 540 substantially parallel to layer 530. The layers may appear to form a substantially 90 degree angle at the tip when viewed in cross-sectional view.

Fig. 5E shows the cell stack after additional layers are formed and portions of the layers (e.g., layers 541-546) are selectively removed. In an exemplary embodiment, portions of the layers (e.g., layers 541 and 546) that are present or otherwise extend beyond the length of any cell (e.g., cell 510 or cell 520) may be removed so that the layers do not extend beyond the length of any cell. In other words, the layers (e.g., layers 541-546) are made flush with the cell (e.g., cell 510 or cell 520). Any suitable process for removing material located beyond the length of a cell (e.g., cell 510 or cell 520) may be used. One example of such a process is the use of chemical mechanical polishing or planarization. Chemical mechanical polishing is a process that combines mechanical and chemical forces. Removing material in a planar manner is suitable for removing excess material from layers, such as layers 541-546. However, other suitable processes may be used to remove the excess material, such as, for example, shallow trench isolation. Therefore, materials must be selected for both processes.

Fig. 5F shows the cell stack after the above removal process, and another electrode is added to form the next stack of memory cells. The additional electrode 590 is added flush with the existing cells (e.g., cells 510 and 520) and additional layers (e.g., layers 541-546) that fill the space within the cells. The next electrode (e.g., electrode 590) may be added parallel or perpendicular to the existing electrode (501).

The process described in fig. 5A-5F may be repeated again to create a stacked memory cell containing an intra-cell material layer. By stacking the electrodes, isolated memory cell pillars can be formed. By repeating the process described in fig. 5A-5F, each memory cell formed is thermally isolated from other memory cells within the memory cell stack.

One advantage of memory cells created as described above is reduced thermal cross-talk between cells. By increasing the thermal boundary resistance and creating multiple layers, thermal cross talk is reduced. Furthermore, by filling the gaps, additional mechanical support is provided to the entire three-dimensional memory structure, which is beneficial for reducing the fabricated dimensions to smaller pitches and for subsequent processing of the memory.

FIG. 6 depicts a method (method 600) according to an exemplary embodiment of the present disclosure. The method starts at step 610. In step 610, a memory cell may be formed by stacked deposition on a substrate. The substrate may be a conductive material, such as an electrode. The memory cell may be formed by any suitable method, such as for example by atomic layer deposition. The memory cell may be formed to have an intra-cell gap. In step 620, a first layer may be formed over the memory cells. A first layer may be formed in three dimensions to surround and encapsulate the memory cells. The first layer may be formed of any suitable material, such as, for example, a dielectric material. In step 630, a second layer is deposited on top of and encapsulates the first layer. The second layer may be composed of any suitable material or combination of materials and deposited by any suitable method. In step 640, additional layers may be deposited to encapsulate the second layer. Additional layers may be added as needed to fill in the intra-cell gaps between memory cells. Each additional layer encapsulates a previous layer. The addition of each layer may occur in three dimensions. In step 650, material located beyond the intra-cell gap and atop the cell may be removed by any suitable technique. Material may be removed in a manner that allows a substantially flat and continuous surface to be created between the cells and the layers added in steps 610-650. In step 660, a substrate may be added where material was removed. In step 670, steps 610-660 may be repeated as desired. The method ends at step 680.

Most of the foregoing alternatives are not mutually exclusive, but can be implemented in various combinations to achieve unique advantages. As these and other variations and combinations of the features discussed above can be utilized without departing from the subject matter defined by the claims, the foregoing description of the embodiments should be taken by way of illustration rather than by way of limitation of the subject matter defined by the claims. For example, the foregoing operations need not be performed in the exact order described above. Rather, the various steps may be processed in a different order, such as an inverted order or concurrently. Steps may also be omitted unless otherwise noted. In addition, the provision of the examples described herein, as well as clauses phrased as "such as," "including," and the like, should not be interpreted as limiting the subject matter of the claims to the specific examples; rather, these examples are intended to illustrate only one of many possible embodiments. Moreover, the same reference numbers in different drawings may identify the same or similar elements.

Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A three-dimensional memory, comprising:

a first storage unit;

a second storage unit;

an electrode electrically connecting the first memory cell and the second memory cell;

an intra-cell space between the first storage unit and the second storage unit; and

a first layer that three-dimensionally, at least partially encapsulates the first memory cell, the second memory cell, and the electrode,

wherein the first and second storage units are configured to be exposed on at least one surface.

2. The three-dimensional memory of claim 1, wherein the first layer is deposited using a chemical vapor deposition method.

3. The three-dimensional memory of claim 1, wherein the first layer is deposited using an atomic deposition method.

4. The three-dimensional memory of claim 1, further comprising a second layer at least partially and three-dimensionally surrounding the first layer.

5. The three-dimensional memory of claim 4, further comprising at least one additional layer.

6. The three-dimensional memory of claim 5, further comprising a plurality of additional layers, wherein the plurality of additional layers occupy the entire intra-cell space.

7. The three-dimensional memory of claim 5, wherein the first layer, the second layer, and the at least one additional layer are comprised of a dielectric material.

8. The three-dimensional memory of claim 7, wherein the dielectric material is selected from NiTi, a _ C, PCM, OTS, or W.

9. The three-dimensional memory of claim 2, wherein the first layer and the second layer are comprised of different materials.

10. The three-dimensional memory of claim 2, wherein the first layer and the second layer are comprised of a dielectric material.

11. A three-dimensional memory, comprising:

a top cell array of memory cells;

a bottom cell array of memory cells;

at least one electrode electrically connected to at least one of the top array of memory cells or the bottom array of memory cells; and

an in-memory space between the memory cells, wherein the in-memory space is filled with a plurality of layers that create a plurality of in-material interfaces.

12. The three-dimensional memory of claim 11, wherein the in-memory space is partially filled.

13. The three-dimensional memory of claim 11, wherein the in-memory space is completely filled.

14. A method of forming a three-dimensional memory, comprising:

providing a first storage unit;

providing a second storage unit;

providing an electrode electrically connecting the first memory cell and the second memory cell;

creating a first layer that three-dimensionally encapsulates the first memory cell, the second memory cell, and the electrode; and

exposing the first memory cell and the second memory cell on at least one surface.

15. The method of claim 14, further comprising the steps of:

creating a second layer that at least partially and three-dimensionally surrounds the first layer.

16. The method of claim 15, further comprising the steps of:

a plurality of layers is created such that the plurality of layers partially occupy a space within a cell.

17. The method of claim 16, further comprising the steps of:

creating a plurality of layers such that the plurality of layers completely occupy the intra-cellular space.

18. The method of claim 17, further comprising the steps of:

removing material between the intra-cell spaces beyond a top of the first storage cell or the second storage cell.

19. The method of claim 18, further comprising the steps of:

adding an electrode substantially over a surface exposed by removing material beyond a top of the first memory cell or the second memory cell.