CN1324686C - Method of making semiconductor components - Google Patents
Method of making semiconductor components Download PDFInfo
- Publication number
- CN1324686C CN1324686C CNB031024718A CN03102471A CN1324686C CN 1324686 C CN1324686 C CN 1324686C CN B031024718 A CNB031024718 A CN B031024718A CN 03102471 A CN03102471 A CN 03102471A CN 1324686 C CN1324686 C CN 1324686C
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- dielectric layer
- substrate
- semiconductor element
- those
- manufacture method
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 28
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 239000000463 material Substances 0.000 claims abstract description 24
- 238000000034 method Methods 0.000 claims description 67
- 230000004888 barrier function Effects 0.000 claims description 19
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- 238000004518 low pressure chemical vapour deposition Methods 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 4
- 229910052796 boron Inorganic materials 0.000 claims description 4
- 239000005360 phosphosilicate glass Substances 0.000 claims description 4
- 238000002955 isolation Methods 0.000 abstract description 3
- 239000010410 layer Substances 0.000 description 86
- 239000003990 capacitor Substances 0.000 description 5
- 229910052814 silicon oxide Inorganic materials 0.000 description 5
- 230000005669 field effect Effects 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 239000000377 silicon dioxide Substances 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- ZOBHHDKCHRGRRX-UHFFFAOYSA-N [B].OP(O)(O)=O Chemical compound [B].OP(O)(O)=O ZOBHHDKCHRGRRX-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007943 implant Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 230000007935 neutral effect Effects 0.000 description 2
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000008034 disappearance Effects 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Memories (AREA)
Abstract
The present invention relates to a method of making a semiconductor component, which comprises: after a first dielectric layer is formed on a substrate where a grid structure is formed, the first dielectric layer is etched, and a gap wall is formed on the side wall of the grid structure; subsequently, a source/drain region is formed on the substrate at both sides of the gap wall, and a second dielectric layer is formed on the substrate, wherein the material of the second dielectric layer is the same as that of the first dielectric layer. Because the material of the first dielectric layer and that of the second dielectric layer are the same, the first dielectric layer does not need to be removed, and the second dielectric layer can be directly formed. Thus, the problem of hole production in an isolation region when the first dielectric layer is removed can be prevented.
Description
Technical field
The invention relates to a kind of manufacture method of semiconductor element, and the method for particularly being damaged relevant for a kind of shallow-channel isolation region that prevents dynamic random access memory.
Background technology
Dynamic random access memory is to utilize the electrically charged and neutral of capacitors a large amount of in the substrate to store binary data.A capacitor is represented a bank bit, the state of representing capacitor " electrically charged " or " neutral " respectively for binary data " 0 " or " 1 " of its storage.By shifting field-effect transistor, the action of read/write can be done among the DRAM, the source electrode that wherein shifts field-effect transistor and bit line (Bite Line BL) connects, and its drain electrode is connected with capacitor, and its grid and character line (Word Line, WL) connection.Via shifting field-effect transistor, bit line feeds a voltage and makes capacitor electrically charged thus, and shifts field-effect transistor and selectively control it with character line and become initiatively or passive, so just finishes the action that writes.
The leading portion manufacturing process of common dynamic random access memory is shown in Figure 1A to Fig. 1 D.At first, please refer to Figure 1A, one substrate 100 is provided, substrate 100 has a memory cell areas 130 and a periphery circuit region 140, and be formed with grid structure 110a (being constituted) in the memory cell areas 130 by gate dielectric layer 104a, grid conducting layer 106a and cap layer 108a, and be formed with in the periphery circuit region 140 isolated area 102 with gate structure 110b (being constituted) by gate dielectric layer 104b, grid conducting layer 106b and cap layer 108b.And also be formed with thin clearance wall 112a, a 112b respectively at the sidewall of grid structure 110a, 110b.
Then, form a light doped drain region 114 in periphery circuit region 140, it is formed in the thin clearance wall 112b substrate on two sides 100.Afterwards, in substrate 100, form a barrier layer 116, on barrier layer 116, deposit one deck silester (TEOS)-silica 118, overlies gate structure 110a, 110b again.
Please refer to Figure 1B, TEOS-silicon oxide layer 118 is carried out an etch back process, come out up to barrier layer 116.Therefore wherein, in memory cell areas 130, narrower because of the interval between the adjacent grid structure 110a, left TEOS-silicon oxide layer 118a can fill up space between the grid structure 110a after this etch back process.And in periphery circuit region 140, bigger because of the interval between grid structure 110b and the contiguous element, therefore left TEOS-silicon oxide layer can become the clearance wall 118b of grid structure 110b after this etch back process.
Yet, after this etch back process, tending to find that can attenuation near the barrier layer 116 of clearance wall 118b part 122, same, at the label 124 indication places of memory cell areas, it is thinner that barrier layer 116 also can become, it is called weakness (weak point) again.
After forming clearance wall 118b, in clearance wall 118b substrate on two sides 100, form source 120.Then, utilize a wet etching process again, remove TEOS-silicon oxide layer 118a and clearance wall 118b, shown in Fig. 1 C.After removing TEOS-silicon oxide layer 118a and clearance wall 118b, in substrate 100, form one deck boron phosphosilicate glass (BPSG) 126 again, overlies gate structure 110a, 110b are shown in Fig. 1 D.
Yet, in the process of above-mentioned wet etching process, barrier layer 116 places (weakness place) 122,124 that originally became thin might be by eating thrown, and for 122 places in periphery circuit region 140, because of being isolated area 102 under the barrier layer 116, this wet etching process may continue the isolated area 102 under the etch barrier 116 after eating thrown barrier layer 116, be formed with hole and cause in the isolated area 102.If be formed with hole in the isolated area 102, will make the isolating power of isolated area 102 worsen, and cause disappearances such as leakage current and element reliability variation.
Summary of the invention
Therefore purpose of the present invention just provides a kind of manufacture method of semiconductor element, is known in solution in the manufacture process of dynamic random access memory and has the problem that forms hole in isolated area.
The present invention proposes a kind of manufacture method of semiconductor element, the method is at first providing a substrate, wherein substrate has a memory cell areas and a periphery circuit region, and has been formed with several first grid structures in the memory cell areas, and has been formed with several second grid structures in the periphery circuit region.Then, form a barrier layer, on the conformal surface that covers substrate, first grid structure and second grid structure.Afterwards, on barrier layer, form one first dielectric layer, and then etch-back first dielectric layer, at this, in memory cell areas, less because of the spacing between the first grid structure, therefore first dielectric layer that remains can fill in the space between the first grid structure.And in periphery circuit region, because of the spacing between second grid structure and the neighbouring element is bigger, therefore first dielectric layer that remains can become the clearance wall of second grid sidewall.Subsequently, form source in periphery circuit region, it is formed in the clearance wall substrate on two sides.Then, in substrate, form one second dielectric layer, first dielectric layer that covering remains, clearance wall, first grid structure and second grid structure, second dielectric layer are as the usefulness of interlayer dielectric layer (ILD), and wherein the material of second dielectric layer is identical with the material of first dielectric layer.In the present invention, preferably boron phosphosilicate glass (BPSG) of the material of first dielectric layer and second dielectric layer.
Because first dielectric layer of the present invention is identical material with second dielectric layer, therefore, in periphery circuit region, form after the source/drain regions, do not need the clearance wall of second grid structure side wall is removed, and can continue to form second dielectric layer.So, knownly can cause forming in the isolated area pertusate situation when removing first dielectric layer and just can not take place.
In addition, because of the present invention does not need first dielectric layer is removed, and can directly continue deposition second dielectric layer on first dielectric layer, therefore method of the present invention has been omitted the step that removes first dielectric layer compared to known method, so technology is also comparatively simplified.
Description of drawings
Figure 1A to Fig. 1 D is the leading portion manufacturing process generalized section of known dynamic random access memory;
Fig. 2 A to Fig. 2 C is the leading portion manufacturing process generalized section according to the dynamic random access memory of a preferred embodiment of the present invention.
100: substrate
102: isolated area
104a, 104b: gate dielectric layer
106a, 106b: grid conducting layer
108a, 108b: cap layer
110a, 110b: grid structure
112a, 112b: thin clearance wall
114: light doped drain region
116: barrier layer
118,118a:TEOS-silica
118b, 200b: clearance wall
120: source/drain regions
122,124: weakness
126,200,200a:BPSG layer
Embodiment
Shown in Fig. 2 A to Fig. 2 C, it is the leading portion manufacturing process generalized section according to the dynamic random access memory of a preferred embodiment of the present invention.
Please refer to Fig. 2 A, one substrate 100 at first is provided, wherein substrate 100 has a memory cell areas 130 and a periphery circuit region 140, and be formed with grid structure 110a (being constituted) in the memory cell areas 130 by gate dielectric layer 104a, grid conducting layer 106a and cap layer 108a, and be formed with in the periphery circuit region 140 isolated area 102 with gate structure 110b (being constituted) by gate dielectric layer 104b, grid conducting layer 106b and cap layer 108b.In a preferred embodiment, the material of gate dielectric layer 104a, 104b for example is a silica, and the material of grid conducting layer 106a, 106b for example is a polysilicon, and the material of cap layer 108a, 108b for example is a silicon nitride, and isolated area 102 for example is a shallow-channel isolation region.
Then, sidewall at grid structure 110a, 110b forms thin clearance wall 112a, 112b respectively, the method that wherein forms thin clearance wall 112a, 112b for example is prior to forming a conformal thin layer (not illustrating) afterwards in the substrate 100, this thin conforma layer of etch-back can form thin clearance wall 112a, 112b again.In a preferred embodiment, the material of thin clearance wall 112a, 112b for example is a silicon nitride.
Afterwards, form light doped drain region 114 in periphery circuit region 140, it is formed in the thin clearance wall 112b substrate on two sides 100.Wherein, the method that forms light doped drain region 114 serves as to implant the cover curtain to carry out an ion implantation step and form with grid 110b and thin clearance wall 112b for example.
After forming light doped-drain 114, in substrate 100, form first dielectric layer 200.In a preferred embodiment, the material of first dielectric layer 200 for example is a boron phosphoric acid acid glass, and the method that forms first dielectric layer 200 for example is boiler tube formula Low Pressure Chemical Vapor Deposition (Furnace-LPCVD), boiler tube formula aumospheric pressure cvd method (Furnace-APCVD), one chip formula aumospheric pressure cvd method (Chamber-APCVD), boiler tube formula time aumospheric pressure cvd method (Furnace-SAPCVD) or one chip formula time aumospheric pressure cvd method (Chamber-SAPCVD).In another embodiment, before forming first dielectric layer 200, also comprise forming a barrier layer 116 earlier, cover to compliance on the surface of substrate 100, isolated area 102, grid structure 110a and grid structure 110b.The material of barrier layer 116 for example is a silicon nitride.
Please refer to Fig. 2 B, first dielectric layer 200 is carried out an etch back process, the barrier layer 116 up to grid structure 110a, 110b top comes out.Therefore wherein, in memory cell areas 130, narrower because of the interval between the adjacent grid structure 110a, the first left dielectric layer 200a can fill up space between the grid structure 110a after this etch back process.Therefore and in periphery circuit region 140, bigger because of the interval between grid structure 110b and the neighbouring element, the first left dielectric layer can become the clearance wall 200b of grid structure 110b after this etch back process.
Afterwards, form source 120 in periphery circuit region 140, it is formed in the clearance wall 200b substrate on two sides 100.Wherein, the method that forms source/drain regions 120 serves as to implant cover act to carry out an ion implantation step and form with grid structure 110b and clearance wall 200b for example.
Please refer to Fig. 2 C, after forming source/drain regions 120, do not need the first dielectric layer 200a and clearance wall 200b are removed, and directly in substrate 100 deposition second dielectric layer 126, the first dielectric layer 200a, the clearance wall 200b that covering remains, first grid structure 110a and second grid structure 110b, second dielectric layer 126 is as the usefulness of interlayer dielectric layer (ILD).At this, the material of second dielectric layer 126 is identical with the material of the first dielectric layer 200a and clearance wall 200b.In a preferred embodiment, the material of second dielectric layer 126 for example is a boron phosphoric acid acid glass, and the method that forms second dielectric layer 126 is identical with the method that forms first dielectric layer 200, for example is boiler tube formula Low Pressure Chemical Vapor Deposition, boiler tube formula aumospheric pressure cvd method, one chip formula aumospheric pressure cvd method, boiler tube formula time aumospheric pressure cvd method or one chip formula time aumospheric pressure cvd method.
Follow-up, just can form contact hole, bit line or the like member in the substrate and continue at, and finish the making of memory component according to the design of memory component.
In the present invention, because first dielectric layer is identical material with second dielectric layer, therefore, in periphery circuit region, form after the source/drain regions, do not need the clearance wall of grid structure sidewall in first dielectric layer between the grid structure and the periphery circuit region in the memory cell areas is removed, and can directly above substrate, form second dielectric layer.Thus, knownly can cause forming in the isolated area pertusate situation when removing first dielectric layer and just can not take place.
In addition, because of the present invention does not need the clearance wall of grid structure sidewall in first dielectric layer between the grid structure and the periphery circuit region in the memory cell areas is removed, and can directly on first dielectric layer, continue deposition second dielectric layer, therefore method of the present invention has been omitted the step that removes first dielectric layer compared to known method, so technology is also comparatively simplified.
Claims (16)
1. the manufacture method of a semiconductor element is characterized in that, this method comprises:
One substrate is provided, and this substrate has a memory cell areas and a periphery circuit region, and has been formed with a plurality of first grid structures in this memory cell areas, has been formed with a plurality of second grid structures and a plurality of isolated area in this periphery circuit region;
In this substrate, form one first dielectric layer, cover those isolated areas, those first grid structures and those second grid structures;
This first dielectric layer of etch-back, this that retains first dielectric layer fills up the space between those first grid structures, and this first dielectric layer that retains also becomes a clearance wall of those second grid sidewalls simultaneously;
In this substrate of these clearance wall both sides, form source; And
Form one second dielectric layer above this substrate, cover this first dielectric layer, this clearance wall, those first grid structures and those second grid structures that retain, wherein the material of this second dielectric layer is identical with the material of this first dielectric layer.
2. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the material of this first dielectric layer and this second dielectric layer comprises the boron phosphosilicate glass.
3. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, the method that forms this first dielectric layer is identical with the method that forms this second dielectric layer.
4. the manufacture method of semiconductor element as claimed in claim 1, it is characterized in that the method that forms this first dielectric layer and this second dielectric layer comprises boiler tube formula Low Pressure Chemical Vapor Deposition, boiler tube formula aumospheric pressure cvd method, one chip formula aumospheric pressure cvd method, boiler tube formula time aumospheric pressure cvd method or one chip formula time aumospheric pressure cvd method.
5. the manufacture method of semiconductor element as claimed in claim 1, it is characterized in that, before forming this first dielectric layer, more comprise forming a barrier layer earlier, cover to compliance on the surface of this substrate, those isolated areas, those first grid structures and those second grid structures.
6. the manufacture method of semiconductor element as claimed in claim 5 is characterized in that, the material of this barrier layer comprises silicon nitride.
7. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, those first grid structures and those second grid structures are made of a gate dielectric layer, a grid conducting layer and a cap layer respectively.
8. the manufacture method of semiconductor element as claimed in claim 1 is characterized in that, is formed with a thin clearance wall respectively at the sidewall of those first grid structures and those second grid structures.
9. the manufacture method of semiconductor element as claimed in claim 8 is characterized in that, be formed with a light doped drain region in this substrate that should approach the clearance wall both sides of those second grid structures.
10. the manufacture method of a semiconductor element is characterized in that, this method comprises:
One substrate is provided, has formed an isolated area in this substrate, be formed with a grid structure in this substrate, and the sidewall of this grid structure is formed with one first clearance wall;
In this substrate of these first clearance wall both sides, form a light doped drain region;
In this substrate, form one first dielectric layer; Cover this grid structure;
This first dielectric layer of etch-back forms one second clearance wall with the sidewall at this grid structure;
In this substrate of these second clearance wall both sides, form source; And
Form one second dielectric layer in this substrate, cover this grid structure and this second clearance wall, wherein the material of this second dielectric layer is identical with the material of this first dielectric layer.
11. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, the material of this first dielectric layer and this second dielectric layer comprises the boron phosphosilicate glass.
12. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, it is identical with the method for this second dielectric layer to form this first dielectric layer.
13. the manufacture method of semiconductor element as claimed in claim 10, it is characterized in that the method that forms this first dielectric layer and this second dielectric layer comprises boiler tube formula Low Pressure Chemical Vapor Deposition, boiler tube formula aumospheric pressure cvd method, one chip formula aumospheric pressure cvd method, boiler tube formula time aumospheric pressure cvd method or one chip formula time aumospheric pressure cvd method.
14. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, before forming this first dielectric layer, more comprises forming a barrier layer earlier, on the surface that covers this substrate and this grid structure of compliance.
15. the manufacture method of semiconductor element as claimed in claim 14 is characterized in that, the material of this barrier layer comprises silicon nitride.
16. the manufacture method of semiconductor element as claimed in claim 10 is characterized in that, this grid structure is made of a gate dielectric layer, a grid conducting layer and a cap layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031024718A CN1324686C (en) | 2003-01-27 | 2003-01-27 | Method of making semiconductor components |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031024718A CN1324686C (en) | 2003-01-27 | 2003-01-27 | Method of making semiconductor components |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1521836A CN1521836A (en) | 2004-08-18 |
| CN1324686C true CN1324686C (en) | 2007-07-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB031024718A Expired - Lifetime CN1324686C (en) | 2003-01-27 | 2003-01-27 | Method of making semiconductor components |
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| Country | Link |
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Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104034159B (en) * | 2014-06-06 | 2016-01-20 | 西安航空制动科技有限公司 | A kind of C/C composite cvd furnace |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1065151A (en) * | 1996-08-14 | 1998-03-06 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10242462A (en) * | 1997-02-28 | 1998-09-11 | Nec Corp | Semiconductor device and its manufacture |
| US6218235B1 (en) * | 1999-07-08 | 2001-04-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a DRAM and logic device |
-
2003
- 2003-01-27 CN CNB031024718A patent/CN1324686C/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1065151A (en) * | 1996-08-14 | 1998-03-06 | Sony Corp | Semiconductor device and its manufacturing method |
| JPH10242462A (en) * | 1997-02-28 | 1998-09-11 | Nec Corp | Semiconductor device and its manufacture |
| US6218235B1 (en) * | 1999-07-08 | 2001-04-17 | Mitsubishi Denki Kabushiki Kaisha | Method of manufacturing a DRAM and logic device |
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| Publication number | Publication date |
|---|---|
| CN1521836A (en) | 2004-08-18 |
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