JPH1065151A - Semiconductor device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the electrode structure capable of suppressing the occurrence of curent leakage. SOLUTION: This semiconductor device 10 has a gate electrode structure made of a gate insulating film 14, a gate electrode 16 and a gate offset insulating film 18 on an Si substrate 12. The first sidewall 20 made of Si3 N4 , SiO2 , etc., in a width almost equivalent to the diffusion length in the lateral direction of an LDD diffused layer is formed outside the gate electrode structure. A diffused layer LDD structure part 22 is formed on the Si substrate surface layer on the lower side and outside the first sidewall. The second sidewall 4 made of Si3 N4 , SiO2 , etc., is formed outside the first sidewall. A source/drain diffused layer 26 is formed on the Si substrate surface layer outside the second sidewall 24. Since the overlapping regions of the gate electrode and the diffused LDD structure part is either non-existent or extremely narrow even if existent, the current leakage due to the field distribution can be suppressed, thereby enabling the electrostatic capacity between gate/source and gate/drain to be made small.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to suppressing current leakage (GIDL) due to electric field distribution from a gate electrode, and having excellent high-speed operation and high-frequency operation. And a method of manufacturing the same having a gate electrode structure.

[0002]

2. Description of the Related Art As the integration of semiconductor devices becomes higher and the device dimensions of semiconductor devices become smaller, the electric field inside the semiconductor device tends to increase. Incidentally, one of the undesirable effects of a high electric field on the characteristics of a semiconductor device is a leak current caused by a gate electric field (Gate Induced Drain L).
eakage: hereinafter simply referred to as GIDL).
Hereinafter, the mechanism of occurrence of the current leak will be described with reference to FIG. 4 showing a layer structure of a conventional semiconductor device. FIG.
As shown in (1), the electric field generated from the gate electrode 1 of the semiconductor device is strongly distributed at the interface between the gate insulating film 2 and the semiconductor LDD portion in the gate / diffusion layer overlap region 5, so that carriers in the semiconductor in the vicinity of the region. Causes a tunnel leak, causing a current leak. In FIG. 4, 4 is a Si substrate, 3
Is a source or drain diffusion layer or an LDD diffusion layer, 6 is a source region, and 7 is a drain region. Conventionally, as a method for suppressing the leakage current, a method has been known in which, after forming a gate structure, the gate structure is re-oxidized to locally increase the thickness of the insulating film in this region to reduce the gate electric field. ing.

[0003]

However, this method is
Since the leak current is suppressed by increasing the thickness of the insulating film, it is expected that it will eventually become difficult to satisfy the required conditions as the insulating film becomes thinner. In addition, this method involves re-oxidation of the gate structure, which causes various problems such as the diffusion of impurities in the substrate due to the thermal load at that time, the mutual diffusion of gate impurities, and the diffusion of boron through the gate. It is expected that.

SUMMARY OF THE INVENTION In view of the above circumstances, an object of the present invention is to provide a semiconductor device having a gate electrode and a diffusion layer (LDD) structure which suppresses current leakage due to a gate electric field, and a method of manufacturing the same. It is to be.

[0005]

In order to achieve the object of suppressing the occurrence of current leakage due to the gate electric field, the present inventors first studied and reported on the mechanism of GIDL generation in 718-721-IEDM87. TYChan et al., The Impact of Gate-Induced Drain Leakage C
We focused on urrent on MOSFET scaling. According to these papers, the drain leak current Id due to GIDL
Is the electric field intensity E in the semiconductor / gate insulating film surface electric field.
Using s

[0006]

(Equation 1)

[0007] Here, A and B are constants, respectively. This equation shows that as Es is smaller, the leak current Id
Is small. In addition, the electric field Es
Is expressed as follows using the insulating film relative dielectric constant kox and the semiconductor relative dielectric constant ks based on the gate-drain voltage Vgd and the oxide film thickness Tox shown in the simple analysis model of GIDL in FIG. 5, respectively.

[0008]

(Equation 2)

Here, Vbend is the semiconductor band bending caused by the gate electric field, and this value is the band gap E of the semiconductor.
In the analysis of the leak current, Vbend = 1.2 V
(≒ Eg) is substituted and the calculation of the expression (2) is performed.

The present inventor has proposed that instead of increasing the thickness of the insulating film as in the conventional method, that is, instead of increasing the value of Tox in the equation (2), the gate diffusion layer overlap region is made extremely small. ), The value of the term A in the equation is changed, and as a result, as shown in FIG. 3, the leakage current Id due to GIDL can be suppressed to be equal to or less than other leakage current generated in the LOCOS peripheral portion and the like. I paid attention.

Based on the above-mentioned findings, the semiconductor device according to the present invention provides the LDD side walls on both side surfaces of the gate electrode as first LDs having a width substantially equal to the lateral diffusion length of the LDD diffusion region.
, And a second sidewall outside the first sidewall, an LDD diffusion region is formed in a substrate surface layer below and outside the first sidewall, and a source / drain diffusion is formed in a substrate surface layer outside the second sidewall. It is characterized by having each area. Preferably, the capacitance between the gate / source and between the gate / drain is reduced by making the dielectric constant of the material forming the first sidewall lower than the dielectric constant of the material forming the second sidewall. Thus, a semiconductor device suitable for high-speed operation is realized.

In a method of manufacturing a semiconductor device according to the present invention, after a gate electrode having a gate oxide film as a lower layer is formed on a semiconductor substrate, the gate electrode is formed by a CVD method and etched back to form a first side wall. Forming an LDD diffusion region by performing ion implantation, forming a film outside the first sidewall by a CVD method, and then etching back to form a second sidewall. And a step of forming source / drain diffusion regions by performing ion implantation. Preferably, by forming the first sidewall with a thin TEOS film formed by a CVD method, an etch-back operation when forming the first sidewall can be omitted.

According to the present invention, L is provided on both sides of the gate electrode.
A first sidewall having a width substantially equal to the lateral diffusion length of the LDD diffusion region as the DD sidewall;
By providing the LDD diffusion regions on the substrate surface layer below and on the side wall of the substrate, the overlap region of the gate electrode / LDD diffusion layer can be minimized. Also,
By minimizing the overlap region of the gate electrode / LDD diffusion layer, the capacitance between the gate / source and between the gate / drain can be reduced.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in more detail with reference to the accompanying drawings based on embodiments. Embodiment 1 of a semiconductor device according to the present invention FIG. 1 is a schematic diagram showing a layer structure of an embodiment of a semiconductor device according to the present invention. As shown in FIG. 1, the semiconductor device 10 of the present embodiment has a gate electrode structure including a gate insulating film 14, a gate electrode 16, and a gate offset insulating film 18 on a Si substrate 12. Outside the gate electrode structure,
A first sidewall 20 made of, for example, Si ₃ N ₄ and having a width substantially equal to the lateral diffusion length of the LDD ion implantation is formed. A diffusion layer LDD structure 22 is formed on the surface of the Si substrate 12 below and outside the first sidewall 20 by ion implantation. Outside the first sidewall 20,
For example, a second sidewall 24 made of Si ₃ N ₄ is formed. S outside the second sidewall 24
Source / drain diffusion layers 26 are formed on the surface layer of the i-substrate 12 by ion implantation.

Hereinafter, a method of manufacturing the semiconductor device 10 according to the first embodiment shown in FIG. 1 will be described. (1) The gate insulating film 14, the gate electrode 16, and the gate offset insulating film 1 are formed on the Si substrate 12 in the same manner as in the prior art.
8 are formed, and then an etching process is performed to form a gate structure. (2) Next, the first sidewall 2 having a width corresponding to the lateral diffusion length of the LDD ion implantation.
0 is formed by a CVD method and an etch-back method. (3) Perform ion implantation of the LDD to form the diffusion layer LDD structure 22. (4) The second sidewall 24 is formed by a CVD method and an etch-back method. (5) Hereinafter, the manufacturing process of the semiconductor device is performed by the same method as the related art.

In this embodiment, as shown in FIG. 1, since the first sidewall 20 has the same width as the lateral diffusion length of the diffusion layer LDD structure 22, the gate electrode 14 and the diffusion layer LDD are formed. The region of overlap with the structure 22 is absent or very small, if at all. Therefore, in this embodiment, no current leak due to the electric field distribution from the gate electrode occurs. The capacitance between the gate / source and the capacitance between the gate / drain are each constituted by the sum of the capacitance via the gate insulating film in the overlap region and other capacitance components. In this embodiment,
As described above, since the overlap region is absent or minute, the capacitance in the gate / diffusion layer overlap region is zero or minute. As a result,
The capacitance between the gate / source and between the gate / drain of this embodiment is smaller than that of the conventional semiconductor device having the gate / diffusion layer overlap region.

Embodiment 2 FIG. 2 is a schematic view showing the layer structure of another embodiment of the semiconductor device according to the present invention. In the semiconductor device 30 of the present embodiment,
While the first sidewall 20 of the first embodiment is formed of Si ₃ N ₄ , the first sidewall 32 of the present embodiment is formed of a thin TEOS film formed by a CVD method. I have. The other configuration is the same as the configuration of the semiconductor device 10 of the first embodiment, and has the same effect as the first embodiment. In this embodiment, the first sidewall 32 is formed by CVD.
Since the first sidewall 20 is formed by the thin TEOS film formed by the method, the etch-back process which is necessary when the first sidewall 20 of the first embodiment is formed is not required.

Embodiment 3 FIG. 3 is a schematic view showing a layer structure of still another embodiment of the semiconductor device according to the present invention. In the semiconductor device 40 of this embodiment, the first sidewall 42 is made of SiO ₂ having a low dielectric constant.
And the outer second sidewalls 44Si ₃ N
₄ is formed. Thereby, between the gate / source,
In addition, the capacitance between the gate and the drain, and the capacitance between the gate and the contact can be further reduced as compared with the first embodiment. Further, in the present embodiment, it is considered that the parasitic capacitance around the gate can be reduced, and therefore, the high-speed operability of the semiconductor device can be improved.

[0019]

According to the structure of the present invention, the first sidewall having a width substantially equal to the lateral diffusion length of the LDD diffusion region is formed on both side surfaces of the gate electrode as LDD sidewalls. By providing LDD diffusion regions on the lower and outer substrate surface layers, the overlap region of the gate electrode / diffusion layer can be minimized. Thereby, (1) the leak current caused by GIDL can be suppressed. (2) Since the re-oxidation of the gate electrode structure does not need to be performed, there is an effect that various problems due to the thermal process at that time do not occur. (3) The capacitance between the gate and the source and between the gate and the drain can be reduced, and the high-frequency operation and the high-speed operation of the semiconductor device can be improved.

[Brief description of the drawings]

FIG. 1 is a schematic view illustrating a layer structure of a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a schematic view illustrating a layer structure of a semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a schematic view illustrating a layer structure of a semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a schematic diagram showing a layer structure of a conventional semiconductor device.

FIG. 5 is a schematic diagram illustrating a mechanism of generating GIDL.

FIG. 6 is a graph illustrating that GIDL is suppressed.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Gate electrode, 2 ... Gate insulating film, 3 ... Source or drain diffusion layer or LDD diffusion layer, 4 ... Si substrate, 5 ... Gate / diffusion layer overlap region, 6 ... Source region, 7 ...... Drain region, 10 ... Semiconductor device of Example 1, 12 ... Si substrate, 14 ... Gate insulating film,
16 gate electrode, 18 gate offset insulating film, 20 first sidewall, 22 diffusion layer L
DD structure part, 24... Second sidewall, 26.
Source / drain diffusion layer, 30... Semiconductor device of Example 2, 32... First sidewall, 40.
Of the semiconductor device, 42... First sidewall, 44.
... the second sidewall.

Claims (4)

[Claims] A first sidewall having a width substantially equal to a lateral diffusion length of an LDD diffusion region as an LDD sidewall on both side surfaces of the gate electrode, and a second sidewall outside the first sidewall; LD on the lower and outer surfaces of the substrate
A semiconductor device comprising: a D diffusion region; and a source / drain diffusion region on a part of a lower side of a second sidewall and a surface layer of an outer substrate. 2. The semiconductor device according to claim 1, wherein a dielectric constant of a material forming the first sidewall is lower than a dielectric constant of a material forming the second sidewall. 3. After forming a gate electrode having a gate oxide film as a lower layer on a semiconductor substrate, the gate electrode is formed by a CVD method.
Forming a first sidewall by etching back; forming an LDD diffusion region by performing ion implantation; forming a film outside the first sidewall by a CVD method;
A method of manufacturing a semiconductor device, comprising: a step of forming a second sidewall by etching back; and a step of forming a source / drain diffusion region by performing ion implantation. 4. The method according to claim 3, wherein the first side wall is formed of a thin TEOS film formed by a CVD method.