CN1121058C - Trapezoidal polysilicon plug and its producing method - Google Patents
Trapezoidal polysilicon plug and its producing method Download PDFInfo
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- CN1121058C CN1121058C CN97122618A CN97122618A CN1121058C CN 1121058 C CN1121058 C CN 1121058C CN 97122618 A CN97122618 A CN 97122618A CN 97122618 A CN97122618 A CN 97122618A CN 1121058 C CN1121058 C CN 1121058C
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Abstract
The present invention relates to a method for forming a trapezoidal polysilicon contact plug with small dimension. One polysilicon side clearance wall is made into a mask, and an oxidization layer is etched anisotropically to form a contact layer for depositing polysilicon with high doping density, wherein the deposited polysilicon with the high doping density is used for forming the contact plug. According to the present invention, the trapezoidal contact plug can be formed. The present invention has simple process step and can be suitable for the contact plug structure with small dimension.
Description
Technical field
The present invention relates to a kind of trapezoidal (TAPERED) contact hole and the method for connector and connector of manufacturing thereof in semiconductor device, made.
Background technology
Semiconductor device is to form high concentration P type (P on silicon base
+Type) and high concentration N type (N
+Type) doped region, and utilize these P
+Type and N
+The type doped region connects into desired circuit with it with ad hoc structure as the fundamental of device.This circuit passes the contact mat of test usefulness and passes the wafer that bond to is packed, and can be connected with the external world.Therefore, in order to form the semiconductor circuit, at least must be to layer of conductive material, for example the polysilicon of metal or high-dopant concentration deposits and the step of composition, to form contact or intraconnections between the zones of different of wafer.For example, in typical semiconductor fabrication, at first cover an insulating barrier on wafer, then composition and etching on insulating barrier forms contact hole (opening), deposits conductive material then, and in order to limit the contact that forms contact plunger and intraconnections.
Usually, with silicon or metal silicide to contact (CONTACT) be at an insulating barrier or claim in the dielectric layer, utilize the technology of photoetching and dry ecthing to form.Wherein, dry ecthing is anisotropic etching, makes the contact hole of making can have bigger high wide size than (ASPECT RATIO) and subvertical sidewall.And contact window, then usually with electric conducting material, for example the polysilicon of metal or high-dopant concentration is inserted, and forms vertical connection the with the first rank metal (FIRST LEVEL METAL).If be used to contact N type doped region as the polysilicon of contact plunger then must be the N type; If be used to contact P type doped region then must be the P type, avoid mutual diffusion (INTER-DIFFUSION) and impurity compensation (DOPANT COMPE SATION) effect by this.Polysilicon film can mix in deposition process simultaneously, promptly with environment doping (IN-SITU DOPING).Promptly when under 600 ℃, carrying out low pressure heating and decomposition technical process with the deposit spathic silicon film, in admixture of gas, add arsenic, phosphorus or Boroethane simultaneously with silicon ethane.
Polysilicon film also can mix with the ion implantation process or with diffusion process after deposition process.Polysilicon is the most normal to be applied in the metal-oxide-semiconductor integrated circuit (MOSIC).For example the polysilicon deposition film of high-dopant concentration is used as the intraconnections in grid (GATE) electrode and the MOS circuit usually.And because it has high compatibility to the secondary high temp process, the thermal oxide interfacial property that it is desirable, it is relatively better more stable than aluminium gate material, its consistency (CONFORMIBILITY) when the steep shape of deposition (STEEP TOPOGRAPHY), and, all make polysilicon film have purposes widely covering the ability that forms silicide structural on the metal.
When polysilicon is used as contact plunger, all be formed on usually in the dielectric layer, in order to separate other connector intraconnections and circuit.In order to form contact plunger, contact hole (opening) must utilize selective etch (being the circuit or the intraconnections of one deck under the expose portion) to be formed in the dielectric layer, at polysilicon deposition behind contact hole, in order to connecting time one deck intraconnections and last layer intraconnections, and be deposited on subsequently on the intermediate dielectric layer.The etching process that forms contact hole can be Wet-type etching or dry-etching.The Wet-type etching process be by wafer is immersed in a kind of suitable etching solution or by with this spray solution on wafer.When Wet-type etching, etching operation is isotropic in essence, so this material is with horizontal direction and vertical direction etching.And the horizontal etching regular meeting in the Wet-type etching produces undesired undercutting in most of manufacture process (UNDER CUTTING) under mask.On the contrary, dry etch process then is anisotropic, so can produce vertical sidewall in contact hole, promptly the top of this opening and bottom are similar wide.Can not waste extra horizontal area in order to as contact hole because dry-etching can not produce undercutting (UNDER CUTTING) and dry-etching, modern time micron devices mostly uses the dry-etching technology.The benefit that dry-etching also provides the minimizing chemical hazard in addition, reduces processing step, the easy automation of step is finished and instrument is trooped (TOOL CLUSTERING).The dry-etching technology of the most normal use at present has plasma etch techniques (PLASMA ETCHING TECHNIQUE) and reactive ion etching technique (REACTIVE ION ETCHING TECHNIQUE).
Though the dry-etching technology obtains great improvement on the size Control problem, also therefore in the manufacture method of VLSI and ULSI, widely to use, it also has some shortcomings simultaneously.More just relate to the anisotropy of its etching process, the sidewall of perpendicular is formed in the contact hole in the dry-etching process, but the degree of difficulty that vertical sidewall has been deepened next step (for the internal connecting layer of last layer more) in the contact hole.This problem in required component size the more little and wide size of required height than just serious more under (ASPECT RATIO) high more situation.For example, when the internal connecting layer of electric conducting material will deposit with conventional deposition method, the particulate of electric conducting material can not be consistent with the shape of contact hole, especially in the position that steep or sharp-pointed corner is arranged.Therefore, just thinner than required electric conducting material, perhaps invalid contact plunger may appear.
Therefore, the someone attempts to go to solve this problem of contact hole of how filling up with diverse ways.For example, United States Patent (USP) the 4th, 698 has just disclosed a kind of improved dry-etching process No. 128, and it can make a trapezoidal contact hole sloped sidewall.Yet, the dry-etching circulation that this process need one is time-consuming, and not too suitablely be used for etching media layer hole in thick dielectric layer.In addition, United States Patent (USP) the 4th, 902 is then attempted for No. 377 with the process of dry-etching and Wet-type etching separately.In this method, the upper end of dielectric layer hole is earlier with Wet-type etching undercut mask layer isotropically, to form angled side walls.Then, the bottom of dielectric layer hole forms with dry-etching again, and this dry-etching comprises some replacement step in isotropic mask etch step and the anisotropic dielectric layer etch step.Yet this manufacture process is difficult to carry out, because it needs some both to increase the labour, and the treatment step of losing time.
Summary of the invention
For this reason, the object of the present invention is to provide the trapezoidal contact hole of a kind of formation, perhaps a kind of trapezoidal connector, it is by the mask that uses side clearance walls as the dielectric layer anisotropic etching, and can form trapezoidal contact hole and trapezoidal contact plunger.
Therefore, main purpose of the present invention is to provide a kind of method that forms trapezoidal polysilicon plug, and it can avoid the shortcoming of traditional connector formation technology.
Another object of the present invention is to provide a kind of method that forms trapezoidal polysilicon plug, it only needs to use the dry-etching technology to form contact hole.
Another purpose of the present invention is to provide a kind of method that forms trapezoidal polysilicon plug, and it forms earlier minimum two polysilicon side clearance walls in contact hole, and etching dielectric layer anisotropically, can form the contact hole with a beveled like this.
Another purpose of the present invention is to provide a kind of method that forms trapezoidal polysilicon plug, it through heavily depositing with covering, and heavily cover the ground anisotropic etching and fall polysilicon layer forming the polysilicon side clearance walls, and with its part as the polysilicon plug that then will deposit.
Another purpose of the present invention is to provide a kind of method that forms trapezoidal polysilicon plug, and it re-uses this clearance wall as mask by depositing earlier and forming the polysilicon side clearance walls, in order to anisotropically to etch away dielectric material, to form connector.
Another purpose of the present invention is to provide a kind of trapezoidal polysilicon plug, and it has mainly that a plug bodies and at least one are looped around the plug bodies next door or near the side clearance walls on the top of connector.
A further object of the present invention is to provide a kind of trapezoidal polysilicon plug, it is formed at dielectric layer, and comprises a plug bodies, at least two polysilicon side clearance walls that are looped around plug bodies and face the top that patches plug, at this place, connector mixes with polycrystalline silicon material and forms.
To achieve these goals, the invention provides a kind of method that forms trapezoidal contact hole, may further comprise the steps:
(a) provide the semiconductor substrate, be formed with a dielectric layer and one first polysilicon layer in this substrate, and this first polysilicon layer is positioned on this dielectric layer;
(b) in this first polysilicon layer etching one contact hole to exposing this dielectric layer, to form one first polysilicon side clearance walls;
(c) utilize this first polysilicon side clearance walls as mask, this dielectric layer to one desired depth of etching, and this semiconductor-based end, exposed;
(d) deposition one second polysilicon layer;
(e) this second polysilicon layer of etching is to exposing this dielectric layer, to form one second polysilicon side clearance walls; And
(f) utilize this second polysilicon side clearance walls as mask, this dielectric layer of etching is to expose this semiconductor-based end.
Preferably to this first, this second polysilicon layer and employed this etching process of this dielectric layer be anisotropic etch techniques.
The present invention also provides a kind of method that forms trapezoidal contact hole, may further comprise the steps:
(a) provide the semiconductor substrate, be formed with a dielectric layer and one first polysilicon layer in this substrate, and this first polysilicon layer is positioned on this dielectric layer;
(b) in this first polysilicon layer etching one contact hole to exposing this dielectric layer, to form one first polysilicon side clearance walls;
(c) utilize this first polysilicon side clearance walls as mask, this dielectric layer to one desired depth of etching, and this semiconductor-based end, exposed;
(d) deposition one second polysilicon layer;
(e) this second polysilicon layer of etching is to exposing this dielectric layer, to form one second polysilicon side clearance walls;
(f) utilize this second polysilicon side clearance walls as mask, this dielectric layer of etching but do not expose this semiconductor-based end;
(g) deposition one the 3rd polysilicon layer;
(h) etching the 3rd polysilicon layer is to exposing this dielectric layer, to form one the 3rd polysilicon side clearance walls; And
(i) utilize the 3rd polysilicon side clearance walls as mask, this dielectric layer of etching is to expose this semiconductor-based end.
The present invention also provides a kind of method that forms trapezoidal contact hole, may further comprise the steps:
(a) provide the semiconductor substrate, be formed with a dielectric layer and one first polysilicon layer in this substrate, and this first polysilicon layer is positioned on this dielectric layer;
(b) in this first polysilicon layer etching one contact hole to exposing this dielectric layer, to form one first polysilicon side clearance walls;
(c) utilize this first polysilicon side clearance walls as mask, this dielectric layer to one desired depth of etching, and this semiconductor-based end, exposed;
(d) deposition one second polysilicon layer;
(e) this second polysilicon layer of etching is to exposing this dielectric layer, to form one second polysilicon side clearance walls;
(f) utilize this second polysilicon side clearance walls as mask, this dielectric layer of etching but do not expose this semiconductor-based end;
(g) deposition one the 3rd polysilicon layer;
(h) etching the 3rd polysilicon layer is to exposing this dielectric layer, to form one the 3rd polysilicon side clearance walls;
(i) utilize the 3rd polysilicon side clearance walls as mask, this dielectric layer of etching but do not expose this semiconductor-based end;
(g) deposition one the 4th polysilicon layer;
(h) etching the 4th polysilicon layer is to exposing this dielectric layer, to form one the 4th polysilicon side clearance walls;
(i) utilize the 4th polysilicon side clearance walls as mask, this dielectric layer of etching is to expose this semiconductor-based end.
Preferably this semiconductor-based end is a silicon base.
Preferably this dielectric layer is an oxide layer.
Preferably, this method also comprise one etching this first and this second polysilicon layer before, deposit and limit the step of a photoresist layer pattern.
Preferably this first and this second polysilicon side clearance walls cover the dielectric material of this contact hole sidewall.
Preferably this method also comprises the final step of polysilicon deposition in this contact hole.
The present invention also provides a kind of method that forms trapezoidal contact plunger, may further comprise the steps:
(a) provide the semiconductor substrate;
(b) on this semiconductor-based end, form an oxide layer;
(c) deposition one first polysilicon layer on this oxide layer;
(d) on this first polysilicon layer, deposit one first photoresist layer, and limit the pattern of this first photoresist layer;
(e) etching one contact hole anisotropically on this first polysilicon layer, and expose the first area of this oxide layer in the bottom of this contact hole, make one first polysilicon side clearance walls cover the sidewall of this contact hole;
(f) use the first polysilicon side clearance walls as mask, anisotropically etch exposed is in the first area of this oxide layer of this contact hole bottom, makes it be etched to a degree of depth that is no more than this oxide layer overall width;
(g) deposition one second polysilicon layer in this contact hole;
(h) on this second polysilicon layer, deposit one second photoresist layer, and limit the pattern of this second photoresist layer;
(i) this second polysilicon layer of etching anisotropically, second area with this oxide layer of being exposed to this contact hole bottom, and allowing the second polysilicon side clearance walls cover this contact hole sidewall, the first area area of this oxide layer that the second area area of this oxide layer of exposure exposes is little;
(j) utilize this second polysilicon side clearance walls as mask, the second area of this oxide layer that anisotropic etching exposes is to expose this semiconductor-based end of bottom;
(k) deposit spathic silicon in this contact hole.
Preferably this semiconductor-based end is a silicon base.
This polysilicon that preferably is deposited into this contact hole is the polysilicon once doping.
The present invention also provides a kind of method that forms trapezoidal contact plunger, may further comprise the steps:
(a) provide the semiconductor substrate;
(b) on this semiconductor-based end, form an oxide layer;
(c) deposition one first polysilicon layer on this oxide layer;
(d) on this first polysilicon layer, deposit one first photoresist layer, and limit the pattern of this first photoresist layer;
(e) etching one contact hole anisotropically on this first polysilicon layer, and expose the first area of this oxide layer in the bottom of this contact hole, make one first polysilicon side clearance walls cover the sidewall of this contact hole;
(f) use the first polysilicon side clearance walls as mask, anisotropically etch exposed is in the first area of this oxide layer of this contact hole bottom, makes it be etched to a degree of depth that is no more than this oxide layer overall width;
(g) deposition one second polysilicon layer in this contact hole;
(h) on this second polysilicon layer, deposit one second photoresist layer, and limit the pattern of this second photoresist layer;
(i) this second polysilicon layer of etching anisotropically, second area with this oxide layer of being exposed to this contact hole bottom, and allowing the second polysilicon side clearance walls cover this contact hole sidewall, the first area area of this oxide layer that the second area area of this oxide layer of exposure exposes is little;
(j) utilize this second polysilicon side clearance walls as mask, the second area of this oxide layer that anisotropic etching exposes, etch depth does not expose this semiconductor-based end of bottom;
(k) deposition one the 3rd polysilicon layer in this contact hole;
(l) on the 3rd polysilicon layer, deposit one the 3rd photoresist layer, and limit the pattern of the 3rd photoresist layer;
(m) etching the 3rd polysilicon layer anisotropically, the 3rd zone with this oxide layer of being exposed to this contact hole bottom, and allowing the 3rd polysilicon side clearance walls cover this contact hole sidewall, the second area area of this oxide layer that the 3rd region area of this oxide layer of exposure exposes is little;
(n) utilize the 3rd polysilicon side clearance walls as mask, the 3rd zone of this oxide layer that anisotropic etching exposes is to expose this semiconductor-based end of bottom; And
(o) deposit spathic silicon in this contact hole.
The present invention also provides a kind of method that forms trapezoidal contact plunger, may further comprise the steps:
(a) provide the semiconductor substrate;
(b) on this semiconductor-based end, form an oxide layer;
(c) deposition one first polysilicon layer on this oxide layer;
(d) on this first polysilicon layer, deposit one first photoresist layer, and limit the pattern of this first photoresist layer;
(e) etching one contact hole anisotropically on this first polysilicon layer, and expose the first area of this oxide layer in the bottom of this contact hole, make one first polysilicon side clearance walls cover the sidewall of this contact hole;
(f) use the first polysilicon side clearance walls as mask, anisotropically etch exposed is in the first area of this oxide layer of this contact hole bottom, makes it be etched to a degree of depth that is no more than this oxide layer overall width;
(g) deposition one second polysilicon layer in this contact hole;
(h) on this second polysilicon layer, deposit one second photoresist layer, and limit the pattern of this second photoresist layer;
(i) this second polysilicon layer of etching anisotropically, second area with this oxide layer of being exposed to this contact hole bottom, and allowing the second polysilicon side clearance walls cover this contact hole sidewall, the first area area of this oxide layer that the second area area of this oxide layer of exposure exposes is little;
(j) utilize this second polysilicon side clearance walls as mask, the second area of this oxide layer that anisotropic etching exposes, etch depth does not expose this semiconductor-based end of bottom;
(k) deposition one the 3rd polysilicon layer in this contact hole;
(l) on the 3rd polysilicon layer, deposit one the 3rd photoresist layer, and limit the pattern of the 3rd photoresist layer;
(m) etching the 3rd polysilicon layer anisotropically, the 3rd zone with this oxide layer of being exposed to this contact hole bottom, and allowing the 3rd polysilicon side clearance walls cover this contact hole sidewall, the second area area of this oxide layer that the 3rd region area of this oxide layer of exposure exposes is little;
(n) utilize the 3rd polysilicon side clearance walls as mask, the 3rd zone of this oxide layer that anisotropic etching exposes, but do not expose this semiconductor-based end of bottom;
(o) deposition one the 4th polysilicon layer in this contact hole;
(p) on the 4th polysilicon layer, deposit one the 4th photoresist layer, and limit the pattern of the 4th photoresist layer;
(q) etching the 4th polysilicon layer anisotropically, the 4th zone with this oxide layer of being exposed to this contact hole bottom, and allowing the 4th polysilicon side clearance walls cover this contact hole sidewall, the 3rd region area of this oxide layer that the 4th region area of this oxide layer of exposure exposes is little;
(r) utilize the 4th polysilicon side clearance walls as mask, the 4th zone of this oxide layer that anisotropic etching exposes is to expose this semiconductor-based end of bottom;
(s) deposit spathic silicon in this contact hole.
Preferably the present invention comprises that also one removed this first photoresist layer before this second polysilicon layer of deposition, and the step of removing this second photoresist layer in contact hole before this polysilicon of deposition.
The present invention also provides a kind of trapezoidal polysilicon contact plunger that is formed on dielectric layer, and it comprises a plug bodies and at least one polysilicon side clearance walls, and these side clearance walls are looped around the top of this plug bodies or near the top.
Preferably above-mentioned trapezoidal polysilicon contact plunger comprises two polysilicon side clearance walls at least, is looped around the top of this plug bodies or near the top.
Preferably this plug bodies is once the polysilicon that mixes.
Preferably this dielectric layer is the oxide layer that is deposited on the semiconductor.
Preferably this dielectric layer is the oxide layer that is deposited on the silicon base.
According to a preferred embodiment of the present invention, propose a kind of method that forms trapezoidal contact hole, it may further comprise the steps: at first, provide one to have the semiconductor-based end that a dielectric layer and upper end thereof are coated with first polysilicon layer; Secondly, at the first polysilicon layer etching, one contact hole, dielectric layer is exposed, and form the first polysilicon side clearance walls; Secondly, utilize the first polysilicon side clearance walls as mask, etching dielectric layer to a degree of depth under the principle that does not expose substrate again; Again secondly, deposition second polysilicon layer in contact hole, etching second polysilicon layer exposes dielectric layer, and forms the second polysilicon side clearance walls, then, utilizes the second polysilicon side clearance walls to be mask, and etching and exposed dielectric layer are to substrate.
According to another preferred embodiment of the invention, a kind of method that forms trapezoidal connector is proposed, at first, the semiconductor substrate is provided, in substrate, form an oxide layer, deposition first polysilicon layer on oxide layer, deposit the first photoresist layer (photoresist layer) again and to this layer composition, secondly, etching one contact hole anisotropically in first polysilicon layer, the first area of the oxide layer of contact hole bottom is exposed, and make the first polysilicon side clearance walls cover the sidewall of contact hole, in addition, be mask with the first polysilicon side clearance walls, with the contact hole bottom, the oxide layer of the first area that exposes anisotropically etching one is no more than the degree of depth of oxidated layer thickness.Then, deposition second polysilicon layer on contact hole, the deposition second photoresist layer on second polysilicon layer, and limit the pattern of this photoresist layer and etching second polysilicon layer, and make the second polysilicon side clearance walls cover the sidewall of contact hole so that the second area of the oxide layer of contact hole bottom exposes.Here, the second area area of oxide layer exposure is littler than first area area.The second area of this exposed oxide layer of etching anisotropically, and be mask with the second polysilicon side clearance walls makes outside the semiconductor-based end of lower floor is exposed to, like this can be in contact hole deposit spathic silicon.
The present invention also provides a kind of trapezoidal contact plunger that forms in dielectric layer, it comprises a plug bodies, at least one polysilicon side clearance walls, and it is looped around plug bodies, is positioned at or near the top of this main body.
Brief description of drawings
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by a preferred embodiment, and conjunction with figs. elaborates.In the accompanying drawing:
Fig. 1 is an amplification profile of device of the present invention, and its top in silicon base forms an oxide layer, a polysilicon layer, and once the photoresist layer of composition;
Fig. 2 is an amplification profile of device of the present invention, and its top in silicon base forms an oxide layer and once the polysilicon layer of composition;
Fig. 3 is an amplification profile of device of the present invention, and its top at silicon base and contact hole forms an oxide layer and a polysilicon layer;
Fig. 4 is an amplification profile of device of the present invention, and it deposits second polysilicon layer in contact hole;
Fig. 5 is an amplification profile of device of the present invention, its anisotropically etching second polysilicon layer so that oxide surface exposes;
Fig. 6 is an amplification profile of device of the present invention, and it is etching oxide layer anisotropically;
Fig. 7 is an amplification profile of device of the present invention, and it deposits the 3rd crystal silicon layer in contact hole;
Fig. 8 is an amplification profile of device of the present invention, its anisotropically etching the 3rd polysilicon layer to form the second polysilicon side clearance walls;
Fig. 9 is an amplification profile of device of the present invention, its anisotropically etching oxide layer to expose silicon base;
Figure 10 is an amplification profile of device of the present invention, and it is deposit spathic silicon in contact hole;
Figure 11 is an amplification profile of device of the present invention, and it forms polysilicon plug in contact hole.
Embodiment
Please refer to Fig. 1, it illustrates the amplification profile of semiconductor device 10.Device 10 is formed on the silicon base 12, then forms a thick oxide layer 14 on it, claims dielectric layer again.Wherein oxide layer 14 can be with a kind of boron-phosphorosilicate glass (BPSG) material or any suitable material deposition, and the thickness of oxide layer 14 about 3000 dusts between 12000 dusts.
In the upper end of oxide layer 14, then form one first polysilicon layer 16, in order in subsequent step as the mask of etching oxide layer 14.The thickness of desirable polysilicon layer 16 is that 2000 dusts are between 3000 dusts.Pattern at polysilicon layer 16 upper ends deposition and qualification photoresist layer 18 utilizes anisotropic dry-etching technology to form contact hole 22 in polysilicon layer 16 upper ends then.Wherein, the anisotropy etch back process of polysilicon layer 16 (ETCH BACK PROCESS) can be utilized etching gas (ETCHANT GAS) Cl when etching condition 200～500mTorr
2/ HBr.As shown in Figure 2.This anisotropic etching process is accounting for consequence in the present invention, because it provides a vertical sidewall 26 at contact hole 22, and this anisotropic etch process can not cause any undercutting in the lower end of photoresist mask 18, can not make the etching of any horizontal direction yet and wastes the area of wafer.
Next procedure of the present invention as shown in Figure 3, utilizes polysilicon layer 16 as mask, and oxide layer 14 is carried out anisotropic etching.This etching process is to utilize temporal mode, promptly controls etch depth to about 1500 dusts of oxide layer with a reasonable time.When this etching process is when using the ionic reaction structure, can use etching gas CF
3H/CH
4, under 0～25 ℃, keep half a minute approximately.The etching operation that is noted that this temporal mode is very important, because it can provide a definite etch depth.At least have two or more anisotropic etch process owing to will produce a contact hole, the thickness that oxide layer will be removed in etching each time all must be controlled carefully.
After first oxide layer in contact hole 22 is etched, equably second polysilicon layer is deposited on the upper end of element 10, it also comprises the part of contact hole 22.According to polysilicon height consistency to steep shape when depositing, can on element 10, deposit the polysilicon of thick about 1000 dusts～2000 dusts equably.Please refer to Fig. 4.On polysilicon layer 28, carry out the photomask process then and carry out another time anisotropy etch back process, bottom 32 is etched away, only stay side clearance walls 34 capping oxidation layer sidewall 26, as shown in Figure 5.Here second polysilicon layer 28 and first end that are noted that new deposition deposit the 3rd polysilicon layer 52, and fill up contact hole 22 and cover the oxidized surface 42 that exposes, as shown in Figure 7.Here, the deposition process of the 3rd polysilicon layer 52 and be used in before the deposition second polysilicon layer 28 step similar.Its thickness is then greatly between 1000 dusts～2500 dusts.Then, deposit and limit the pattern of a photoresist layer, and anisotropically eat-back the bottom 54 of polysilicon layer 52, as shown in Figure 8, in contact hole 22, form the second polysilicon side clearance walls 58.The new oxide regions 62 that exposes is eat-back polysilicon layer 52 backs in anisotropy and is formed.It should be noted that the polysilicon layer 52 and 28 in Fig. 7 is expressed as an independent polysilicon layer 52 in Fig. 8.And the new oxide regions area that exposes is littler than the area of previous oxide regions 42 and 24, and this makes that the contact hole area in the oxide layer 14 is more and more narrow.
Please refer to Fig. 9, wherein utilize the second polysilicon side clearance walls 58, on oxide layer 14, carry out an anisotropic etch process as mask.Thus, form new contact hole region area 66, the cross section area of label 62 expressions of itself and Fig. 8 is identical.New contact hole 66 etches away remaining oxide layer, and exposes an area of base 62, so just finishes the making of contact hole 22.The present invention makes the method for a trapezoidal contact hole and can be learnt by above-mentioned explanation and Fig. 1～9.
The method that the present invention makes a trapezoidal contact hole can form one and have the contact hole of meticulousr resolution than existing photoetching corrosion method.And the method can be finished among forming a string polysilicon side clearance walls 34 and 58.It should be noted that in this preferred embodiment we only form twice side clearance walls in contact hole, but, it has littler size if we will form a contact hole, then as long as in reasonable range, also can utilize the number that increases side clearance walls to realize.For example, we can use the 3rd or the 4th polysilicon side clearance walls before oxide layer is etched into silicon base.The change of its process also only need be removed thin oxidated layer thickness after forming the polysilicon side clearance walls each time.
Another preferred embodiment of the present invention then is presented in and forms a contact plunger in the contact hole 22, and it is shown in Figure 10 and Figure 11.In Figure 10, at the upper end of device 10 deposition layer of even polysilicon layer 72.In order to promote the conductivity of polysilicon, the general all arsenic ion or the phosphonium ion of doped with high concentration.The doping process of polysilicon layer can be finished under the same environment of deposition process, also can form behind the ion implanted polysilicon layer again.Then, behind polysilicon layer 72 process photomask processes and the composition, obtain contact plunger 76, as shown in figure 11.
Though disclose the present invention in conjunction with the preferred side of implementing; but it is not in order to limit the present invention; those skilled in the art can make some and change and retouching, so protection scope of the present invention should be limited by accompanying Claim without departing from the spirit and scope of the present invention.
Claims (20)
1. method that forms trapezoidal contact hole may further comprise the steps:
(a) provide the semiconductor substrate, be formed with a dielectric layer and one first polysilicon layer in this substrate, and this first polysilicon layer is positioned on this dielectric layer;
(b) in this first polysilicon layer etching one contact hole to exposing this dielectric layer, to form one first polysilicon side clearance walls;
(c) utilize this first polysilicon side clearance walls as mask, this dielectric layer to one desired depth of etching, and this semiconductor-based end, exposed;
(d) deposition one second polysilicon layer;
(e) this second polysilicon layer of etching is to exposing this dielectric layer, to form one second polysilicon side clearance walls; And
(f) utilize this second polysilicon side clearance walls as mask, this dielectric layer of etching is to expose this semiconductor-based end.
2. the method for claim 1, wherein to this first, this second polysilicon layer and employed this etching process of this dielectric layer be anisotropic etch techniques.
3. method that forms trapezoidal contact hole may further comprise the steps:
(a) provide the semiconductor substrate, be formed with a dielectric layer and one first polysilicon layer in this substrate, and this first polysilicon layer is positioned on this dielectric layer;
(b) in this first polysilicon layer etching one contact hole to exposing this dielectric layer, to form one first polysilicon side clearance walls;
(c) utilize this first polysilicon side clearance walls as mask, this dielectric layer to one desired depth of etching, and this semiconductor-based end, exposed;
(d) deposition one second polysilicon layer;
(e) this second polysilicon layer of etching is to exposing this dielectric layer, to form one second polysilicon side clearance walls;
(f) utilize this second polysilicon side clearance walls as mask, this dielectric layer of etching but do not expose this semiconductor-based end;
(g) deposition one the 3rd polysilicon layer;
(h) etching the 3rd polysilicon layer is to exposing this dielectric layer, to form one the 3rd polysilicon side clearance walls; And
(i) utilize the 3rd polysilicon side clearance walls as mask, this dielectric layer of etching is to expose this semiconductor-based end.
4. method that forms trapezoidal contact hole may further comprise the steps:
(a) provide the semiconductor substrate, be formed with a dielectric layer and one first polysilicon layer in this substrate, and this first polysilicon layer is positioned on this dielectric layer;
(b) in this first polysilicon layer etching one contact hole to exposing this dielectric layer, to form one first polysilicon side clearance walls;
(c) utilize this first polysilicon side clearance walls as mask, this dielectric layer to one desired depth of etching, and this semiconductor-based end, exposed;
(d) deposition one second polysilicon layer;
(e) this second polysilicon layer of etching is to exposing this dielectric layer, to form one second polysilicon side clearance walls;
(f) utilize this second polysilicon side clearance walls as mask, this dielectric layer of etching but do not expose this semiconductor-based end;
(g) deposition one the 3rd polysilicon layer;
(h) etching the 3rd polysilicon layer is to exposing this dielectric layer, to form one the 3rd polysilicon side clearance walls;
(i) utilize the 3rd polysilicon side clearance walls as mask, this dielectric layer of etching but do not expose this semiconductor-based end;
(g) deposition one the 4th polysilicon layer;
(h) etching the 4th polysilicon layer is to exposing this dielectric layer, to form one the 4th polysilicon side clearance walls;
(i) utilize the 4th polysilicon side clearance walls as mask, this dielectric layer of etching is to expose this semiconductor-based end.
5. the method for claim 1, wherein this semiconductor-based end is a silicon base.
6. the method for claim 1, wherein this dielectric layer is an oxide layer.
7. the method for claim 1, its also comprise one etching this first and this second polysilicon layer before, deposit and limit the step of a photoresist layer pattern.
8. the method for claim 1, wherein this first and this second polysilicon side clearance walls cover the dielectric material of this contact hole sidewall.
9. the method for claim 1 wherein also comprises the final step of polysilicon deposition in this contact hole.
10. method that forms trapezoidal contact plunger may further comprise the steps:
(a) provide the semiconductor substrate;
(b) on this semiconductor-based end, form an oxide layer;
(c) deposition one first polysilicon layer on this oxide layer;
(d) on this first polysilicon layer, deposit one first photoresist layer, and limit the pattern of this first photoresist layer;
(e) etching one contact hole anisotropically on this first polysilicon layer, and expose the first area of this oxide layer in the bottom of this contact hole, making one first polysilicon side clearance. wall covers the sidewall of this contact hole;
(f) use the first polysilicon side clearance walls as mask, anisotropically etch exposed is in the first area of this oxide layer of this contact hole bottom, makes it be etched to a degree of depth that is no more than this oxide layer overall width;
(g) deposition one second polysilicon layer in this contact hole;
(h) on this second polysilicon layer, deposit one second photoresist layer, and limit the pattern of this second photoresist layer;
(i) this second polysilicon layer of etching anisotropically, second area with this oxide layer of being exposed to this contact hole bottom, and allowing the second polysilicon side clearance walls cover this contact hole sidewall, the first area area of this oxide layer that the second area area of this oxide layer of exposure exposes is little;
(j) utilize this second polysilicon side clearance walls as mask, the second area of this oxide layer that anisotropic etching exposes is to expose this semiconductor-based end of bottom;
(k) deposit spathic silicon in this contact hole.
11. method as claimed in claim 10, wherein this semiconductor-based end is a silicon base.
12. method as claimed in claim 10, this polysilicon that wherein is deposited into this contact hole is the polysilicon once doping.
13. a method that forms trapezoidal contact plunger may further comprise the steps:
(a) provide the semiconductor substrate;
(b) on this semiconductor-based end, form an oxide layer;
(c) deposition one first polysilicon layer on this oxide layer;
(d) on this first polysilicon layer, deposit one first photoresist layer, and limit the pattern of this first photoresist layer;
(e) etching one contact hole anisotropically on this first polysilicon layer, and expose the first area of this oxide layer in the bottom of this contact hole, make one first polysilicon side clearance walls cover the sidewall of this contact hole;
(f) use the first polysilicon side clearance walls as mask, anisotropically etch exposed is in the first area of this oxide layer of this contact hole bottom, makes it be etched to a degree of depth that is no more than this oxide layer overall width;
(g) deposition one second polysilicon layer in this contact hole;
(h) on this second polysilicon layer, deposit one second photoresist layer, and limit the pattern of this second photoresist layer;
(i) this second polysilicon layer of etching anisotropically, second area with this oxide layer of being exposed to this contact hole bottom, and allowing the second polysilicon side clearance walls cover this contact hole sidewall, the first area area of this oxide layer that the second area area of this oxide layer of exposure exposes is little;
(j) utilize this second polysilicon side clearance walls as mask, the second area of this oxide layer that anisotropic etching exposes, etch depth does not expose this semiconductor-based end of bottom;
(k) deposition one the 3rd polysilicon layer in this contact hole;
(l) on the 3rd polysilicon layer, deposit one the 3rd photoresist layer, and limit the pattern of the 3rd photoresist layer;
(m) etching the 3rd polysilicon layer anisotropically, the 3rd zone with this oxide layer of being exposed to this contact hole bottom, and allowing the 3rd polysilicon side clearance walls cover this contact hole sidewall, the second area area of this oxide layer that the 3rd region area of this oxide layer of exposure exposes is little;
(n) utilize the 3rd polysilicon side clearance walls as mask, the 3rd zone of this oxide layer that anisotropic etching exposes is to expose this semiconductor-based end of bottom; And
(o) deposit spathic silicon in this contact hole.
14. a method that forms trapezoidal contact plunger may further comprise the steps:
(a) provide the semiconductor substrate;
(b) on this semiconductor-based end, form an oxide layer;
(c) deposition one first polysilicon layer on this oxide layer;
(d) on this first polysilicon layer, deposit one first photoresist layer, and limit the pattern of this first photoresist layer;
(e) etching one contact hole anisotropically on this first polysilicon layer, and expose the first area of this oxide layer in the bottom of this contact hole, make one first polysilicon side clearance walls cover the sidewall of this contact hole;
(f) use the first polysilicon side clearance walls as mask, anisotropically etch exposed is in the first area of this oxide layer of this contact hole bottom, makes it be etched to a degree of depth that is no more than this oxide layer overall width;
(g) deposition one second polysilicon layer in this contact hole;
(h) on this second polysilicon layer, deposit one second photoresist layer, and limit the pattern of this second photoresist layer;
(i) this second polysilicon layer of etching anisotropically, second area with this oxide layer of being exposed to this contact hole bottom, and allowing the second polysilicon side clearance walls cover this contact hole sidewall, the first area area of this oxide layer that the second area area of this oxide layer of exposure exposes is little;
(j) utilize this second polysilicon side clearance walls as mask, the second area of this oxide layer that anisotropic etching exposes, etch depth does not expose this semiconductor-based end of bottom;
(k) deposition one the 3rd polysilicon layer in this contact hole;
(l) on the 3rd polysilicon layer, deposit one the 3rd photoresist layer, and limit the pattern of the 3rd photoresist layer;
(m) etching the 3rd polysilicon layer anisotropically, the 3rd zone with this oxide layer of being exposed to this contact hole bottom, and allowing the 3rd polysilicon side clearance walls cover this contact hole sidewall, the second area area of this oxide layer that the 3rd region area of this oxide layer of exposure exposes is little;
(n) utilize the 3rd polysilicon side clearance walls as mask, the 3rd zone of this oxide layer that anisotropic etching exposes, but do not expose this semiconductor-based end of bottom;
(o) deposition one the 4th polysilicon layer in this contact hole;
(p) on the 4th polysilicon layer, deposit one the 4th photoresist layer, and limit the pattern of the 4th photoresist layer;
(q) etching the 4th polysilicon layer anisotropically, the 4th zone with this oxide layer of being exposed to this contact hole bottom, and allowing the 4th polysilicon side clearance walls cover this contact hole sidewall, the 3rd region area of this oxide layer that the 4th region area of this oxide layer of exposure exposes is little;
(r) utilize the 4th polysilicon side clearance walls as mask, the 4th zone of this oxide layer that anisotropic etching exposes is to expose this semiconductor-based end of bottom;
(s) deposit spathic silicon in this contact hole.
15. method as claimed in claim 10, it comprises that also one removed this first photoresist layer before this second polysilicon layer of deposition, and the step of removing this second photoresist layer in contact hole before this polysilicon of deposition.
16. a trapezoidal polysilicon contact plunger that is formed on dielectric layer, it comprises a plug bodies and at least one polysilicon side clearance walls, and these side clearance walls are looped around the top of this plug bodies or near the top.
17. trapezoidal polysilicon contact plunger as claimed in claim 16, it comprises two polysilicon side clearance walls at least, is looped around the top of this plug bodies or near the top.
18. trapezoidal polysilicon contact plunger as claimed in claim 16, wherein this plug bodies is once the polysilicon that mixes.
19. trapezoidal polysilicon contact plunger as claimed in claim 16, wherein this dielectric layer is the oxide layer that is deposited on the semiconductor.
20. trapezoidal polysilicon contact plunger as claimed in claim 16, wherein this dielectric layer is the oxide layer that is deposited on the silicon base.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97122618A CN1121058C (en) | 1997-12-02 | 1997-12-02 | Trapezoidal polysilicon plug and its producing method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97122618A CN1121058C (en) | 1997-12-02 | 1997-12-02 | Trapezoidal polysilicon plug and its producing method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1218985A CN1218985A (en) | 1999-06-09 |
| CN1121058C true CN1121058C (en) | 2003-09-10 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97122618A Expired - Lifetime CN1121058C (en) | 1997-12-02 | 1997-12-02 | Trapezoidal polysilicon plug and its producing method |
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| Country | Link |
|---|---|
| CN (1) | CN1121058C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101330050B (en) * | 2007-06-18 | 2011-03-23 | 中芯国际集成电路制造(上海)有限公司 | Compensating metal oxide semiconductor image sensor and manufacturing method thereof |
| CN101572243B (en) * | 2009-02-06 | 2014-08-27 | 上海华虹宏力半导体制造有限公司 | Method for manufacturing self-aligned sidewall polycrystalline silicon conducting wire and conducting wire manufactured by method |
-
1997
- 1997-12-02 CN CN97122618A patent/CN1121058C/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| CN1218985A (en) | 1999-06-09 |
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