CN1848392A - Semiconductor device and method of manufacture - Google Patents
Semiconductor device and method of manufacture Download PDFInfo
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- CN1848392A CN1848392A CNA2006100752121A CN200610075212A CN1848392A CN 1848392 A CN1848392 A CN 1848392A CN A2006100752121 A CNA2006100752121 A CN A2006100752121A CN 200610075212 A CN200610075212 A CN 200610075212A CN 1848392 A CN1848392 A CN 1848392A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/24—Alloying of impurity materials, e.g. doping materials, electrode materials, with a semiconductor body
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823468—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823418—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
- H01L21/823443—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors
Abstract
Above semiconductor substrate 1 via gate insulation film 3, gate electrode 10 is formed having first insulation layer 5 formed on a top surface of gate electrode 10. On semiconductor substrate 1, second insulation layer 7 is formed in such a manner that the side walls of gate electrode 10 and the top surface of first insulation layer 5 are covered. Second insulation layer 7 is etched back in order to form side wall spacers 11 on the side walls of gate electrode 10 and to expose the surface of an element region. First insulation layer 5 is removed off the surface of gate electrode 10. On the surface of semiconductor substrate 1, high-melting-point metal film 8 is formed in such a manner that the top surface of gate electrode 10 and the surfaces of source-drain regions 1 b are covered, and thereafter, annealing is carried out thereby siliciding the top surface of gate electrode 10 and the surfaces of source-drain regions 1 b in order to form silicide layers 9. According to the present invention, even if the height of the gate electrode is made low, short circuiting between the gate electrode and the source-drain regions is prevented.
Description
Technical field
The present invention relates generally to the method for making semiconductor device, especially relate to and make improving one's methods of semiconductor device, so as can the thinning gate electrode, can handle the refinement of this device architecture and can realize that the height of semiconductor device is integrated.The invention still further relates to the semiconductor device that obtains by this method.
Background technology
Current, for the high-speed cruising of circuit element, use this technology so that reduce the cloth line resistance by this element region of silication.
To a kind of method of making conventional semiconductor device be described.
With reference to Figure 14 (A), on Semiconductor substrate 1, form the element isolation zone 2 that element region and other element region are separated, and thereon, giant grid dielectric film 3 and polysilicon layer 4.
With reference to Figure 14 (B), be positioned on the polysilicon layer 4 and forming on it on corresponding part of grid wiring by photoetching technique formation resist pattern 6.With reference to Figure 14 (B) and 14 (C), utilize resist pattern 6 as mask, etching polysilicon layer 4 and gate insulating film 3 have formed gate electrode 10 thus.Subsequently, removed resist pattern 6.
And with reference to Figure 14 (D), with covering grid electrode 10, it is formed on Semiconductor substrate 1 top to the accumulation silicon oxide film as insulating barrier 7.
With reference to Figure 14 (D) and 15 (E), by etch-back insulating barrier 7, on the sidewall of gate electrode 10, the sidewall spacer 11 that has stayed the silicon dielectric oxide film is used to prevent silication.Subsequently,, utilize sidewall spacer 11 as mask although not shown, implanting impurity ion, thus on the surface of Semiconductor substrate 1 and the both sides of gate electrode 10 formed pair of source-drain region.
With reference to Figure 15 (F), on the whole surface of Semiconductor substrate 1, accumulated refractory metal such as Ti (titanium), Co (cobalt) and Ni (nickel) by sputtering method, formed high melting point metal film 8 thus.With reference to Figure 15 (G), carry out silicidation anneal by proper heat treatment and handle, Semiconductor substrate 1 and high melting point metal film 8 are reacted, thereby formed disilicide layer 9.With reference to Figure 15 (G) and 15 (H),, silicification area and non-silicification area have then been formed simultaneously if removed in the high melting point metal film 8 the still high melting point metal film of unreacted by selective etch.Although not shown, subsequently, on Semiconductor substrate 1, formed interlayer dielectric, and in interlayer dielectric, formed the contact hole that leads to disilicide layer 9.After forming wiring, finished semiconductor device.
According to this method, with reference to Figure 15 (G), when silicidation anneal is handled, even occurred silicon diffusion in the high melting point metal film 8 on sidewall spacer 11 from source-drain region, as long as on the surface of the sidewall spacer between gate electrode 10 and the source-drain region 11, have enough distances, between gate electrode 10 and source-drain region, just can not occur because the short circuit that disilicide layer causes.
Yet, along with grid wiring is made very carefully, the also attenuation of the thickness of gate electrode.Figure 16 (A)-(D) and Figure 17 (E)-(H) show the step of making semiconductor device under the situation of using above-mentioned prior art when the thickness of gate electrode is made thinly.In these figure, provided identical Reference numeral with those the identical or corresponding parts shown in Figure 14 (A)-(D) and Figure 15 (E)-(H), and will no longer repeat its description.
In this case,, compare, form very thinly as the polysilicon layer 4 of gate electrode precursor with above-mentioned prior art with reference to Figure 16 (A).In this case, with reference to Figure 17 (G), because gate electrode 10 is made very thinly, so on the side surface portion of gate electrode 10, the narrower in width of sidewall spacer 11, and on the surface of sidewall spacer 11, the distance between gate electrode 10 and the source-drain region is very short.Thus, when silicidation anneal is handled, if occur silicon diffusion in the high melting point metal film 8 on sidewall spacer 11 from source-drain region, then can on the surface of sidewall spacer 11, form thin disilicide layer, show the such problem of short circuit between gate electrode 10 and source-drain region, to have occurred.
In order to overcome the above problems, as making the gate electrode 10 on the sidewall spacer and the method for the distance between source-drain region, prior art as shown in Figure 18 (for example, Japan patent applicant announce No.08-204193 and Japan patent applicant announce No.08-274043) has been proposed.In these figure, provided identical Reference numeral with those the identical or corresponding parts shown in Figure 14 (A)-(D) and Figure 15 (E)-(H), and will no longer repeat its description.
With reference to Figure 18 (A), on the side surface of the outstanding pattern that constitutes by gate insulating film 3, gate electrode 10 and psg film pattern 51, formed the sidewall spacer 11 of silicon nitride film.Then, with reference to Figure 18 (B),, stayed the sidewall spacer 11 of giving prominence to the shape of the height that is higher than gate electrode 10 by removing psg film pattern 51.With reference to Figure 18 (C), accumulation titanium film 8, and under 450 to 550 ℃ temperature, utilize heating furnace to heat-treat 5-10 minute.Then, if removed the still titanium film of unreacted, reference diagram (D) then can obtain having on the surface of gate electrode 10 and the semiconductor device of the disilicide layer 9 that forms on the surface in source-drain region.
According to this method, by forming the sidewall spacer 11 of the shape of giving prominence to the height that is higher than gate electrode 10, make the sidewall spacer 11 lip-deep distances between gate electrode 10 and the source-drain region very long, and, the short circuit between gate electrode 10 and the source-drain region in silicide step, prevented.
Yet, in method as the prior art shown in Figure 18, under the situation of the sidewall spacer 11 of the shape of the outstanding height that is higher than gate electrode 10, owing to physical damnification or analogue have occurred in the cleaning step between the step of step that psg film 51 is moved apart gate electrode 10 and formation disilicide layer, lose so the top section of sidewall spacer 11 can occur, show to have particle.As a result, there is following problem, promptly polluted manufacturing equipment, and cause significantly reducing to the relevant output of Semiconductor substrate with particle adhesion owing to particle occurring.
Summary of the invention
An object of the present invention is to provide a kind of improving one's methods of semiconductor device of making, even, also can prevent the short circuit between gate electrode and the source-drain region so that the height of gate electrode is made very lowly.
Another object of the present invention provides a kind ofly makes improving one's methods of semiconductor device, so that prevent the short circuit between gate electrode and the source-drain region, and does not have particle.
A further object of the present invention provides a kind of semiconductor device that is obtained by this method.
In the method for making semiconductor device according to a first aspect of the invention, at first, on the surface of Semiconductor substrate, form the element isolation zone that element region and other element region are separated.Next, form gate electrode via gate insulating film above Semiconductor substrate, this gate electrode has first insulating barrier that is formed on the gate electrode top surface.On Semiconductor substrate, formed second insulating barrier in the sidewall and the such mode of the first insulating barrier top surface of covering grid electrode.For the surface that on the sidewall of gate electrode, forms sidewall spacer and expose element region, etch-back second insulating barrier.Utilize gate electrode and sidewall spacer as mask, foreign ion be injected in the surface of element region, with on the surface of Semiconductor substrate and the both sides of gate electrode form pair of source-drain region.First insulating barrier is moved apart the surface of gate electrode.On the surface of Semiconductor substrate, form high melting point metal film with the top surface of covering grid electrode and source-such mode in surface, drain region, and thereafter, the anneal top surface of silicide gate electrode and the surface in source-drain region thus are to form disilicide layer.Remove the still high melting point metal film of unreacted.
According to the present invention, because on Semiconductor substrate, form second insulating barrier that it is the sidewall spacer precursor to cover the such mode of the first insulating barrier top surface, so even the height of gate electrode is made lowly, on the surface of sidewall spacer, also guaranteed distance enough between gate electrode and the source-drain region.
According to a preferred embodiment of the present invention, the step that first insulating barrier is moved apart the gate electrode top surface is undertaken by wet etch process.By this processing, when etching first insulating barrier, can exceedingly not remove the top surface of gate electrode.In addition, when etching first insulating barrier, can exceedingly not remove sidewall.
First insulating barrier is silicon nitride film or silicon oxynitride film preferably.First insulating barrier can be to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film laminated construction as the upper strata.
The thickness of first insulating barrier is preferably 70 to 200nm.
When first insulating barrier is above-mentioned laminated construction, as the thickness of the silicon oxide film of lower floor preferably 5 to 50nm, and as the silicon nitride film on upper strata or silicon oxynitride film preferably 70 to 190nm.
Second insulating barrier is preferably formed by silicon oxide film.
The thickness of second insulating barrier is preferably 70 to 190nm.
Second insulating barrier can be to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film double-decker as the upper strata.In this case, in second insulating barrier, as the thickness of the silicon oxide film of lower floor preferably 5 to 25nm, and as the thickness of the silicon nitride film on upper strata or silicon oxynitride film preferably 70 to 190nm.
According to a preferred embodiment of the present invention, have the relation of h=5W, T 〉=h and W 〉=20nm, wherein W represents the width of sidewall spacer near contact with gate insulating film, and h represents the height of sidewall spacer, and T represents the height of gate electrode.
Have this structure,, on the surface of sidewall spacer, also guaranteed distance enough between gate electrode and the source-drain region even the height of gate electrode is made very lowly.
The above preferred Ti of silicide layer (titanium), Co (cobalt) or the disilicide layer of Ni (nickel).
Above Semiconductor substrate, can there be another step that forms individual layer or two-layer interlayer dielectric.
In the method for making semiconductor device according to a further aspect in the invention, at first, on the surface of Semiconductor substrate, be formed for the element isolation zone that element region is separated with other element region.Next, form gate electrode via gate insulating film above Semiconductor substrate, this gate electrode has first insulating barrier that is formed on the gate electrode top surface.On Semiconductor substrate, form second insulating barrier in the sidewall and the such mode of the first insulating barrier top surface of covering grid electrode.For the surface that on the sidewall of gate electrode, forms sidewall spacer and expose element region, etch-back second insulating barrier.Utilize gate electrode and sidewall spacer as mask, foreign ion be injected in the element region, with on the surface of Semiconductor substrate and the both sides of gate electrode form pair of source-drain region.To cover this source-such mode in surface, drain region is formed first high melting point metal film, and heat-treat, and thereafter, remove still first high melting point metal film of unreacted with formation first disilicide layer on the surface in source-drain region.Above Semiconductor substrate, the such mode of gate electrode that provides first insulating barrier with covering forms interlayer dielectric.The surface of polishing interlayer dielectric is with its surface of planarization, and exposes the surface of first insulating barrier.Remove first insulating barrier that exposes to expose the top surface of gate electrode.On interlayer dielectric, the such mode of top surface that exposes with covering grid electrode forms second high melting point metal film, and heat-treats to form second disilicide layer on the top surface of gate electrode.In interlayer dielectric, form contact hole, and form metal line.
According to the present invention, owing to provide interlayer dielectric to cover the such mode of sidewall spacer, and on the surface of gate electrode, carried out silicidation, so prevented from short circuit to occur between surface gate electrode and source-drain region.
First insulating barrier preferably comprises silicon nitride film or silicon oxynitride film.
First insulating barrier can be to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film laminated construction as the upper strata.
The silicon nitride film in first insulating barrier or the thickness of silicon oxynitride film are preferably 100 to 250nm.
When first insulating barrier is above-mentioned laminated construction, is preferably 5 to 50nm as the thickness of the silicon oxide film of lower floor, and is preferably 70 to 190nm as the silicon nitride film on upper strata or the thickness of silicon oxynitride film.
Second insulating barrier is silicon oxide film preferably.
The thickness that is used as the silicon oxide film of second insulating barrier is preferably 70 to 190nm.
Second insulating barrier can be to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film double-decker as the upper strata.In this case, the thickness that is used as the silicon oxide film of lower floor is preferably 5 to 25nm, and is preferably 70 to 190nm as the silicon nitride film on upper strata or the thickness of silicon oxynitride film.
If the polished amount on interlayer dielectric surface makes thickness 5 to 80% also polished of the dielectric film of winning, then can eliminate the projection at sidewall spacer top.
Semiconductor device according to a further aspect of the invention relates to a kind of semiconductor device, and it comprises: Semiconductor substrate; Be formed on the gate electrode of Semiconductor substrate top via gate insulating film; Be formed on the semiconductor substrate surface and the pair of source-drain region of gate electrode both sides; Be formed on the sidewall spacer on the gate electrode sidewall; And be formed on the gate electrode top surface and the lip-deep disilicide layer in source-drain region.Exist and concern h=5W, T 〉=h, and W 〉=20nm, near the width of the middle sidewall spacer that the W representative here contacts with gate insulating film, h represents the height of sidewall spacer, and T represents the height of gate electrode.
Semiconductor device according to a further aspect of the invention relates to a kind of semiconductor device, and it comprises: Semiconductor substrate; Be formed on the gate electrode of Semiconductor substrate top via gate insulating film; Be formed on the semiconductor substrate surface and the pair of source-drain region of gate electrode both sides; Be formed on the sidewall spacer on the gate electrode sidewall; And be formed on the gate electrode top surface and the lip-deep disilicide layer in source-drain region.The thickness that is formed on the disilicide layer on the surface gate electrode is thicker than the thickness that is formed on the lip-deep disilicide layer in source-drain region.
Each sidewall spacer can be the double-decker that comprises lower floor and upper strata, and this lower floor contacts and formed by silicon oxide film with the sidewall of gate electrode, and this upper strata is provided on the gate electrode sidewall and by silicon nitride film or silicon oxynitride film via this lower floor and forms.
According to the method for making semiconductor device according to the invention, when forming silicification area and non-silicification area at the same time, on the side surface of gate electrode, form sidewall spacer and guarantee to surpass predetermined width.For this reason, when silicidation anneal is handled, even in high melting point metal film, occur spreading, because enough sidewall width also can suppress because gate electrode that disilicide layer causes and the short circuit between source-drain region from the silicon in source-drain region.Thus, can realize the thinning of gate electrode, can handle the refinement of this device architecture, and can realize that the height of semiconductor device is integrated.
Description of drawings
Fig. 1 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 1 (A)-(D).
Fig. 2 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 1 (E)-(H).
Fig. 3 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 1 (I)-(K).
Fig. 4 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 1 (L)-(M).
Fig. 5 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 2 (A)-(D).
Fig. 6 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 2 (E)-(H).
Fig. 7 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 2 (I)-(L).
Fig. 8 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 2 (M)-(O).
Fig. 9 is the sectional view according to the semiconductor device of embodiment 3.
Figure 10 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 4 (A)-(B).
Figure 11 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 5 (A)-(D).
Figure 12 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 5 (E)-(G).
Figure 13 is the sectional view according to the semiconductor device in the step of the method for the semiconductor device of embodiment 6 (A)-(D).
Figure 14 is the sectional view of the semiconductor device in the step (A)-(D) of the conventional method of semiconductor device.
Figure 15 is the sectional view of the semiconductor device in the step (E)-(H) of the conventional method of semiconductor device.
Figure 16 is the sectional view of the semiconductor device in the step (A)-(D) of the another kind of conventional method of semiconductor device.
Figure 17 is the sectional view of the semiconductor device in the step (E)-(H) of the another kind of conventional method of semiconductor device.
Figure 18 is the sectional view of the semiconductor device in the step (A)-(D) of another conventional method of semiconductor device.
In these figure, Reference numeral 1 expression Semiconductor substrate, 2 expression element isolation zones, 3 expression gate insulators, 4 expression polysilicon layers, 5 expressions, first insulating barrier, 6 expression resist patterns, 7 expressions, second insulating barrier, 8 expression high melting point metal films, 9 expression disilicide layers, 10 expression gate electrodes, 11 expression sidewall spacers, 13 expressions, first interlayer dielectric, 14 expression metal lines, 15 expression contact holes, and 16 expressions, second interlayer dielectric.
Embodiment
Below with reference to each figure embodiments of the invention are described.In each figure, identical or corresponding part provides identical Reference numeral below.
[embodiment 1]
With reference to figure 1 (A), similar to prior art, by element isolation zone 2 is provided, formed the element region of a plurality of separation on the surface of silicon substrate as Semiconductor substrate 1.Next, above Semiconductor substrate 1, giant grid dielectric film 3 and polysilicon layer 4.
With reference to figure 1 (B), on polysilicon layer 4, accumulate first insulating barrier 5.As first insulating barrier 5, use silicon nitride film.The thickness of first insulating barrier 5 wishes it is 1400 .Utilize this structure, as described below, when etching polysilicon layer 4 and gate insulating film 3, do not have the first all insulating barrier 5 of etching.In addition, during second insulating barrier 7 that below etching, will describe, the first all insulating barrier 5 of etching not.In addition, when silicidation anneal is handled, even silicon diffusion in sidewall spacer 11 lip-deep high melting point metal films, occurred from source-drain region, also guaranteed enough width for sidewall spacer 11, be not formed on the surface of sidewall spacer 11 so that cause the disilicide layer of short circuit between gate electrode 10 and the source-drain region.
With reference to figure 1 (C) and (D), formed on it on surface of corresponding first insulating barrier 5 of part of gate electrode, formed resist pattern 6 by photoetching technique.Next, utilize resist pattern 6,, first insulating barrier 5 is carried out anisotropic etching by for example utilizing under magnetron RIE (reactive ion etching) equipment and condition below as mask.
Pressure: 50mTorr
High frequency power: 500W
CH
2F
2/Ar/O
2＝40/30/15sccm
With reference to figure 1 (D) and 2 (E),, remove resist pattern 6 by using incineration equipment.
With reference to figure 2 (E) and 2 (F), utilize remaining first insulating barrier 5 as etching mask, the polysilicon layer 4 beyond the part at etching mask place and the part of gate insulating film 3, thus form gate electrode 10.Next, the ion that is used to form transistorized LDD district 1a injects.
With reference to figure 2 (G),, on Semiconductor substrate 1, accumulate silicon oxide film to cover the gate electrode 10 and remaining first insulating barrier, the 5 such modes that form as second insulating barrier 7.With reference to figure 2 (G) and 2 (H),, on the sidewall of gate electrode 10, stayed the sidewall spacer 11 of silicon oxide film by etch-back second insulating barrier 7.Using for 7 of second insulating barriers under the situation of silicon oxide film, the width of the sidewall spacer 11 that obtains by etch-back (near the width of the middle sidewall spacer 11 that contact with processed gate insulating film 3) approximately is 17 to 20nm.The height of sidewall spacer 11 is about five times of sidewall spacer 11 width, and approximates the height (thickness that comprises first insulating barrier 5) of gate electrode 10.
With reference to figure 2 (H) and 3 (I), remove remaining first insulating barrier 5.Next, in order to form the highly dense N district of transistor formed source-drain region 1b, the ion that carries out arsenic etc. injects, and heat-treats the arsenic ion that is injected to activate.
With reference to figure 3 (J), accumulate refractory metal by sputtering method, galvanoplastic or CVD method, as Ti (titanium), Co (cobalt) and Ni (nickel), thereby on the whole surface of Semiconductor substrate 1, form refractory metal 8.Next,, handle, the surface of gate electrode 10, surface and the high melting point metal film 8 of source-drain region 1b are reacted, thus, formed disilicide layer 9 by carry out silicidation anneal with suitable heat treatment with reference to figure 3 (K).
With reference to figure 3 (K) and 4 (L), remove in the high melting point metal film 8 the still high melting point metal film of unreacted by selective etch.By top step, form silicification area and non-silicification area simultaneously.
With reference to figure 4 (M), above Semiconductor substrate 1, form first interlayer dielectric 13 and second interlayer dielectric 16, and in first and second interlayer dielectrics 13 and 16, formation exposes the contact hole 15 on the surface of disilicide layer 9, and by metal line 14 is provided, has finished semiconductor device.
According to present embodiment, when the silicidation anneal in the step of Fig. 3 (K) is handled, even occurred silicon diffusion in the high melting point metal film 8 on sidewall spacer 11 from source-drain region, because sidewall spacer 11 has enough width, therefore controlled because gate electrode 10 that disilicide layer causes and the short circuit between source-drain region 1b.
[embodiment 2]
Present embodiment is the situation of carrying out the silication in the silication of surface gate electrode and source-drain region in different steps.
With reference to figure 5 (A), similar to embodiment 1, by element isolation zone 2 is provided, formed the element region of a plurality of separation on the surface of Semiconductor substrate 1.Above Semiconductor substrate 1, giant grid dielectric film 3 and polysilicon layer 4.
With reference to figure 5 (B), on polysilicon layer 4, accumulate first insulating barrier 5.As first insulating barrier 5, use silicon oxide film, silicon nitride film or oxygen silicon nitride membrane.And first insulating barrier 5 can be a laminated construction, so as on polysilicon layer 4 growth 5 to 50nm silicon oxide film, and grow thereon 70 to 190nm silicon nitride film or oxygen silicon nitride membrane.
Next,, on it, formed on corresponding first insulating barrier 5 of part of gate electrode, formed resist pattern 6 by photoetching technique with reference to figure 5 (C) and 5 (D).Next, utilize resist 6 as mask, magnetron RIE (reactive ion etching) equipment carries out anisotropic etching to first insulating barrier 5 by for example utilizing.
Then, with reference to figure 5 (D) and 6 (E),, remove resist pattern 6 by using incineration equipment and cleaning equipment.
Next, with reference to figure 6 (E) and 6 (F), utilize remaining first insulating barrier 5 as etching mask, the polysilicon layer 4 beyond the part at this mask place of etching and the part of gate insulating film 3 form gate electrode 10 thus.Next, the ion that is used to form transistorized LDD district 1a injects.
And, with reference to figure 6 (G),,, on Semiconductor substrate 1, accumulate silicon oxide film, silicon nitride film or silicon oxynitride film with covering grid electrode 10 and the such mode of remaining first insulating barrier 5 as second insulating barrier 7.
With reference to figure 6 (G) and 6 (H),, on the sidewall of gate electrode 10, formed the sidewall spacer 11 of silicon oxide film by etch-back second insulating barrier 7.Because second insulating barrier 7 comprises silicon oxynitride film or silicon nitride film, even so carried out etch-back, near the width of sidewall spacer 11 (contact with processed gate insulating film 3 in the width of sidewall spacer) is also than forming widelyer when for 7 uses of second insulating barrier silicon oxide film.
Next, shown in Fig. 6 (H), in order to form the highly dense N district of source transistor-drain region 1b, the ion that carries out arsenic etc. injects, and the arsenic ion that injects in order to activate is heat-treated.
Then, shown in Fig. 7 (I), utilize refractory metal such as Ti (titanium), cobalt (Co) and Ni (nickel), on the whole surface of Semiconductor substrate 1, accumulate 10 to 100nm refractory metal 8 by sputtering method, galvanoplastic or CVD method.Next, carry out first silicidation anneal by 450 to 650 ℃ heat treatment steps and handle, Semiconductor substrate 1 and high melting point metal film 8 are reacted, thus, on source-drain region 1b, form disilicide layer 9.Then, remove in the high melting point metal film 8 the still high melting point metal film of unreacted by selective etch.
Next, with reference to figure 7 (J), on Semiconductor substrate 1, form about 300 to 800nm first interlayer dielectric 13.With reference to figure 7 (K), carry out planarization by polishing first interlayer dielectric 13.As the stopper film of polishing, in component forming region, be formed at the effect that first insulating barrier 5 on the gate electrode 10 demonstrates this film.This stopper film has the material similar to first insulating barrier 5, and also is formed on the periphery of Semiconductor substrate 1 and on the element isolation zone.In this case, the polished amount of first insulating barrier 5 is controlled as about 2 to 20% of first insulating barrier, 5 thickness.
Subsequently, to 7 (L), remove first insulating barrier 5 with reference to figure 7 (K).As a result, formed the semiconductor device that has wherein stayed the higher sidewall spacer 11 of aspect ratio gate electrode 10.Notice if first insulating barrier 5 is only formed by silicon oxide film, then form the short sidewall spacer 11 of aspect ratio gate electrode 10.Then, in order in gate electrode 10, to form highly dense N district, carry out the ion injection of arsenic etc., and the arsenic ion that injects in order to activate is heat-treated.
Next, shown in Fig. 8 (M),,, then on the whole surface of Semiconductor substrate 1, form refractory metal 8 as Ti (titanium), Co (cobalt) and Ni (nickel) if by sputtering method, galvanoplastic or CVD method accumulation refractory metal.Next, carry out silicidation anneal by 450 to 650 ℃ heat treatment steps and handle, polysilicon layer and high melting point metal film 8 as gate electrode 10 are reacted, thus, on the surface of gate electrode 10, form disilicide layer 9.Next, remove in the high melting point metal film 8 the still high melting point metal film of unreacted by selective etch.
Routinely, the silication on transistor gate surface and the silication in source-drain region are carried out simultaneously, and because the degree of depth in source-drain region is made shallowly, so can not carry out sufficient silication.Therefore, be used for gate electrode polysilicon resistance to reduce be inadequate.According to present embodiment, owing to can select the thickness of high melting point metal film independently, and heat treatment temperature can be chosen in a high value, so can easily finish reducing of polygate electrodes resistance related in being about to the refinement of carrying out.
In addition, conventional silicidation makes in the lip-deep high melting point metal film of sidewall spacer, when heat treatment, silicon from the source-leakage diffusion and migration, generate disilicide layer thus, as a result, the surface that utilizes sidewall spacer is as current path, caused short circuit between the surface of gate electrode and source-drain region.Yet, according to embodiment 2, because the surface of sidewall spacer 11 covered by first interlayer dielectric 13, and carries out the silicidation of gate electrode top surface then, so realized preventing from effectively to occur between surface gate electrode and the source-drain region effect of short circuit.
Next, with reference to figure 8 (N), above Semiconductor substrate 1, form second interlayer dielectric 16 of 50 to 250nm thickness.
Next,, in first interlayer dielectric 13 and second interlayer dielectric 16, behind the formation contact hole 15, form metal line 14, formed transistor thus with reference to figure 8 (O).Subsequently, can form other interlayer dielectric, perhaps can form surface protection film and finish semiconductor device.
[embodiment 3]
[embodiment 4]
According to present embodiment, when the planarization of first interlayer dielectric 13, remove the projection at sidewall spacer 11 tops places, and when first silicidation anneal is handled, remove the silicide powder on the upper surface of staying sidewall spacer 11 and the conducting strip of high melting point metal film 8.As a result, prevented by aforesaid on surface gate electrode part disilicide layer 9 and transistorized source region or drain region between the short circuit that causes.
Then, carry out the identical step of step with Fig. 7 (L), 8 (M) and 8 (N).With reference to Figure 10 (B), above Semiconductor substrate 1, form second interlayer dielectric 16 of 50 to 250nm thickness.Next, in first interlayer dielectric 13 and second interlayer dielectric 16, behind the formation contact hole 15, form metal line 14, finished transistor thus.
[embodiment 5]
Present embodiment relates to another variation example of embodiment 2.In the present embodiment, each sidewall spacer all is a double-layer structure.At first, carry out the identical step of step with Fig. 5 (A)-(D) and Fig. 6 (E)-(F).
Next,,, on Semiconductor substrate 1, form silicon oxide film 7a with covering grid electrode 10 and the such mode of remaining first insulating barrier 5 with reference to Figure 11 (A), and thereon, accumulation silicon oxynitride film (or silicon nitride film) 7b.As the thickness of the silicon oxide film 7a of lower floor is 5 to 25nm, and is 70 to 190nm as the thickness of silicon oxynitride film (or silicon nitride film) 7b on upper strata.
With reference to Figure 11 (A) and 11 (B),, on the sidewall of gate electrode 10, form sidewall spacer 11 by etch-back silicon oxynitride film (or silicon nitride film) 7b and silicon oxide film 7a.Because sidewall spacer 11 comprises silicon oxynitride film (or silicon nitride film), even so carried out etch-back, near the width of sidewall spacer 11 (contact with processed gate insulating film 3 in the width of sidewall spacer 11) forms also than wideer when only using silicon oxide film for second insulating barrier 7, shown in Fig. 6 (G).Next, in order to form the highly dense N district of source transistor-drain region 1b, the ion that carries out arsenic etc. injects, and the arsenic ion that injects in order to activate is heat-treated.
Then, shown in Figure 11 (C), utilize refractory metal such as titanium (Ti), Co (cobalt) and Ni (nickel), by sputtering method, galvanoplastic or CVD method refractory metal 8 in the whole surface accumulation 10 to 100nm of Semiconductor substrate 1.Next, carry out first silicidation anneal by 450 to 650 ℃ heat treatment steps and handle, Semiconductor substrate 1 and high melting point metal film 8 are reacted, thus, on source-drain region 1b, form disilicide layer 9.Then, remove in the high melting point metal film 8 the still high melting point metal film of unreacted by selective etch.
Next, with reference to Figure 11 (D), on Semiconductor substrate 1, formed about 300 to 800nm first interlayer dielectric 13.With reference to Figure 12 (E), carry out planarization by polishing first interlayer dielectric 13.As the stopper film that is used to polish, in component forming region, be formed at the effect that first insulating barrier 5 on the gate electrode 10 demonstrates this film.Although not shown, stopper film has the material similar to first insulating barrier 5, and also is formed on peripheral part of element isolation zone and Semiconductor substrate 1.In this case, the polished amount of first insulating barrier 5 is controlled as about 2 to 20% of first insulating barrier, 5 thickness.
Subsequently, with reference to Figure 12 (E) and 12 (F), remove first insulating barrier 5.As a result, formed the semiconductor device that sidewall spacer 11 wherein has the height higher than gate electrode 10.Then, carry out the identical step of step with Fig. 7 (L), 8 (M) and 8 (N), and on gate electrode 2, form disilicide layer 9.Next,, in first interlayer dielectric 13 and second interlayer dielectric 16, behind the formation contact hole 15, formed metal line 14, formed transistor thus with reference to Figure 12 (G).
[embodiment 6]
Present embodiment relates to the variation example of embodiment 5.Figure 13 (A) is corresponding to Figure 11 (D).With reference to Figure 13 (A) and 13 (B), carry out planarization, so that polish first interlayer dielectric 13 in the such mode of 20 to 80% thickness of polishing first insulating barrier 5.Then, with reference to Figure 13 (B) and 13 (C), remove first insulating barrier 5.
According to present embodiment, when planarization first interlayer dielectric 13, remove the projection at sidewall spacer 11 tops places, and when first silicidation anneal is handled, removed the silicide powder stayed on sidewall spacer 11 top sections and the conducting strip of high melting point metal film 8.As a result, prevented by aforesaid on surface gate electrode part disilicide layer 9 and transistorized source region or drain region between the short circuit that causes.
Then, carry out the identical step of step with Fig. 7 (L), 8 (M) and 8 (N).With reference to Figure 13 (D), above Semiconductor substrate 1, form second interlayer dielectric 16 of 50 to 250nm thickness.Next, in first interlayer dielectric 13 and second interlayer dielectric 16, behind the formation contact hole 15, form metal line 14, formed transistor thus.
By the present invention, can realize the thinning of gate electrode, can handle the refinement of this device architecture, and can realize that the height of semiconductor device is integrated.
Embodiment described here is all thought exemplary and is not provided constraints from all aspects.Scope of the present invention not only should be determined by the embodiment of institute's example, and should be determined by appended claim, and therefore falls into the meaning of equal value of claims and all changes in the scope and all mean and be contained in wherein.
Claims (25)
1. method of making semiconductor device may further comprise the steps:
On the surface of Semiconductor substrate, be formed for the element isolation zone that element region is separated with other element region;
Form gate electrode via gate insulating film above Semiconductor substrate, this gate electrode has first insulating barrier that is formed on the gate electrode top surface;
On Semiconductor substrate, form second insulating barrier with the sidewall of covering grid electrode and the such mode of top surface of first insulating barrier;
For the surface that on the sidewall of gate electrode, forms sidewall spacer and expose element region, etch-back second insulating barrier;
Utilize gate electrode and sidewall spacer as mask, foreign ion be injected in the surface of element region, with on the surface of Semiconductor substrate and the both sides of gate electrode form pair of source-drain region;
First insulating barrier is moved apart the surface of gate electrode;
On the surface of Semiconductor substrate, form high melting point metal film with the top surface of covering grid electrode and source-such mode in surface, drain region, and thereafter, thereby the surface in the top surface of the silicide gate electrode of annealing and source-drain region, to form disilicide layer; And
Remove the still high melting point metal film of unreacted.
2. according to the method for the manufacturing semiconductor device of claim 1, wherein first insulating barrier is silicon nitride film or silicon oxynitride film.
3. according to the method for the manufacturing semiconductor device of claim 1, wherein first insulating barrier is to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film laminated construction as the upper strata.
4. according to the method for the manufacturing semiconductor device of claim 1, wherein the thickness of first insulating barrier is 70 to 200nm.
5. according to the method for the manufacturing semiconductor device of claim 3, wherein in first insulating barrier, be 5 to 50nm, and be 70 to 190nm as the thickness of the silicon nitride film on upper strata or silicon oxynitride film as the thickness of the silicon oxide film of lower floor.
6. according to the method for the manufacturing semiconductor device of claim 1, wherein second insulating barrier is formed by silicon oxide film.
7. according to the method for the manufacturing semiconductor device of claim 1, wherein the thickness of second insulating barrier is 70 to 190nm.
8. according to the method for the manufacturing semiconductor device of claim 1, wherein in second insulating barrier, lower floor is a silicon oxide film, and the upper strata is silicon nitride film or silicon oxynitride film.
9. the method for manufacturing semiconductor device according to Claim 8 wherein in second insulating barrier, is 5 to 25nm as the thickness of the silicon oxide film of lower floor, and is 70 to 190nm as the thickness of the silicon nitride film on upper strata or silicon oxynitride film.
10. according to the method for the manufacturing semiconductor device of claim 1, there is the relation of h=5W, T 〉=h and W 〉=20nm,
Wherein W represents the width of sidewall spacer near contact with gate insulating film, and h represents the height of sidewall spacer, and T represents the height of gate electrode.
11. according to the method for the manufacturing semiconductor device of claim 1, wherein silicide layer is the silicide layer of Ti (titanium), Co (cobalt) or Ni (nickel).
12. according to the method for the manufacturing semiconductor device of claim 1, further be included in the top of Semiconductor substrate, form the step of individual layer or two-layer interlayer dielectric.
13. a method of making semiconductor device comprises the steps:
On the surface of Semiconductor substrate, be formed for the interelement septal area that element region is separated with other element region;
Form gate electrode via gate insulating film above Semiconductor substrate, this gate electrode has first insulating barrier that is formed on the gate electrode top surface;
On Semiconductor substrate, form second insulating barrier with the sidewall of covering grid electrode and the such mode of top surface of first insulating barrier;
For the surface that on the sidewall of gate electrode, forms sidewall spacer and expose element region, etch-back second insulating barrier;
Utilize gate electrode and sidewall spacer as mask, foreign ion be injected in the element region, with on the surface of Semiconductor substrate and the both sides of gate electrode form pair of source-drain region;
Form first high melting point metal film to cover this surperficial such mode, and heat-treat, and thereafter, remove still first high melting point metal film of unreacted with formation first disilicide layer on the surface in source-drain region to source-drain region;
Above Semiconductor substrate, the such mode of gate electrode that provides first insulating barrier with covering forms interlayer dielectric;
The surface of polishing interlayer dielectric is so that its surface of planarization, and exposes the surface of first insulating barrier;
Remove first dielectric film that exposes so that expose the top surface of gate electrode;
On interlayer dielectric, form second high melting point metal film in the such mode of top surface of the exposure of covering grid electrode, and heat-treat on the top surface of gate electrode, to form second disilicide layer; And
In interlayer dielectric, form contact hole, and form metal line.
14. according to the method for the manufacturing semiconductor device of claim 13, wherein first insulating barrier comprises silicon nitride film or silicon oxynitride film.
15. according to the method for the manufacturing semiconductor device of claim 13, wherein first insulating barrier is to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film laminated construction as the upper strata.
16. according to the method for the manufacturing semiconductor device of claim 14, wherein the thickness of silicon nitride film in first insulating barrier or silicon oxynitride film is 100 to 250nm.
17. according to the method for the manufacturing semiconductor device of claim 15, wherein in first insulating barrier, be 5 to 50nm, and be 70 to 190nm as the thickness of the silicon nitride film on upper strata or silicon oxynitride film as the thickness of the silicon oxide film of lower floor.
18. according to the method for the manufacturing semiconductor device of claim 13, wherein second insulating barrier is a silicon oxide film.
19., be 70 to 190nm wherein as the thickness of the silicon oxide film of second insulating barrier according to the method for the manufacturing semiconductor device of claim 18.
20. according to the method for the manufacturing semiconductor device of claim 13, wherein second insulating barrier is to have silicon oxide film as lower floor and silicon nitride film or the silicon oxynitride film double-layer structure as the upper strata.
21. according to the method for the manufacturing semiconductor device of claim 20, wherein in second insulating barrier, be 5 to 25nm, and be 70 to 190nm as the thickness of the silicon nitride film on upper strata or silicon oxynitride film as the thickness of the silicon oxide film of lower floor.
22. according to the method for the manufacturing semiconductor device of claim 13, wherein the polished amount on interlayer dielectric surface is make the insulator film thickness of winning 5 to 80% also polished.
23. a semiconductor device comprises:
Semiconductor substrate;
Be formed on the gate electrode of Semiconductor substrate top via gate insulating film;
Be formed on pair of source-drain region of locating with the gate electrode both sides on the semiconductor substrate surface;
Be formed on the sidewall spacer on the gate electrode sidewall; And
Be formed on the gate electrode top surface and the lip-deep disilicide layer in source-drain region,
Wherein exist and concern h=5W, T 〉=h, and W 〉=20nm,
Wherein W represents the width of sidewall spacer near contact with gate insulating film, and h represents the height of sidewall spacer, and T represents the height of gate electrode.
24. a semiconductor device comprises:
Semiconductor substrate;
Be formed on the gate electrode of Semiconductor substrate top via gate insulating film;
Be formed on pair of source-drain region of locating with the gate electrode both sides on the semiconductor substrate surface;
Be formed on the sidewall spacer on the gate electrode sidewall; And
Be formed on the gate electrode top surface and the lip-deep disilicide layer in source-drain region,
The thickness that wherein is formed on the disilicide layer on the surface gate electrode is thicker than the thickness that is formed on the lip-deep disilicide layer in source-drain region.
25. semiconductor device according to claim 23, wherein each sidewall spacer all is the double-decker that comprises lower floor and upper strata, this lower floor contacts and is formed by silicon oxide film with the sidewall of gate electrode, and this upper strata is provided at the side-walls of gate electrode via this lower floor and is formed by silicon nitride film or silicon oxynitride film.
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| JP2005116618A JP2006295025A (en) | 2005-04-14 | 2005-04-14 | Semiconductor apparatus and manufacturing method therefor |
| JP2005116618 | 2005-04-14 |
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| US (1) | US20060252196A1 (en) |
| JP (1) | JP2006295025A (en) |
| KR (2) | KR100748906B1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106972015A (en) * | 2015-11-16 | 2017-07-21 | 三星电子株式会社 | Semiconductor devices |
| CN110556293A (en) * | 2018-05-30 | 2019-12-10 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing semiconductor device |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100755671B1 (en) * | 2006-07-14 | 2007-09-05 | 삼성전자주식회사 | A semiconductor device having a uniform nickel alloy silicide layer and method for fabricating the same |
| JP5315779B2 (en) * | 2008-05-09 | 2013-10-16 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
| KR101080200B1 (en) * | 2009-04-14 | 2011-11-07 | 주식회사 하이닉스반도체 | Semiconductor Memory Apparatus and Refresh Control Method of the Same |
Family Cites Families (14)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TW232751B (en) * | 1992-10-09 | 1994-10-21 | Semiconductor Energy Res Co Ltd | Semiconductor device and method for forming the same |
| JP3382743B2 (en) * | 1995-01-27 | 2003-03-04 | 株式会社リコー | Method for manufacturing semiconductor device |
| US6060387A (en) * | 1995-11-20 | 2000-05-09 | Compaq Computer Corporation | Transistor fabrication process in which a contact metallization is formed with different silicide thickness over gate interconnect material and transistor source/drain regions |
| US5731239A (en) * | 1997-01-22 | 1998-03-24 | Chartered Semiconductor Manufacturing Pte Ltd. | Method of making self-aligned silicide narrow gate electrodes for field effect transistors having low sheet resistance |
| JPH11233770A (en) * | 1997-09-02 | 1999-08-27 | Sony Corp | Manufacture of semiconductor device |
| US6306712B1 (en) * | 1997-12-05 | 2001-10-23 | Texas Instruments Incorporated | Sidewall process and method of implantation for improved CMOS with benefit of low CGD, improved doping profiles, and insensitivity to chemical processing |
| JP3168992B2 (en) * | 1998-09-08 | 2001-05-21 | 日本電気株式会社 | Method for manufacturing semiconductor device |
| US20010053572A1 (en) * | 2000-02-23 | 2001-12-20 | Yoshinari Ichihashi | Semiconductor device having opening and method of fabricating the same |
| US6803318B1 (en) * | 2000-09-14 | 2004-10-12 | Cypress Semiconductor Corp. | Method of forming self aligned contacts |
| US6376320B1 (en) * | 2000-11-15 | 2002-04-23 | Advanced Micro Devices, Inc. | Method for forming field effect transistor with silicides of different thickness and of different materials for the source/drain and the gate |
| KR100396469B1 (en) * | 2001-06-29 | 2003-09-02 | 삼성전자주식회사 | Method of forming the gate electrode in semiconductor device and Method of manufacturing the non-volatile memory device comprising the same |
| JP3657915B2 (en) * | 2002-01-31 | 2005-06-08 | 株式会社東芝 | Semiconductor device and manufacturing method of semiconductor device |
| US6657244B1 (en) * | 2002-06-28 | 2003-12-02 | International Business Machines Corporation | Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation |
| JP4057985B2 (en) * | 2003-09-19 | 2008-03-05 | 株式会社東芝 | Manufacturing method of semiconductor device |
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| CN106972015A (en) * | 2015-11-16 | 2017-07-21 | 三星电子株式会社 | Semiconductor devices |
| CN110556293A (en) * | 2018-05-30 | 2019-12-10 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing semiconductor device |
| CN110556293B (en) * | 2018-05-30 | 2024-03-08 | 瑞萨电子株式会社 | Semiconductor device and method of manufacturing the same |
Also Published As
| Publication number | Publication date |
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| JP2006295025A (en) | 2006-10-26 |
| KR20060108537A (en) | 2006-10-18 |
| CN100501948C (en) | 2009-06-17 |
| TWI308779B (en) | 2009-04-11 |
| KR100748906B1 (en) | 2007-08-13 |
| KR20070062957A (en) | 2007-06-18 |
| KR100754262B1 (en) | 2007-09-03 |
| TW200707586A (en) | 2007-02-16 |
| CN101425540A (en) | 2009-05-06 |
| US20060252196A1 (en) | 2006-11-09 |
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