TWI587310B - 非揮發性記憶體的驅動電路 - Google Patents
非揮發性記憶體的驅動電路 Download PDFInfo
- Publication number
- TWI587310B TWI587310B TW105140642A TW105140642A TWI587310B TW I587310 B TWI587310 B TW I587310B TW 105140642 A TW105140642 A TW 105140642A TW 105140642 A TW105140642 A TW 105140642A TW I587310 B TWI587310 B TW I587310B
- Authority
- TW
- Taiwan
- Prior art keywords
- node
- supply voltage
- transistor
- source
- gate
- Prior art date
Links
- 238000010586 diagram Methods 0.000 description 9
- 230000006870 function Effects 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
- H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/12—Programming voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/109—Control signal input circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/326—Application of electric currents or fields, e.g. for electroforming
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0646—PN junctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
- H01L29/0688—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions characterised by the particular shape of a junction between semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
- G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0067—Converter structures employing plural converter units, other than for parallel operation of the units on a single load
- H02M1/007—Plural converter units in cascade
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Geometry (AREA)
- Non-Volatile Memory (AREA)
- Semiconductor Memories (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Read Only Memory (AREA)
- Dc-Dc Converters (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
- Electronic Switches (AREA)
Description
本發明是有關於一種驅動電路,且特別是有關於一種運用於非揮發性記憶體的驅動電路。
眾所周知,非揮發性記憶體可在電源消失之後,仍可保存資料,因此非揮發性記憶體已經廣泛的運用於電子產品中。再者,非揮發性記憶體中包括多個非揮發性記憶胞(non-volatile cell)排列而成非揮發性記憶胞陣列(non-volatile cell array),而每個非揮發性記憶胞中皆包含一浮動閘電晶體(floating gate transistor)。
請參照第1圖,其所繪示為揮發性記憶體示意圖。非揮發性記憶體中包括一非揮發性記憶胞陣列110與一驅動電路(driving circuit)120。其中,驅動電路120連接至非揮發性記憶胞陣列110,且驅動電路120可在各種運作模式下提供各種驅動信號OUT至非揮發性記憶胞陣列110。
舉例來說,根據非揮發性記憶胞陣列的運作模式,驅動電路120提供適當的驅動信號OUT來操控非揮發性記憶胞陣
列110進行讀取運作(read operation)或者編程運作(program operation)。
本發明之主要目的係提出一種非揮發性記憶體中的驅動電路,可在高溫的環境下,穩定地提供驅動信號至非揮發性記憶胞陣列。
本發明係有關於一種驅動電路,包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2;一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至一第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;其中,該節點b2產生一驅動信號;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓、汲極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極
連接至一第四供應電壓;一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓;一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該第四節點;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該第二節點。
本發明係有關於一種驅動電路,包括:一第一驅動器,包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2;一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極與體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至一第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓(Vpp3)、汲
極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極連接至一第四供應電壓;一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓;一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該第四節點;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該第二節點;一第一切換電路,連接於該節點b2與一第一輸出端之間;以及一第二驅動器,連接於該第一輸出端,且該第一輸出端產生一第一輸出信號。
為了對本發明之上述及其他方面有更佳的瞭解,下文特舉較佳實施例,並配合所附圖式,作詳細說明如下:
110‧‧‧非揮發性記憶胞陣列
120、200、300‧‧‧驅動電路
310、320、430、440‧‧‧偏壓電路
400、460、465‧‧‧驅動器
450、455‧‧‧切換電路
第1圖所所繪示為揮發性記憶體示意圖。
第2圖所繪示為本發明的第一實施例非揮發性記憶體的驅動電路。
第3A圖所繪示為本發明的第二實施例運用於非揮發性記憶體的驅動電路。
第3B圖所繪示為本發明第二實施例中的第一偏壓電路。
第3C圖所繪示為本發明第二實施例中的第二偏壓電路。
第4A圖所繪示為本發明的第三實施例運用於非揮發性記憶體的驅動電路。
第4B圖所繪示為本發明第三實施例中的第三偏壓電路。
第4C圖所繪示為本發明第三實施例中的第四偏壓電路。
第4D圖所繪示為本發明第三實施例驅動電路運作於各種模式時的真值表。
請參照第2圖,其所繪示為本發明的第一實施例非揮發性記憶體的驅動電路。驅動電路200可提供一驅動信號OUT至非揮發性記憶胞陣列(未繪示)。
驅動電路200包括:包括多個p型電晶體m1~m8,以及多個n型電晶體m9~m12。其中,電晶體m1~m4的體極(body terminal)連接至第一供應電壓Vpp1,電晶體m9~m12的體極連接至第四供應電壓Vnn,第一供應電壓Vpp1有最高的電壓值,第四供應電壓Vnn有最低的電壓值。
電晶體m1源極連接至第一供應電壓Vpp1、閘極連接至節點b2、汲極連接至節點a1;電晶體m2源極連接至第一供應電壓Vpp1、閘極連接至節點a2、汲極連接至節點b1;電晶體m3源極連接至第二供應電壓Vpp2、閘極與汲極連接至節點a1;電晶體m4源極連接至第二供應電壓Vpp2、閘極與汲極連接至節
點b1;電晶體m5源極與體極連接至節點a1、閘極連接至第二供應電壓Vpp2、汲極連接至節點a2;電晶體m6源極與體極連接至節點b1、閘極連接至第二供應電壓Vpp2、汲極連接至節點b2;其中,第二供應電壓Vpp2小於等於第一供應電壓Vpp1,且節點b2可產生驅動信號OUT。
再者,電晶體m7源極與體極連接至節點a2、閘極連接至第三供應電壓Vpp3、汲極連接至節點a3;電晶體m8源極與體極連接至節點b2、閘極連接至第三供應電壓Vpp3、汲極連接至節點b3;其中,第三供應電壓Vpp3小於等於第二供應電壓Vpp2。
電晶體m9汲極連接至節點a3、閘極連接至第三供應電壓Vpp3、源極連接至節點a4;電晶體m10汲極連接至節點b3、閘極連接至第三供應電壓Vpp3、源極連接至節點b4;電晶體m11汲極連接至節點a4、閘極連接至輸入信號IN、源極連接至第四供電壓Vnn;電晶體m12汲極連接至節點b4、閘極連接至反相的輸入信號INb、源極連接至第五供應電壓Vpr。其中,第五供應電壓Vpr小於等於第三供應電壓Vpp3,且第五供應電壓Vpr大於等於第四供應電壓Vnn。
舉例來說,第一供應電壓Vpp1為為非揮發性記憶體的編程電壓(program voltage),例如9V。第二供應電壓Vpp2為6V。第三供應電壓Vpp3為4.5V。第四供應電壓Vnn為0V。第五供應電壓Vpr為非揮發性記憶體的讀取電壓,例如1.5V。
基本上,第一實施例的驅動電路200操作在高溫的環境時,例如150℃~250℃。由於在操作的過程,節點a2或者b2可能會呈現浮接的狀態。舉例來說,於節點b2呈現浮接狀態時,電晶體m6的源極與汲極之間的電壓差(voltage difference)可能超過其安全運作區(safe operation area,簡稱SOA)。同理,電晶體m1的源極與閘極之間的電壓差也可能超過其安全運作區。另外,當電晶體m1、m6超過安全運作區後,會導致漏電流(leakage current)增加,進而影響供應電壓與驅動信號OUT,並使得非揮發性記憶胞陣列無法正常運作。
請參照第3A圖,其所繪示為本發明的第二實施例運用於非揮發性記憶體的驅動電路。與第一實施例的差異在於,第二實施例的驅動電路300中,增加一第一偏壓電路310與第二偏壓電路320分別連接至節點a2與b2。第一偏壓電路310可提供一特定電壓於節點a2,使得節點a2不會呈現浮接狀態。同理,第二偏壓電路320可提供一特定電壓於節點b2,使得節點b2不會呈現浮接狀態。
請參照第3B圖,其所繪示為本發明第二實施例中的第一偏壓電路。請參照第3C圖,其所繪示為本發明第二實施例中的第二偏壓電路。
第一偏壓電路310:包括p型電晶體m13與m14。電晶體m13源極連接至節點a2,閘極接收控制信號C1;以及,電晶體m14源極連接至電晶體m13汲極,閘極接收控制信號C1,
汲極接收特定電壓B1。根據本發明的實施例,控制信號C1為節點a3上的電壓,特定電壓B1為第三供應電壓Vpp3。亦即,電晶體m13與m14的閘極連接至節點a3,電晶體m14汲極連接至電晶體m9的閘極。因此,第一偏壓電路310可提供第三供應電壓Vpp3於節點a2。
第二偏壓電路320:包括p型電晶體m15與m16。電晶體m15源極連接至節點b2,閘極接收控制信號D1;以及,電晶體m16源極連接至電晶體m15汲極,閘極接收控制信號D1,汲極接收特定電壓B1。根據本發明的實施例,控制信號D1為節點b3上的電壓,特定電壓B1為第三供應電壓Vpp3。亦即,電晶體m15與m16的閘極連接至節點b3,電晶體m16汲極連接至電晶體m10的閘極。因此,第二偏壓電路320可提供第三供應電壓Vpp3於節點b2。
另外,在電晶體m13~m16可以順利運作的考量下,電晶體m13的體極與源極可以相互連接,而電晶體m14~m16也是相同的連接方式。或者,可將電晶體m13~m16的體極連接至第一供應電壓Vpp1或者其他的偏壓電壓(biasing voltage)。
以下以節點a2來做說明,當輸入信號IN為高邏輯準位且反相的輸入信號INb為低邏輯準位時,節點a3為第四供應電壓Vnn,亦即控制信號C1為第四供應電壓Vnn。再者,節點b2與b3為第一供應電壓Vpp1,亦即控制信號D1為第一供應電壓Vpp1,第二偏壓電路320不會運作。再者,由於控制信號
C1為第四供應電壓Vnn,使得第一偏壓電路310中電晶體m13與m14開啟,並且第三供應電壓Vpp3提供至節點a2。其中,高邏輯準位為Vdd,例如3.3V,低邏輯準位為接地電壓,例如0V。
反之,當輸入信號IN為低邏輯準位且反相的輸入信號INb為高邏輯準位時,節點a2與a3為第一供應電壓Vpp1,第一偏壓電路310不會運作。再者,節點b3為第五供應電壓Vpr,使得第二偏壓電路320中電晶體m15與m16開啟,節點b2即為第三供應電壓Vpp3。
由以上的說明可知,第二實施例的驅動電路300可以使得節點a2不會呈現浮接狀態。同理,第二實施例的驅動電路300也可以使得節點b2不會呈現浮接狀態。
請參照第4A圖,其所繪示為本發明的第三實施例運用於非揮發性記憶體的驅動電路。第三實施例的驅動電路包括一第一驅動器(driver)400、一第二驅動器460、一第三驅動器465、一第一切換電路(switching circuit)450與一第二切換電路455。其中,第一驅動器400與第二實施例之驅動電路300完全相同,此處不再贅述。
相較於第二實施例,第三實施例增加了第一切換電路450、第二切換電路455、第二驅動器460與第三驅動器465。其中,第一切換電路450連接於節點b2與一第一輸出端之間,且第一輸出端可產生第一輸出信號OUT1。第二切換電路455連接於節點b2與一第二輸出端之間,且第二輸出端可產生第二輸
出信號OUT2。再者,第二驅動器460連接至第一輸出端;第三驅動器465連接至第二輸出端。
第一切換電路450中,電晶體m17~m19係作為開關的用途。其中,電晶體m17源極接收驅動信號OUT、體極連接至源極、閘極接收模式信號(mode signal)M1、汲極連接至節點x1;電晶體m18源極連接至節點x1、體極連接至源極、閘極接收第二供應電壓Vpp2、汲極連接至節點x2;電晶體m19源極連接至節點x2、體極連接至源極、閘極接第三供應電壓Vpp3、汲極連接至第一輸出端以產生第一輸出信號OUT1。
第二驅動器460包括n型電晶體m20~m22,電晶體m20~m22的體極皆連接至第四供應電壓Vnn。電晶體m20汲極連接至第一輸出端以產生第一輸出信號OUT1,閘極接收第三供應電壓Vpp3;電晶體m21汲極連接至電晶體m20源極、閘極接收反相的輸入信號INb、源極連接至第五供應電壓Vpr;電晶體m22極汲極連接至電晶體m20源極、閘極接收模式信號M2、源極連接至第五供應電壓Vpr。
同理,為了防止節點x1與x2在驅動電路運作的過程呈現浮接狀態,本發明更提供一第三偏壓電路430連接於節點x1,以及提供一第四偏壓電路440連接於節點x2。
第二切換電路455中,電晶體m26係作為開關的用途。其中,電晶體m26源極接收驅動信號OUT、體極連接至源極、閘極接收第三供應電壓Vpp3、汲極連接至第二輸出端以產生第二
輸出信號OUT2。
第三驅動器465包括n型電晶體m27、m28,電晶體m27、28的體極皆連接至第四供應電壓Vnn。電晶體m27汲極連接至第二輸出端以產生第二輸出信號OUT2,閘極接收第三供應電壓Vpp3;電晶體m28汲極連接至電晶體m27源極、閘極接收反相的輸入信號INb、源極連接至第五供應電壓Vpr。
請參照第4B圖,其所繪示為本發明第三實施例中的第三偏壓電路。請參照第4C圖,其所繪示為本發明第三實施例中的第四偏壓電路。
第三偏壓電路430:包括p型電晶體m23。電晶體m23源極連接接收特定電壓B2、閘極與汲極皆連接至節點x1,體極連接至第一供應電壓Vpp1。根據本發明的實施例,特定電壓B2為第二供應電壓Vpp2。因此,第三偏壓電路430可供應(Vpp2-|Vthp|)至節點x1。其中,Vthp為電晶體m23的臨限電壓(threshold voltage)。
第四偏壓電路440:包括p型電晶體m24與m25。電晶體m24源極連接至節點x2,閘極接收第一輸出信號OUT1;以及,電晶體m25源極連接至電晶體m24汲極,閘極接收第一輸出信號OUT1,汲極接收特定電壓B3。根據本發明的實施例,特定電壓B3為第三供應電壓Vpp3。因此,第四偏壓電路440可提供第三供應電壓Vpp3於節點x2。
請參照第4D圖,其所繪示為本發明第三實施例驅
動電路運作於各種模式時的真值表。
其中,於第一模式時,模式信號M1為Vpp1,模式信號M2為Vdd;於第二模式時,模式信號M1與M2為0V;或者,於第二模式時,模式信號M1也可以是第三供應電壓Vp3用以降低電晶體m17的電壓應力(stress)。
在第一情況下,驅動電路處於第一模式、輸入信號IN為Vdd且反相的輸入信號INb為0V時,節點a2為第三供應電壓Vpp3、節點b2為第一供應電壓Vpp1、節點x1為(Vpp2-|Vthp|)、x2為第三供應電壓Vpp3、第一輸出信號OUT1為第五供應電壓Vpr。且第二輸出信號OUT2為第一供應電壓Vp1。
在第二情況下,驅動電路處於第二模式、輸入信號IN為Vdd且反相的輸入信號INb為0V時,節點a2為第三供應電壓Vpp3、節點b2為第一供應電壓Vpp1、節點x1、x2與第一輸出信號OUT1皆為第一供應電壓Vpp1。且第二輸出信號OUT2為第一供應電壓Vp1。
在第三情況下,驅動電路處於第一模式、輸入信號IN為0V且反相的輸入信號INb為Vdd時,節點a2為第一供應電壓Vpp1、節點b2為第三供應電壓Vpp3、節點x1為(Vpp2-|Vthp|)、x2為第三供應電壓Vpp3、第一輸出信號OUT1為第五供應電壓Vpr。且第二輸出信號OUT2為第五供應電壓Vpr。
在第四情況下,驅動電路處於第二模式、輸入信號IN為0V且反相的輸入信號INb為Vdd時,節點a2為第一供應
電壓Vpp1、節點b2為第三供應電壓Vpp3、節點x1為(Vpp2-|Vthp|)、節點x2為第三供應電壓Vpp3,第一輸出信號OUT1為第五供應電壓Vpr。且第二輸出信號OUT2為第五供應電壓Vpr。
由以上的說明可知,本發明第二實施例與第三實施例的驅動電路確實可以讓節點不會呈現浮接狀態。因此,第二實施例與第三實施例的驅動電路可以穩定地操作在高溫的環境,並使得非揮發性記憶胞陣列正常運作。
再者,在此技術領域的技術人員也可以對本發明進行修改並達成本發明所教示的功能。舉例來說,驅動電路可以修改為僅有第一驅動器、第二驅動器與第一切換電路。而驅動電路僅輸出第一輸出信號OUT1。而省略輸出第二驅動信號OUT2的第三驅動器與第二切換電路。
綜上所述,雖然本發明已以較佳實施例揭露如上,然其並非用以限定本發明。本發明所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作各種之更動與潤飾。因此,本發明之保護範圍當視後附之申請專利範圍所界定者為準。
310、320、430、440‧‧‧偏壓電路
400、460、465‧‧‧驅動器
450、455‧‧‧切換電路
Claims (19)
- 一種驅動電路,連接至一非揮發性記憶胞陣列,該驅動電路包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2;一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極連接至一第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極連接至該第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至該第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;其中,該節點b2產生一驅動信號;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓、汲極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極連接至一第四供應電壓; 一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓;一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該節點a2;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該節點b2。
- 如申請專利範圍第1項所述之驅動電路,其中該第一偏壓電路包括:一第十三電晶體,閘極連接至該節點a3、源極連接至該節點a2;以及一第十四電晶體,源極連接至該第十三電晶體的汲極、閘極連接至該節點a3、汲極連接至該第三供應電壓。
- 如申請專利範圍第2項所述之驅動電路,其中該第二偏壓電路包括:一第十五電晶體,閘極連接至該節點b3、源極連接至該節點 b2;以及一第十六電晶體,源極連接至該第十五電晶體的汲極、閘極連接至該節點b3、汲極連接至該第三供應電壓。
- 如申請專利範圍第3項所述之驅動電路,其中該第十三電晶體的體極與源極相互連接,該第十四電晶體的體極與源極相互連接,該第十五電晶體的體極與源極相互連接,該第十六電晶體的體極與源極相互連接。
- 如申請專利範圍第3項所述之驅動電路,其中該第十三電晶體、該第十四電晶體、該第十五電晶體與該第十六電晶體的體極連接至一偏壓電壓。
- 如申請專利範圍第1項所述之驅動電路,其中該第一供應電壓大於等於該第二供應電壓,該第二供應電壓大於等於該第三供應電壓,該第三供應電壓大於該第四供應電壓。
- 一種驅動電路,連接至一非揮發性記憶胞陣列,該驅動電路包括:一第一驅動器,包括:一第一電晶體,其源極與體極連接至一第一供應電壓,汲極連接至一節點a1、閘極連接至一節點b2; 一第二電晶體,其源極與體極連接至該第一供應電壓,汲極連接至一節點b1、閘極連接至一節點a2;一第三電晶體,其源極連接至一第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點a1;一第四電晶體,其源極連接至該第二供應電壓,體極連接至該第一供應電壓,汲極與閘極連接至該節點b1;一第五電晶體,其源極與體極連接至該節點a1,閘極連接至該第二供應電壓、汲極連接至該節點a2;一第六電晶體,其源極與體極連接至該節點b1,閘極連接至該第二供應電壓、汲極連接至該節點b2;一第七電晶體,其源極與體極連接至該節點a2,閘極連接至一第三供應電壓、汲極連接至一節點a3;一第八電晶體,其源極與體極連接至該節點b2,閘極連接至該第三供應電壓、汲極連接至一節點b3;一第九電晶體,其汲極連接至該節點a3、閘極連接至該第三供應電壓、源極連接至一節點a4、體極連接至一第四供應電壓;一第十電晶體,其汲極連接至該節點b3、閘極連接至該第三供應電壓、源極連接至一節點b4、體極連接至該第四供應電壓;一第十一電晶體,其汲極連接至該節點a4、閘極接收一輸入信號、源極與體極連接至該第四供應電壓; 一第十二電晶體,其汲極連接至該節點b4、閘極接收一反相的輸入信號、源極連接至一第五供應電壓、體極連接至該第四供應電壓;一第一偏壓電路,連接至該節點a2並提供一特定電壓至該節點a2;以及一第二偏壓電路,連接至該節點b2並提供該特定電壓至該節點b2;一第一切換電路,連接於該節點b2與一第一輸出端之間;以及一第二驅動器,連接於該第一輸出端,且該第一輸出端產生一第一輸出信號。
- 如申請專利範圍第7項所述之驅動電路,其中該第一偏壓電路包括:一第十三電晶體,閘極連接至該節點a3、源極連接至該節點a2;以及一第十四電晶體,源極連接至該第十三電晶體的汲極、閘極連接至該節點a3、汲極連接至該第三供應電壓。
- 如申請專利範圍第8項所述之驅動電路,其中該第二偏壓電路包括:一第十五電晶體,閘極連接至該節點b3、源極連接至該節點 b2;以及一第十六電晶體,源極連接至該第十五電晶體的汲極、閘極連接至該節點b3、源極連接至該第三供應電壓。
- 如申請專利範圍第9項所述之驅動電路,其中該第十三電晶體的體極與源極相互連接,該第十四電晶體的體極與源極相互連接,該第十五電晶體的體極與源極相互連接,該第十六電晶體的體極與源極相互連接。
- 如申請專利範圍第9項所述之驅動電路,其中該第十三電晶體、該第十四電晶體、該第十五電晶體與該第十六電晶體的體極連接至一偏壓電壓。
- 如申請專利範圍第7項所述之驅動電路,其中該第一供應電壓大於等於該第二供應電壓,該第二供應電壓大於等於該第三供應電壓,該第三供應電壓大於該第四供應電壓。
- 如申請專利範圍第7項所述之驅動電路,其中該第一切換電路包括:一第十七電晶體,其源極與體極連接至該節點b2、閘極接收一第一模式信號、汲極連接至一節點x1;一第十八電晶體,其源極與體極連接至該節點x1、閘極接收 該第二供應電壓、汲極連接至一節點x2;一第十九電晶體,其源極與體極連接至該節點x2、閘極接收該第三供應電壓、汲極連接至該第一輸出端;一第三偏壓電路,連接至該節點x1;以及一第四偏壓電路,連接至該節點x2。
- 如申請專利範圍第13項所述之驅動電路,其中該第二驅動器包括:一第二十電晶體,汲極連接至該第一輸出端、閘極連接至該第三供應電壓、體極連接至該第四供應電壓;一第二十一電晶體,汲極連接至該第二十電晶體的源極、閘極接收該反相的輸入信號、體極連接至該第四供應電壓、源極連接至該第五供應電壓;以及一第二十二電晶體,汲極連接至該第二十電晶體的源極、閘極接收一第二模式信號、體極連接至該第四供應電壓、源極連接至該第五供應電壓。
- 如申請專利範圍第13項所述之驅動電路,其中該第三偏壓電路包括:一第二十三電晶體,源極連接至該第二供應電壓、閘極與汲極連接至該節點x1、體極連接至該第一供應電壓。
- 如申請專利範圍第15項所述之驅動電路,其中該第四偏壓電路包括:一第二十四電晶體,源極連接至該節點x2、閘極連接至該第一輸出端;一第二十五電晶體,源極連接至該第二十四電晶體的汲極、閘極連接至該第一輸出端、汲極連接至該第三供應電壓。
- 如申請專利範圍第7項所述之驅動電路,更包括:一第二切換電路,連接於該節點b2與一第二輸出端之間;以及一第三驅動器,連接於該第二輸出端,且該第二輸出端產生一第二輸出信號。
- 如申請專利範圍第17項所述之驅動電路,其中該第二切換電路包括:一第二十六電晶體,其源極與體極連接至該節點b2、閘極接收該第三供應電壓、汲極連接至該第二輸出端。
- 如申請專利範圍第17項所述之驅動電路,其中該第三驅動器包括:一第二十七電晶體,汲極連接至該第二輸出端、閘極連接至該第三供應電壓、體極連接至該第四供應電壓; 一第二十八電晶體,汲極連接至該第二十七電晶體的源極、閘極接收該反相的輸入信號、體極連接至該第四供應電壓、源極連接至該第五供應電壓。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201662362068P | 2016-07-14 | 2016-07-14 | |
US62/362,068 | 2016-07-14 |
Publications (2)
Publication Number | Publication Date |
---|---|
TWI587310B true TWI587310B (zh) | 2017-06-11 |
TW201810260A TW201810260A (zh) | 2018-03-16 |
Family
ID=57909468
Family Applications (5)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105140642A TWI587310B (zh) | 2016-07-14 | 2016-12-08 | 非揮發性記憶體的驅動電路 |
TW105142017A TWI593221B (zh) | 2016-07-14 | 2016-12-19 | 電荷幫浦裝置 |
TW105143779A TWI637489B (zh) | 2016-07-14 | 2016-12-29 | 半導體製程方法 |
TW106127876A TW201906140A (zh) | 2016-07-14 | 2017-08-17 | 具有uv透射窗的uv可抹除記憶體元件及其製作方法 |
TW106132048A TWI649858B (zh) | 2016-07-14 | 2017-09-19 | 非揮發性記憶體及其製作方法 |
Family Applications After (4)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW105142017A TWI593221B (zh) | 2016-07-14 | 2016-12-19 | 電荷幫浦裝置 |
TW105143779A TWI637489B (zh) | 2016-07-14 | 2016-12-29 | 半導體製程方法 |
TW106127876A TW201906140A (zh) | 2016-07-14 | 2017-08-17 | 具有uv透射窗的uv可抹除記憶體元件及其製作方法 |
TW106132048A TWI649858B (zh) | 2016-07-14 | 2017-09-19 | 非揮發性記憶體及其製作方法 |
Country Status (4)
Country | Link |
---|---|
US (3) | US9633734B1 (zh) |
JP (2) | JP6316393B2 (zh) |
CN (4) | CN107623438B (zh) |
TW (5) | TWI587310B (zh) |
Families Citing this family (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9882566B1 (en) * | 2017-01-10 | 2018-01-30 | Ememory Technology Inc. | Driving circuit for non-volatile memory |
KR102423675B1 (ko) * | 2017-09-22 | 2022-07-22 | 주식회사 디비하이텍 | 레벨 쉬프터, 및 이를 포함하는 소스 드라이버, 게이트 드라이버, 및 디스플레이 장치 |
US10797063B2 (en) * | 2018-01-10 | 2020-10-06 | Ememory Technology Inc. | Single-poly nonvolatile memory unit |
US10461635B1 (en) * | 2018-05-15 | 2019-10-29 | Analog Devices Global Unlimited Company | Low VIN high efficiency chargepump |
CN109887839A (zh) * | 2019-03-01 | 2019-06-14 | 上海华力微电子有限公司 | 一种改善闪存器件数据保存能力的方法 |
US10818592B1 (en) * | 2019-04-29 | 2020-10-27 | Nanya Technology Corporation | Semiconductor memory device including decoupling capacitor array arranged overlying one-time programmable device |
US11508719B2 (en) * | 2019-05-13 | 2022-11-22 | Ememory Technology Inc. | Electrostatic discharge circuit |
CN112447739B (zh) * | 2019-09-02 | 2023-09-19 | 联芯集成电路制造(厦门)有限公司 | 半导体存储装置 |
US11424257B2 (en) * | 2019-10-15 | 2022-08-23 | Ememory Technology Inc. | Method for manufacturing semiconductor structure and capable of controlling thicknesses of oxide layers |
TWI765643B (zh) | 2021-04-06 | 2022-05-21 | 華邦電子股份有限公司 | 記憶體元件及其製造方法 |
US20220367651A1 (en) * | 2021-05-12 | 2022-11-17 | Ememory Technology Inc. | Stacked-gate non-volatile memory cell |
TWI802971B (zh) * | 2021-08-23 | 2023-05-21 | 旺宏電子股份有限公司 | 記憶體晶胞,記憶體裝置之製造方法及其操作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7446564B2 (en) * | 2004-01-15 | 2008-11-04 | Via Technologies, Inc. | Level shifter |
US7501856B2 (en) * | 2005-09-20 | 2009-03-10 | Via Technologies, Inc. | Voltage level shifter |
US8373485B2 (en) * | 2011-04-20 | 2013-02-12 | Ememory Technology Inc. | Voltage level shifting apparatus |
US8653878B2 (en) * | 2011-10-19 | 2014-02-18 | Ememory Technology Inc. | Voltage switch circuit produced by logic circuit manufacturing process capable of withstanding high voltage stress |
Family Cites Families (56)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5625544A (en) * | 1996-04-25 | 1997-04-29 | Programmable Microelectronics Corp. | Charge pump |
JPH09297997A (ja) * | 1996-05-02 | 1997-11-18 | Toshiba Corp | 不揮発性半導体記憶装置 |
KR100235958B1 (ko) * | 1996-08-21 | 1999-12-15 | 김영환 | 반도체 메모리 장치의 복수 레벨 전압 발생기 |
US6487687B1 (en) * | 1997-01-02 | 2002-11-26 | Texas Instruments Incorporated | Voltage level shifter with testable cascode devices |
US5963061A (en) * | 1997-04-08 | 1999-10-05 | Micron Technology, Inc. | Switch for minimizing transistor exposure to high voltage |
JP2978467B2 (ja) * | 1998-03-16 | 1999-11-15 | 株式会社日立製作所 | 半導体集積回路装置の製造方法 |
JP3223504B2 (ja) * | 1998-03-31 | 2001-10-29 | 日本電気株式会社 | 昇圧回路 |
JP3446644B2 (ja) * | 1999-01-07 | 2003-09-16 | 日本電気株式会社 | 単一電子メモリ素子の駆動回路及びその駆動方法 |
CN1138333C (zh) * | 1999-02-02 | 2004-02-11 | 旺宏电子股份有限公司 | 电荷泵及其集成电路以及减小电荷泵的峰值电流的方法 |
US6370071B1 (en) * | 2000-09-13 | 2002-04-09 | Lattice Semiconductor Corporation | High voltage CMOS switch |
US6914791B1 (en) * | 2002-11-06 | 2005-07-05 | Halo Lsi, Inc. | High efficiency triple well charge pump circuit |
CN1282238C (zh) * | 2003-03-24 | 2006-10-25 | 旺宏电子股份有限公司 | 半导体工序 |
CN1302536C (zh) * | 2003-06-04 | 2007-02-28 | 旺宏电子股份有限公司 | 虚接地阵列的混合信号嵌入式屏蔽只读存储器及其制造方法 |
CN1291481C (zh) * | 2003-08-12 | 2006-12-20 | 旺宏电子股份有限公司 | 具牺牲层的嵌入式非挥发性存储器的制造方法 |
US7145370B2 (en) | 2003-09-05 | 2006-12-05 | Impinj, Inc. | High-voltage switches in single-well CMOS processes |
US6980045B1 (en) * | 2003-12-05 | 2005-12-27 | Xilinx, Inc. | Merged charge pump |
US7580311B2 (en) | 2004-03-30 | 2009-08-25 | Virage Logic Corporation | Reduced area high voltage switch for NVM |
JP2005347589A (ja) * | 2004-06-04 | 2005-12-15 | Matsushita Electric Ind Co Ltd | 不揮発性半導体記憶装置及びその製造方法 |
JP4967237B2 (ja) * | 2005-01-28 | 2012-07-04 | パナソニック株式会社 | 固体撮像装置 |
US7671401B2 (en) | 2005-10-28 | 2010-03-02 | Mosys, Inc. | Non-volatile memory in CMOS logic process |
KR100660903B1 (ko) * | 2005-12-23 | 2006-12-26 | 삼성전자주식회사 | 프로그래밍 속도를 개선한 이이피롬, 이의 제조 방법 및이의 동작 방법 |
US20080169500A1 (en) * | 2007-01-16 | 2008-07-17 | Atmel Corporation | Low voltage non-volatile memory cell with shared injector for floating gate |
JP2008198985A (ja) * | 2007-01-17 | 2008-08-28 | Matsushita Electric Ind Co Ltd | 昇圧回路 |
JP2008253031A (ja) * | 2007-03-29 | 2008-10-16 | Univ Waseda | チャージポンプ回路 |
CN101315934B (zh) * | 2007-05-31 | 2012-06-27 | 联华电子股份有限公司 | 增进照光效能的内嵌式光抹除存储器及其制造方法 |
JP4969322B2 (ja) * | 2007-06-01 | 2012-07-04 | 三菱電機株式会社 | 電圧発生回路およびそれを備える画像表示装置 |
US7880274B2 (en) * | 2007-06-25 | 2011-02-01 | Macronix International Co., Ltd. | Method of enabling alignment of wafer in exposure step of IC process after UV-blocking metal layer is formed over the whole wafer |
US7968926B2 (en) * | 2007-12-19 | 2011-06-28 | Taiwan Semiconductor Manufacturing Company, Ltd. | Logic non-volatile memory cell with improved data retention ability |
JP5259270B2 (ja) * | 2008-06-27 | 2013-08-07 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
TWI376097B (en) * | 2008-09-18 | 2012-11-01 | Ili Technology Corp | Level shift circuit |
US8222130B2 (en) * | 2009-02-23 | 2012-07-17 | Globalfoundries Singapore Pte. Ltd. | High voltage device |
US8053319B2 (en) * | 2009-02-23 | 2011-11-08 | Globalfoundries Singapore Pte. Ltd. | Method of forming a high voltage device |
US9184097B2 (en) * | 2009-03-12 | 2015-11-10 | System General Corporation | Semiconductor devices and formation methods thereof |
JP5494252B2 (ja) * | 2009-09-11 | 2014-05-14 | ソニー株式会社 | 同期発振器、クロック再生装置、クロック分配回路、およびマルチモード注入回路 |
JP2011192363A (ja) * | 2010-03-16 | 2011-09-29 | Seiko Epson Corp | 電源切換回路、不揮発性記憶装置、集積回路装置及び電子機器 |
CN101969305B (zh) * | 2010-11-09 | 2012-09-05 | 威盛电子股份有限公司 | 电位转换电路 |
JP5638408B2 (ja) * | 2011-01-28 | 2014-12-10 | ルネサスエレクトロニクス株式会社 | 半導体装置及び半導体装置の製造方法 |
US20120309155A1 (en) * | 2011-06-03 | 2012-12-06 | Nanya Technology Corporation | Semiconductor process |
WO2013095500A1 (en) | 2011-12-22 | 2013-06-27 | Intel Corporation | High-voltage level-shifter |
CN102543891B (zh) * | 2012-01-05 | 2014-09-03 | 复旦大学 | 栅控二极管半导体存储器器件的制备方法 |
US8658495B2 (en) | 2012-03-08 | 2014-02-25 | Ememory Technology Inc. | Method of fabricating erasable programmable single-poly nonvolatile memory |
US8772854B2 (en) * | 2012-04-02 | 2014-07-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multiple-time programming memory cells and methods for forming the same |
WO2013149669A1 (en) * | 2012-04-05 | 2013-10-10 | X-Fab Semiconductor Foundries Ag | A method of fabricating a tunnel oxide layer and a tunnel oxide layer for a semiconductor device |
CN102663980B (zh) * | 2012-04-13 | 2014-10-29 | 北京京东方光电科技有限公司 | 一种栅极驱动电路的控制电路及其工作方法、液晶显示器 |
US8796098B1 (en) * | 2013-02-26 | 2014-08-05 | Cypress Semiconductor Corporation | Embedded SONOS based memory cells |
US9041089B2 (en) * | 2013-06-07 | 2015-05-26 | Ememory Technology Inc. | Nonvolatile memory structure |
US9013229B2 (en) * | 2013-07-15 | 2015-04-21 | Texas Instruments Incorporated | Charge pump circuit |
CN103631723B (zh) * | 2013-11-29 | 2017-02-01 | 中国电子科技集团公司第四十七研究所 | 调节电路及电路调节方法 |
US9082500B1 (en) * | 2014-01-10 | 2015-07-14 | Ememory Technology Inc. | Non-volatile memory |
US9508396B2 (en) * | 2014-04-02 | 2016-11-29 | Ememory Technology Inc. | Array structure of single-ploy nonvolatile memory |
US20160006348A1 (en) * | 2014-07-07 | 2016-01-07 | Ememory Technology Inc. | Charge pump apparatus |
US9431111B2 (en) * | 2014-07-08 | 2016-08-30 | Ememory Technology Inc. | One time programming memory cell, array structure and operating method thereof |
TWI593052B (zh) * | 2015-01-07 | 2017-07-21 | 力旺電子股份有限公司 | 半導體元件及其製造方法 |
KR102340550B1 (ko) * | 2015-04-10 | 2021-12-21 | 에스케이하이닉스 주식회사 | 전원 제어장치 |
US9847133B2 (en) * | 2016-01-19 | 2017-12-19 | Ememory Technology Inc. | Memory array capable of performing byte erase operation |
US9728260B1 (en) * | 2016-04-28 | 2017-08-08 | United Microelectronics Corp. | Light-erasable embedded memory device and method of manufacturing the same |
-
2016
- 2016-11-10 US US15/348,369 patent/US9633734B1/en active Active
- 2016-12-06 JP JP2016236457A patent/JP6316393B2/ja active Active
- 2016-12-08 TW TW105140642A patent/TWI587310B/zh active
- 2016-12-19 TW TW105142017A patent/TWI593221B/zh active
- 2016-12-29 TW TW105143779A patent/TWI637489B/zh active
-
2017
- 2017-01-11 CN CN201710019400.0A patent/CN107623438B/zh active Active
- 2017-01-26 CN CN201710061448.8A patent/CN107622782B/zh active Active
- 2017-02-03 CN CN201710063562.4A patent/CN107634059B/zh active Active
- 2017-02-24 JP JP2017033413A patent/JP6389294B2/ja active Active
- 2017-06-22 US US15/630,927 patent/US20180019250A1/en not_active Abandoned
- 2017-07-13 US US15/648,464 patent/US10103157B2/en active Active
- 2017-08-17 TW TW106127876A patent/TW201906140A/zh unknown
- 2017-08-24 CN CN201710737673.9A patent/CN109119377A/zh active Pending
- 2017-09-19 TW TW106132048A patent/TWI649858B/zh active
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7446564B2 (en) * | 2004-01-15 | 2008-11-04 | Via Technologies, Inc. | Level shifter |
US7501856B2 (en) * | 2005-09-20 | 2009-03-10 | Via Technologies, Inc. | Voltage level shifter |
US8373485B2 (en) * | 2011-04-20 | 2013-02-12 | Ememory Technology Inc. | Voltage level shifting apparatus |
US8653878B2 (en) * | 2011-10-19 | 2014-02-18 | Ememory Technology Inc. | Voltage switch circuit produced by logic circuit manufacturing process capable of withstanding high voltage stress |
Also Published As
Publication number | Publication date |
---|---|
CN107622782B (zh) | 2020-07-14 |
TW201906140A (zh) | 2019-02-01 |
TWI637489B (zh) | 2018-10-01 |
JP6316393B2 (ja) | 2018-04-25 |
TW201803259A (zh) | 2018-01-16 |
CN107634059A (zh) | 2018-01-26 |
TW201803090A (zh) | 2018-01-16 |
TWI649858B (zh) | 2019-02-01 |
JP6389294B2 (ja) | 2018-09-12 |
CN107623438A (zh) | 2018-01-23 |
US20180019252A1 (en) | 2018-01-18 |
CN109119377A (zh) | 2019-01-01 |
CN107634059B (zh) | 2019-12-20 |
CN107622782A (zh) | 2018-01-23 |
TWI593221B (zh) | 2017-07-21 |
US20180019250A1 (en) | 2018-01-18 |
US9633734B1 (en) | 2017-04-25 |
CN107623438B (zh) | 2019-10-25 |
TW201810260A (zh) | 2018-03-16 |
JP2018010708A (ja) | 2018-01-18 |
TW201909392A (zh) | 2019-03-01 |
US10103157B2 (en) | 2018-10-16 |
JP2018011498A (ja) | 2018-01-18 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI587310B (zh) | 非揮發性記憶體的驅動電路 | |
TWI652675B (zh) | 非揮發性記憶體的驅動電路 | |
TWI618072B (zh) | 電源切換電路 | |
TWI538404B (zh) | 準位切換器 | |
JP2005278378A (ja) | チャージポンプ回路 | |
JP3389856B2 (ja) | 半導体装置 | |
TWI517579B (zh) | 位準移位電路以及利用位準移位電路之半導體裝置 | |
CN110703010A (zh) | 测试电路 | |
TW201318339A (zh) | 電壓開關電路 | |
JPH1196749A (ja) | 電圧レベル変換回路 | |
CN107908220B (zh) | 一种适用于宽电源电压范围的参考电压产生电路 | |
CN107086045B (zh) | 产生施加给非易失性存储单元的电压的电压供应器件 | |
JP2007235815A (ja) | レベル変換回路 | |
JP6003759B2 (ja) | スイッチ回路、及び、半導体記憶装置 | |
JP6610223B2 (ja) | 半導体集積回路 | |
TWI756084B (zh) | 針對電池電壓的分壓器電路以及具備分壓器電路的電子裝置 | |
TWI520492B (zh) | 轉壓器 | |
JP2006301840A (ja) | 信号レベル変換バススイッチ | |
KR100372684B1 (ko) | 메모리셀 값 판독용 센스앰프 | |
CN117608348A (zh) | 电压供应电路及转换多个电压电平的方法 | |
JP4552304B2 (ja) | 電圧切換回路 | |
JP5262531B2 (ja) | レベルシフト回路 | |
TW202418026A (zh) | 電壓供應電路及轉換多個電壓電平的方法 | |
TWM484864U (zh) | 位準偏移電路的輸出級電路 | |
CN105743489A (zh) | 一种无静态功耗的电平转换电路 |