TW201906140A - 具有uv透射窗的uv可抹除記憶體元件及其製作方法 - Google Patents

具有uv透射窗的uv可抹除記憶體元件及其製作方法 Download PDF

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TW201906140A
TW201906140A TW106127876A TW106127876A TW201906140A TW 201906140 A TW201906140 A TW 201906140A TW 106127876 A TW106127876 A TW 106127876A TW 106127876 A TW106127876 A TW 106127876A TW 201906140 A TW201906140 A TW 201906140A
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ultraviolet
transmission window
memory device
erasable memory
layer
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蘇婷婷
陳冠勳
羅明山
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力旺電子股份有限公司
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Abstract

一種具紫外線透射窗的紫外線可抹除記憶體裝置，包含：一基底；二個PMOS電晶體，彼此串接在一起，設於該基底上；一層間介電層，覆蓋該二個PMOS電晶體；一第一金屬間介電層，設於該層間介電層上；一中間層，設於該第一金屬間介電層上；一紫外線透射窗，設於該中間層內；以及一第二金屬間介電層，設於該第一金屬間介電層及該紫外線透射窗內。

Description

具有UV透射窗的UV可抹除記憶體元件及其製作方法
本發明係有關於一種非揮發性記憶胞(non-volatile memory)，更具體地說，本發明係有關於一種能夠提高紫外線(UV)抹除效率的單層多晶矽(single-poly)一次編程(OTP)記憶胞。
多元化市場及應用的需求驅使嵌入式邏輯非揮發性記憶體(邏輯非揮發性記憶體)朝各種不同的功能發展。周知的邏輯非揮發性記憶體之一是單層多晶矽非揮發性記憶體或單層多晶矽一次編程(OTP)記憶體技術，與CMOS製程完全相容，廣泛應用於各種晶片設計中用於資料儲存。
通常，單層多晶矽OTP記憶胞包括兩個串聯的電晶體，其中第一個電晶體係作為一選擇電晶體，第二個電晶體的閘極係作為一浮置閘極。單層多晶矽OTP記憶胞通常由對紫外線(UV)透明的介電材料覆蓋。
已知，將熱載子（電子）注入到單層多晶矽浮動閘極中的狀態被稱為“編程”狀態，並且在該狀態下資料得以被儲存，相反的，電子未被注入到單層多晶矽浮動閘極中稱為“抹除”狀態，資料在此狀態下被清除。上述單層多晶矽OTP記憶胞可以被UV抹除。
本發明的一主要目的在提供具有改善的UV抹除效率的UV可抹除記憶體元件。
本發明的另一個目的在提供一種製造具有UV透射窗的UV可抹除記憶體元件的方法。
根據本發明一實施例，披露一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，包含：提供一基底；於該基底上形成串接在一起的二個PMOS電晶體；沉積一層間介電層，覆蓋該二個PMOS電晶體；於該層間介電層上沉積一第一金屬間介電層；於該第一金屬間介電層上沉積一中間層；於該中間層內形成一紫外線透射窗；以及於該第一金屬間介電層及該紫外線透射窗內沉積一第二金屬間介電層。
根據本發明一實施例，該二個PMOS電晶體包含一選擇電晶體及一浮置閘極電晶體。該浮置閘極電晶體包含一多晶矽閘極，用以儲存電荷。該紫外線透射窗係設於該多晶矽閘極正上方。
根據本發明一實施例，披露一種具紫外線透射窗的紫外線可抹除記憶體裝置，包含：一基底；二個PMOS電晶體，彼此串接在一起，設於該基底上；一層間介電層，覆蓋該二個PMOS電晶體；一第一金屬間介電層，設於該層間介電層上；一中間層，設於該第一金屬間介電層上；一紫外線透射窗，設於該中間層內；以及一第二金屬間介電層，設於該第一金屬間介電層及該紫外線透射窗內。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉較佳實施方式，並配合所附圖式，作詳細說明如下。然而如下之較佳實施方式與圖式僅供參考與說明用，並非用來對本發明加以限制者。
在下文中，將參照附圖說明細節，該些附圖中之內容亦構成說明書細節描述的一部份，並且以可實行該實施例之特例描述方式來繪示。下文實施例已描述足夠的細節俾使該領域之一般技藝人士得以具以實施。
當然，亦可採行其他的實施例，或是在不悖離文中所述實施例的前提下作出任何結構性、邏輯性、及電性上的改變。因此，下文的細節描述不應被視為是限制，反之，其中所包含的實施例將由隨附的申請專利範圍來加以界定。
本發明涉及一種紫外線(UV)可抹除記憶體元件，例如具有改進的UV抹除性能的UV可抹除電可編程唯讀記憶體(EPROM)元件或單層多晶矽一次編程(OTP)記憶體元件。
請參閱第1圖至第3圖，其為依據本發明一實施例所繪示的一種具紫外線透射窗的紫外線(UV)可抹除記憶體元件1的製作方法的剖面示意圖。如第1圖所示，提供一基底10。基底10可以是一半導體基底，例如矽基底，但不限於此。舉例來說，基底10可以是一P型矽基底，且一N型井101可以設於基底10的一記憶陣列區內。
根據本發明一實施例，於基底10上，設有二個MOS電晶體11及12，彼此串接在一起，其中第一MOS電晶體11係作為一選擇電晶體，並且可以是一PMOS電晶體。第一MOS電晶體11的一多晶矽閘極111可以耦合至一選擇閘極電壓VSG 。在多晶矽閘極111與基底10之間，設有一選擇閘極介電層112。第一MOS電晶體11另有一第一端點，例如一摻雜區103，可以耦合至一源極線電壓VSL 。其中，摻雜區103可以是一P+ 摻雜區。
第一MOS電晶體11另有一第二端點，例如一摻雜區105，可以耦合至一第二MOS電晶體12的一第一端點。換言之，第一MOS電晶體11係透過共用的摻雜區105，串聯至該第二MOS電晶體12。其中，摻雜區105可以是一P+ 摻雜區。
在多晶矽閘極111的各個側壁上，可以設置側壁子113。輕摻雜汲極（LDD）區域103a和105a可以形成在N型井101中並且分別直接設置在側壁子113的正下方。LDD區域103a和105a可以是P型LDD區域。
第二MOS電晶體12的一第二端點，例如一摻雜區107，係耦合到一位元線電壓VBL 。摻雜區107可以是一P+ 摻雜區域。第二MOS電晶體12是浮置閘極電晶體，並且可以是PMOS電晶體。第二MOS電晶體12的多晶矽閘極121係一用於電荷存儲的浮置閘極。浮置閘極介電層122可以設置在多晶矽閘極121與基底10之間。
同樣的，在多晶矽閘極121的各個側壁上，可以設置側壁子123。輕摻雜汲極（LDD）區域105b和107a可以形成在N型井101中並且分別直接設置在側壁子123的正下方。LDD區域105b和107a可以是P型LDD區域。
可選地，可以進行一自對準矽化金屬製程，以在多晶矽閘極111上形成一矽化金屬層131，在摻雜區103上形成一矽化金屬層133，在摻雜區105上形成一矽化金屬層135，以及在摻雜區107上的矽化金屬層137。根據本發明一實施例，在多晶矽閘極121上不會形成矽化金屬層，因為在上述自對準矽化金屬過程中，多晶矽閘極121被自對準矽化金屬阻擋(SAB)層130覆蓋。
在形成矽化金屬層131、133、135及137之後，接觸蝕刻停止層(CESL)210共形沉積在基底10上以覆蓋矽化金屬層131、133、135及137，第一MOS電晶體11與第二MOS電晶體12。根據本發明一實施例，接觸蝕刻停止層210還覆蓋自對準矽化金屬阻擋層130，並且不與多晶矽閘極121直接接觸。
在接觸蝕刻停止層210沉積之後，將層間介電(ILD)層220沉積在接觸蝕刻停止層210上。例如，層間介電層220可以包括BSG、BPSG或低介電常數介電材料。儘管圖中僅示出了單一層的層間介電層220，但是應當理解，層間介電層220可以包括多層的介電材料。接觸元件(未示出)可以形成在層間介電層220中。
隨後，諸如氮化矽層的蝕刻停止層230可以沉積在層間介電層220上。接著，可以在蝕刻停止層230上沉積一第一金屬間介電（IMD）層240。第一金屬間介電層240可以包括矽氧化物或低介電常數介電材料。接著，中間層250可以沉積在第一金屬間介電層240上。根據本發明一實施例，中間層250可以是厚度範圍在1500埃至2500埃之間的氮氧化矽層，例如2000埃。
由氮氧化矽組成的相對厚的中間層250對於銅雙鑲嵌(copper dual damascene)製程是必要的，例如通孔優先(via-first)銅雙鑲嵌製程。然而，在UV抹除操作期間，這層由氮氧化矽組成的相對厚的中間層250會阻擋UV光，這降低了UV抹除的效率。
如第2圖所示，根據本發明一實施例，接著利用微影製程在中間層250上形成一光阻圖案260。光阻圖案260可以利用通常用於銅雙鑲嵌製程中的同一道光罩來定義，例如，用於在銅雙鑲嵌製程中定義通孔優先的通孔圖案的光罩。因此，不需要額外的光罩。
光阻圖案260包括與多晶矽閘極121對準並定位在其上的開口260a。接著進行一乾蝕刻製程經由開口260a蝕刻中間層250，從而形成穿過中間層250並且可以延伸到部分第一金屬間介電層240中的凹陷溝槽250a。隨後，去除光阻圖案260。
藉由去除多晶矽閘極121正上方的中間層250，形成一UV透射窗300。
如第3圖所示，在去除光阻圖案260之後，在中間層250上沉積一第二金屬間介電層270。凹陷溝槽250a被第二金屬間介電層270完全填滿。儘管未繪示於圖中，應理解的是可以在記憶體陣列外的第一金屬間介電層240、中間層250及第二金屬間介電層270中形成一銅雙鑲嵌結構。例如，銅雙鑲嵌結構可以形成在一周邊電路區域內(圖未示)。
在UV抹除操作期間，UV可抹除記憶體元件1暴露於短波長輻射400例如UV光。藉由在金屬間介電層之間設置UV透射窗300，UV抹除的效率可以顯著提高。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
1‧‧‧紫外線(UV)可抹除記憶體元件
10‧‧‧基底
11‧‧‧第一MOS電晶體
12‧‧‧第二MOS電晶體
101‧‧‧N型井
103‧‧‧摻雜區
103a‧‧‧輕摻雜汲極（LDD）區域
105‧‧‧摻雜區
105a‧‧‧輕摻雜汲極（LDD）區域
105b‧‧‧輕摻雜汲極（LDD）區域
107‧‧‧摻雜區
107a‧‧‧輕摻雜汲極（LDD）區域
111‧‧‧多晶矽閘極
112‧‧‧選擇閘極介電層
113‧‧‧側壁子
121‧‧‧多晶矽閘極
122‧‧‧浮置閘極介電層
123‧‧‧側壁子
130‧‧‧自對準矽化金屬阻擋(SAB)層
131‧‧‧矽化金屬層
133‧‧‧矽化金屬層
135‧‧‧矽化金屬層
137‧‧‧矽化金屬層
210‧‧‧接觸蝕刻停止層(CESL)
220‧‧‧層間介電(ILD)層
230‧‧‧蝕刻停止層
240‧‧‧第一金屬間介電（IMD）層
250‧‧‧中間層
250a‧‧‧凹陷溝槽
260‧‧‧光阻圖案
260a‧‧‧開口
270‧‧‧第二金屬間介電層
300‧‧‧UV透射窗
400‧‧‧短波長輻射
VSG‧‧‧選擇閘極電壓
VSL‧‧‧源極線電壓
VBL‧‧‧位元線電壓
所附圖式係提供對實施例的進一步理解，並且被併入並構成本說明書的一部分。所附圖式用以例示部分實施例，並用於解釋其原理。在所附圖式中： 第1圖至第3圖為依據本發明一實施例所繪示的一種製作UV可抹除記憶體元件的方法的剖面示意圖。 應該注意的是，所附圖式僅供例示說明。為方便說明及為求清楚，部分附圖的相對尺寸及比例係被放大或縮小。通常，相同的附圖標記在各不同實施例中表示對應或相似特徵。

Claims (20)

  1. 一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，包含： 提供一基底； 於該基底上形成串接在一起的二個MOS電晶體； 沉積一層間介電層，覆蓋該二個MOS電晶體； 於該層間介電層上沉積一第一金屬間介電層； 於該第一金屬間介電層上沉積一中間層； 於該中間層內形成一紫外線透射窗；以及 於該第一金屬間介電層及該紫外線透射窗內沉積一第二金屬間介電層。
  2. 申請專利範圍第1項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該二個MOS電晶體包含一選擇電晶體及一浮置閘極電晶體。
  3. 申請專利範圍第2項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該浮置閘極電晶體包含一多晶矽閘極，用以儲存電荷。
  4. 申請專利範圍第3項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該紫外線透射窗係形成在該多晶矽閘極正上方。
  5. 申請專利範圍第1項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該基底係為一P型矽基底，具有一N型井。
  6. 申請專利範圍第2項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中另包含： 形成一自對準矽化金屬阻擋層，覆蓋該多晶矽閘極。
  7. 申請專利範圍第6項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中另包含： 於該串接在一起的二個MOS電晶體上及該自對準矽化金屬阻擋層上沉積一接觸蝕刻停止層。
  8. 申請專利範圍第7項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該層間介電層矽沉積在該接觸蝕刻停止層上。
  9. 申請專利範圍第1項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該中間層係為一氮氧化矽層。
  10. 申請專利範圍第1項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置的製作方法，其中該中間層的厚度介於1500埃至2500埃。
  11. 一種具紫外線透射窗的紫外線可抹除記憶體裝置，包含： 一基底； 二個PMOS電晶體，彼此串接在一起，設於該基底上； 一層間介電層，覆蓋該二個PMOS電晶體； 一第一金屬間介電層，設於該層間介電層上； 一中間層，設於該第一金屬間介電層上； 一紫外線透射窗，設於該中間層內；以及 一第二金屬間介電層，設於該第一金屬間介電層及該紫外線透射窗內。
  12. 申請專利範圍第11項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該二個PMOS電晶體包含一選擇電晶體及一浮置閘極電晶體。
  13. 申請專利範圍第12項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該浮置閘極電晶體包含一多晶矽閘極，用以儲存電荷。
  14. 申請專利範圍第13項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該紫外線透射窗係設於該多晶矽閘極正上方。
  15. 申請專利範圍第11項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該基底係為一P型矽基底，具有一N型井。
  16. 申請專利範圍第12項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中另包含： 一自對準矽化金屬阻擋層，覆蓋該多晶矽閘極。
  17. 申請專利範圍第16項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中另包含： 一接觸蝕刻停止層，設於該二個PMOS電晶體上及該自對準矽化金屬阻擋層上。
  18. 申請專利範圍第17項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該層間介電層矽沉積在該接觸蝕刻停止層上。
  19. 申請專利範圍第11項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該中間層係為一氮氧化矽層。
  20. 申請專利範圍第11項所述的一種具紫外線透射窗的紫外線可抹除記憶體裝置，其中該中間層的厚度介於1500埃至2500埃。
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