TW201112421A - A fin field effect transistor - Google Patents

A fin field effect transistor Download PDF

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Publication number
TW201112421A
TW201112421A TW099130987A TW99130987A TW201112421A TW 201112421 A TW201112421 A TW 201112421A TW 099130987 A TW099130987 A TW 099130987A TW 99130987 A TW99130987 A TW 99130987A TW 201112421 A TW201112421 A TW 201112421A
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Taiwan
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substrate
width
upper portion
fin
field effect
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TW099130987A
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TWI517384B (zh
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Feng Yuan
Hung-Ming Chen
Tsung-Lin Lee
Chang-Yun Chang
Clement Hsingjen Wann
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Taiwan Semiconductor Mfg
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Description

201112421 六、發明說明： 【發明所屬之技術領域】 本發明係有關於電晶體，且特別是有關於一種具有 隔離結構之鰭式場效電晶體。 【先前技術】
半導體裝置廣泛使用於例如電腦、手機等等電子裝 置中。半導體裝置包含積體電路，藉由沉積多種型熊^ 材料薄膜於半導體晶圓上，並將這些材料薄獏圖案化而 形成積體電路。這些積體電路包含場效電晶體， 例如金氧半場效電晶體（MOSFET)。 半導體產業之目標為持續縮減各個金氧半場效電晶 體的尺寸及增進其處理速度。為了達成此目標，目前曰已曰 三維（3D)或非平面電晶體結構，例如.鰭式場效 電s曰體，（麵FET)、:多間極電晶體或環繞式間極電晶 體（gate-all_aroundtransist〇r)，以應用於次 卉 電:曰體節點（t_istornodes)。這些電晶體不僅；進 位密度，亦增進了通道之閘極控制。 θ 難顆然式場電晶體的製造極為複雜且需克服許多 -構項挑料形成無⑽（⑽“如）的隔離 -冓在形成隔離結構之早期階段時 於介電材料中。第以至圔辟 陷Ρ 了月b形成 至1C圖顯示用於鰭式場 100之傳統隔離結構於各種製诰p比讲+ Μ 效電日日體 出現在隔離結構12。中=二之:面圖’凹陷126b 成分離多個縛式結構u。之溝二基材102以形 /再馉122，接著，再以例如高 0503-A34456TWF/jeff 3 201112421 进電聚（HDP)氧化物、四乙氧基⑪烧（teqs)氧化物 電材料一124填充這些溝槽122而形成隔離結構（如 第1B圖所示）。由於溝槽122的高深寬比，介電材料 124可能會含有多個深細縫/凹陷（slims/reeesses) 126a。 第ic圖顯示在移除介電材料124之上部期間或之後，可 月b會化著&些深細縫/凹陷126&形成凹陷a讣於隔離結 構120中。；^些凹陷126b將會於各種情況下造成問題。 例如，廷些隔離結構120中的凹陷216b可在隨後製程中 成為多晶梦或金屬的儲存空間，因而降低裝置的穩定性 及/或使裝置失效。 【發明内容】 本發明係提供一種半導體裝置，包括：一基材，包 含一主要表面，·複數個鰭式結構，突出此基材之此主要 表面’其中每個鰭式結構皆包含—藉由—過渡位置所分 離之-上部及-下部，此過渡位置位於⑽式結構之側 壁與此基材之此主要表面夾角85度之處，其中此上部具 有與此基材之此主要表面實質上垂直之側壁及一具有第 -寬度之頂面’其中此下部在此上部之兩側具有漸窄側 壁，且此下部具有一底部’其中此底部具有一第二寬度 大於此第-寬度；以及複數個隔離結構，位於此些續^ 結構之間，其中每個隔離結構皆自此基材之此主要= 延伸至此過渡位置上方之一點。 本發明亦提供一種場效電晶體，包括·· 一基材，包 含一主要表面；一鰭式結構，突出此基材之此主要表= 0503_A34456TWF/jeff 4 201112421
並化縱向延伸’其中此鰭式結構包含—與此縱向垂直 之剖面’其中此剖面包含—藉由—過渡位置所分離之一 上部及-下部’此過渡位置位於此鰭式結構之侧壁盥此 基材之此主要表面夹角85度之處，其^此上部具有與此 基材之此主要表面實質上垂直之側壁及一具有第一寬度 之頂面’其中此下部在此上部之兩側具有漸窄側壁，^ :下部具有-底部，此底部具有一第二寬度大於此第一 見度’、中此上邛包含一第一縱向部分、一第二縱向部 分及位於此第一縱向部分及此第二縱向部分之間的一第 t縱向部分；一通道區域’位於此上部之此第三縱向部 /刀中.-閘極結構，位於此通道區域上；—珍化物層， 位於此第-及此第二縱向部分中，形成源極，沒極區；以 :二隔離結構’圍繞此鰭式結構，其中此隔離結構自此 土之此主要表面延伸至此過渡位置上方之一點。 為讓本發明之上述和其他目的、特徵、和優點能更 勿 卜文特舉出較佳貫施例，並配合所附圖式， 作詳細說明如下： 【實施方式】 蘇明t發月接下來將會提供許多不同的實施例以實施本 ^$同的特徵。各特定實施射的組成及配置將會 定本：Π以簡化本發明。這些為實施例並非用於限 “ ” “。此=，—第一元件形成於一第二元件‘‘上方”、 一之上之下，或“上，，可包含實施例中的該第一元件與第 --件直接接觸’或也可包含該第一元件與第二元件之 〇503-A34456TWF/jeff 201112421 =更有其他額外元件使該第—元件與第二元件無直接接 觸。此外’在本發明之各鮮狀圖城實施例中，參 考標號可能會有所重複以使表達能清晰簡潔，但表 各實施例及/或圖示間有所關連。各種元件可能以任音不 同比例顯示以使圖示清晰簡潔。 〜 第2A至2H圖顯示依照本發明實施例在一基 造鰭式場效電晶體，於各種製造階段之剖面圖，及第^ 圖顯示使用第2A至2H圖所示步驟所製造之韓式場效 晶體之立體圖。可知較’鰭式場效電晶體2GG的部分 ^牛可由-般的互補式金氧半導體（CM〇s)技術製程製 以，及因此某些製程在此僅簡略描述。此外，第2入 2H圖已作簡化以使本發明之概念易於明瞭。例如，雖然 圖不中僅顯示鰭式場效電晶體·，積體電路中亦可: 其他裝置，例如電阻、電容、電感、炼絲等。 參見第2A目’籍式場效電晶體2〇〇可包含 材202，例如石夕美好 十土 土 j如夕基材。或者，基材202可包含錯化矽 匕鎵或其他合適半導體材料。基材搬可更包含其他元 牛’例如各種摻雜區域、深埋層及/或蟲晶層。再者，基 f ςητ、彳為絕緣層上覆半導體’例如絕緣層上覆矽 Μ曰μ在其他實施例中，半導體基材2〇2可包含摻雜 一日日α、梯度半導體層及/或更包含一半導體層覆於另 不同之半導體層上’例如石夕層覆於鍺化石夕層上。 :美：實Γ中，化合物半導體基材202可包含多層的 矽基材可包含多層的化合物半導體基材。 參見第2A ® ’塾氧化層204形成於基材202之頂面 〇503-A34456TWF/jeff 201112421 上。墊氧化層204較佳為由熱氧化製程所生長形成之氧 化矽，厚度為約80至150A。例如，墊氧化層可由快速 熱氧化（RTO)製程或含氧之傳統退火製程生長形成。 硬罩幕層206，例如氮化矽或氮氧化矽層，形成於墊氧化 層204上。硬罩幕層206可由例如化學氣相沉積（CVD) 製程或低壓化學氣相沉積製程（LPCVD)形成。所形成 之硬罩幕層206厚度較佳為約600至1500 A。 參見第2B圖，形成硬罩幕層206之後，形成圖案化 鲁 光敏層（未顯示）於硬罩幕層206上。可使用例如反應 性離子蝕刻（RIE)或高密度電漿（HDP)製程以非等向 性蝕刻對硬幕層206及墊氧化層204蝕刻，以形成開口 208於硬罩幕層206及墊氧化層204中，暴露部分的基材 202 ° 參見第2C圖，可使用第一蝕刻製程蝕刻基材202， 以形成突出基材202之主要表面202a之鰭·式結構210的 上部210a。第一蝕刻製程可在例如電源功率約550至650 籲 瓦、偏壓功率約55至65瓦、壓力約2至10 mTorr的條 件下，使用二氟曱烷、六氟化硫、氮氣及氦氣作為蝕刻 氣體進行。基材202包含一平行於基材表面202b之主要 表面202a。每個鰭式結構210之上部210a皆具有側壁， 且此側壁實質上垂直於基材202之主要表面202a及頂面 210c。 參見第2D圖，可使用第二蝕刻製程進一步蝕刻基材 202，以形成突出基材202之主要表面202a之鰭式結構 210之下部210b。第二蝕刻製程可例如在電源功率約1100 0503-A34456TWF/jeff 7 201112421 至1250瓦、偏壓功率約200至220瓦、壓力約1〇至2〇 心1"的條件下’使用漠化氫、六氟化硫及氦氣作為餘刻 氣體進行。每個鰭式結構之上部21〇a及下部21〇b皆係 由一過渡位置（transition l〇cation) 210d所分離，該過渡 位置210d位於鰭式結構之側壁與基材2〇2之主要表面 202a之夾角212為85度之處。每個鰭式結構21〇之下部 21〇b ’於上部21〇a及底部21〇e之兩側，具有漸窄的 (tapered)側壁。每個鰭式結構21〇之下部21卯之漸窄 區域較佳與基材202之主要表面2〇2a有約6〇至Μ度之 夾角214。在一實施例中’複數個低深寬比的溝槽222形 成於漸窄的鰭式結構210中，其深寬比較形成於垂直鰭 ^結構110中的溝槽122低。低深寬比的溝槽222可較 高深寬比的溝槽122有較佳的填充效果。 繼續參見第2D圖，每個鰭式結構21〇之上部21〇a 之頂面210c具有第一寬度216a，此第一寬度⑽為約$ 至40 nm。在一實施例中，每個鰭式結構21〇之下部21〇b 之底部2H)e具有第二寬度2他，此第二寬度皿為約 10至60 nm。第一寬度21仏與第二寬度21心之比例較 佳為約0.3至0.5。 繼續參見第2D圖，介於過渡位置2]〇d與頂面21〇c 之間的第一偏移距離（offset distance) 216b為約4〇至 100 nm。在一實施例中，介於底部21〇e與頂面2i〇c之 間的第二偏移距離216b為約1〇〇至3〇〇11111。介於過渡位 置210d及頂面210c之閭的第一偏移距離21补與介於底 邛210e及頂面210c之間的第二偏移距離21讣之間的比 0503-A34456TWF/jeff 201112421 例較佳為約0.15至〇·3。 參見第2E圖’在形成多個鰭式結構21〇之後，在多 個.鰭式結構21〇間的多個溝槽222中形成多個隔離結構 22=概層（未顯示）可實質上順應地形成於基材202上， 包含沿著溝槽222之側壁。襯層為由熱氧化或化學氣相 ’儿積製程形成之介電層（例如氧化物層、氮化物層、氮
氧化物層或前述之組合）。較佳地，襯層之厚度為約30 牵 200 A A。在某些實施例中，襯層可具有減少鰭式結構 210表面因如上所述之溝槽蝕刻製程所造成的損傷。在某 些實施例中，可不使用襯層。 繼續參見第2E圖，在形成襯層之後，形成具有足夠 厚度之介電材料224於溝槽222中及其上。例如，介電 材料224較佳沉積至一厚度，例如自底部210e起算4000 至8000Λ。在—實施例中，可使用化學氣相沉積製程， 例如局密度電漿化學氣相沉積製程（HDP CVD process ) 或-人大氣壓化學氣相沉積（sub-atmospheric CVD， SACVD)製程’來形成介電材料224。介電材料224可 在低於5000 w的低頻功率、低於3500W的高頻功率、 壓力小於lOmTorr及溫度介於500至lOOOt：之間的條件 下’使用矽烷及氧氣作為反應前驅物形成。在另—實施 例中，介電材料224包含次大氣壓無摻雜矽玻璃 (sub-atmospheric undoped-silicon glass，SAUSG)層。 介電材料在壓力為約500至700 torr及溫度為約500至 600°C之間的條件下，使用四乙氧基矽烷（TEOS)及臭 氧（〇3)作為反應前驅物形成。由於溝槽222較低的深 0503-A34456TWF/jeff 9 201112421 寬比，介電材料224可包含多個淺縫隙/凹陷226a。 如^續參見第2E圖，在形成介電材料以於多個溝槽 及其上之後，進行退火製程以增加介電材料的密 ς。因此’ _與介電材料224之_界面在退火製程 後將會 >肖失。退火製程例如可在加熱爐（〖we)、快 速熱製程系統或其他熱系統中進行’上述系統可提供對 ”電材料的熱處理’以提供所欲的薄膜品質。在某些實 施，中’退火製程可在快速熱退火系統中之含氮氣、惰 性亂體或其他實質上不會與介電材料224進行反應之氣 體的環境下於l〇〇(TC下進行約2〇秒。 〜、 第邛圖顯示第2E圖之基材2〇2進行平坦化製程（例 如化學機械研磨製程）以移除介電材料224超過硬罩幕 層206之。卩分，以暴露硬罩幕層，因而剩下填充於溝 槽222的介電材料224。硬罩幕層2〇6亦可作為停止層， 使平坦化製程停止在硬罩幕層2〇6上。在某些實施;， 介電材料224之頂面實質上與硬罩幕層共平面。在平坦 化製程之後，介電材料224之多個淺縫隙226b將會變得 較平坦化製程之前的介電材料之淺縫隙226a更淺及更 寬。 參見第2G圖，在平坦化製程之後，以濕式化學蝕刻 製程移除硬罩幕層206 (例如以將基材202浸至熱磷酸 中），以暴露墊氧化層204之頂面。由於濕式化學蝕刻 製知對於氮相較於氧具有高餘刻選擇性，此姓刻製程移 除硬罩幕層206之速率較介電材料224快。因此，剩餘 的介電材料224延伸超過墊氧化層2〇4之頂面。在硬罩
0503-A34456TWF/jefF 201112421 幕層6之移除製程後，以濕式_製程移除塾氧❹ 頂面 基材搬浸至氫氟酸中）以暴露基材202之 2°既_式化學㈣製程對於塾氧化層綱及介電 材料224幾乎沒有選擇性，介 άΓΑ a 1 u "冤材枓224所損失的厚度 ::歲乎與墊氧化層204所損失的厚度相同。因此，介 枓224仍會突出超過每個鰭式結構2iQ的表面，且 ，，電材料224中的每個淺縫隙22&皆幾近消失。
第=圖顯示在第扣圖之基材2〇2在進行乾钱刻製 ^ (例如將基材置於含四氟甲燒及三氟甲烧之電聚中作 姓刻）以移除介電材料224之上部以暴露每個鰭式結構 之上部210a之後。鰭式結構亦可為例如電阻、電容、 電感、溶絲等其他裝置之—部份。因此，在㈣製程之 尾端，介電材料224幾乎無凹陷且作為各個半導體裝置 之間的隔離結構220。每個隔離結構22〇伸 至過渡位置则上方之_點2243。應健= 介於隔離結構220之點224a及頂面21〇c之間的第三偏 移距離216c。如隔離結構220之點22乜及頂面21(^之 間的第三偏移距離216c太小，淺縫隙/凹陷可能仍會存在 於隔離結構220之點224a上。如隔離結構22〇之點胃22乜 及頂面2l〇c之間的第三偏移距離216c太大，短通道效 應Ί此會降低裝置效能。因此，介於隔離結構22〇之點 224a及頂面21〇c之間的第三偏移距離216c較佳為約15 至45nm。介於隔離結構22〇之點22乜及頂面2i〇c之間 的第二偏移距離216c與介於過渡位置21 〇d及頂面21〇ς 之間的第一偏移距離216b之間的比例較佳為0.3至〇 6。 〇503-A34456TWF/jeff 201112421 第21圖顯示使用如第2 A至2H所製造之鰭式場效電晶體 之立體圖。每個鰭式結構21 〇沿著一縱向21 〇g延伸。如 前所述’第21圖中之隔離結構220無凹陷存在。 第3A至3D圖顯示使用如第2A至2H圖之步驟製造 之具有多個隔離結構220之完整鰭式場效電晶體裝置 300，其中第3A圖顯示一立體圖，且其中第3B至31)圖 各自顯示沿著第3A圖之對應線段的剖面圖。在第2及3 圖中’相似元件以相同標號表示，以使圖示清晰簡潔。 參見第3 A圖’鰭式場效電晶體3〇〇包含多個由隔離 結構220分隔之鰭式結構21〇。每個鰭式結構21〇沿著一 縱向21〇g延伸。含閘極電極32〇a及閘極絕緣層31肋之 閘極結構320置於鰭式結構210上。第3A圖亦顯示鰭式 場效電晶體300之源極/汲極區330a、330b。 .第3B圖顯示鰭式場效電晶體3〇〇沿著第3a圖之線 段.b-b之剖面圖。每個沿著縱向21〇g延伸之鰭式結構 210，包含由過渡位置210d所分離的上部210a及下部 210b，此過渡位置21〇d位在鰭式結構21〇之側壁與基材 202之主要表面202a夾角85度處，上部21〇a具有與頂 面210c及基材202之主要表面202a實質上垂直的侧壁， 此上部21〇a包含一第一縱向部分21〇ga、一第二縱向部 分210gb、.及位於第一縱向部分21〇ga與一第二縱向部分 210gb之間的第三縱向部分2i〇gC。通道區33〇可位於上 部210a之第三縱向部分2i〇gc中。含閘極電極32〇a及閘 極絕緣層31〇b之閘極結構320可置於通道區33〇上方。 矽化物層（未顯示）可置於第一縱向部分21〇ga與一第 0503-A34456TWF/jeflF 12 201112421 二縱向部分210gb中，以形成鰭式場效電晶體300中的 源極/汲極區。上部21〇a下方的下部210b具有自下而上 的漸窄侧壁，位於上部210及底部210e之兩側。 參見第3C圖，其為沿著第3A圖之線段c-c之剖面 圖，閘極結構320包含閘極電極320a及閘極絕緣層 320b。閘極電極320置於閘極絕緣層320b上。當閘極絕 緣層320b在鰭式結構320之整個表面上均具有均勻厚度 時’可形成三閘極電晶體。三閘極電晶體之通道33〇位 於閘極結構320下方及鰭式結構210之上部210b之第三 縱向部分210gc之頂面210c及側壁中。然而，在某些實 施例中，在閘極絕緣層310形成之前或之後，可形成額 外的介電層（未顯示）於上部210a之第三縱向部分21〇gc 之頂面210c上，鰭式場效電晶體3〇〇之通道33〇僅沿著 第二縱向部分21〇gc之側壁形成，形成雙閘極電晶體。 第3D圖為沿著第3A圖之線段c_c之剖面圖。位於 隔離結構220之間的鰭式結構21〇以縱向21〇g在下方某 材202之連續部件（continuous pieces )中延伸。在某些 實施例中，‘ϋ式結構2H)可由絕緣層（未顯示）來分離二。 鐘式結構210之上部210a之第一及第二縱向部分 2H)ga、2H)gb包含重摻雜區（未顯示），切化物声口 顯示）可位於第一及第二縱向部分2、、2曰以市 成鰭式場效電晶體·之源極/没極區。在各種實施例 中’重摻雜區（dopant-dch regi〇n)之厚度為約〇5⑽ 至Μ.接著，在隨後製程中，包含内連線製程，·需於 形成鰭式場效電晶體300之後進杆，^ 而万' 丁以元成積體電路的 13 0503-A34456TWF/jeff r* 201112421 製造。 雖然本發明已以數個較佳實施例揭露如上，然其並 非用以限定本發明，任何所屬技術領域中具有通常知識 者，在不脫離本發明之精神和範圍内，當可作任意之更 動與潤飾，因此本發明之保護範圍當視後附之申請專利 範圍所界定者為準。本發明可用以形成或製造用於無隔 離凹陷之縛式場效電晶體之縛式結構。
0503-A34456TWF/jeff 14 201112421 【圖式簡單說明】 第1A-1C圖顯不用於續式場效電晶體之傳統隔離雄 構之各種製造階段，具有凹陷存在於隔離結構中； 第2A至2H圖顯示依照本發明實施例在基材上製造 鰭式場效電晶體，於各種製造階段之剖面圖； 第21圖顯示使用第2A至2H圖所示步驟所製造之鰭 式場效電晶體之立體圖；以及 第3A至3D圖顯示使用如第2A至2H圖之步驟製造 鲁之具有多個隔離結構之完整鰭式場效電晶體裝置，其中 第3 A圖顯示一立體圖，且第3B至3D圖各自顯示沿著 第3A圖之對應線段的剖面圖。
【主要元件符號說明】 100〜鰭式場效電晶體； 110〜鰭式結構； 122〜溝槽； 126a〜凹陷； 200〜縛式場效電晶體， 202a〜主要表面； 204〜墊氧化層； 208〜開口； 210a〜上部； 210c〜頂面； 210e〜底部； 210ga〜第一縱向部分； 102〜基材； 120〜隔離結構； 124〜介電材料； 126b〜凹陷； 202〜基材； 202b〜基材表面； 206〜硬罩幕層； 210〜鰭式結構； 210b〜下部； 210d〜過渡位置； 210g〜縱向； 210gb〜第二縱向部分； 0503-A34456TWF/jefF 15 201112421 210gc〜第三縱向部分； 214~炎角； 216b〜第一偏移距離； 218a〜第二寬度； 220〜隔離結構； 224〜介電材料； 226a〜淺縫隙； 212〜夾角； 216a〜第一寬度； 216c〜第三偏移距離； 218b〜第二偏移距離； 222〜溝槽； 224a〜點； 226b〜淺縫隙； 226c〜淺縫隙； 300〜鰭式場效電晶體； 320〜閘極結構； 320a〜閘極電極； 泰 320b〜閘極絕緣層； 330〜通道區。
0503-A34456TWF/jeff 16

Claims (1)

  1. 201112421 七、申請專利範圍·· I.一種半導體裝置，包括： 面 一基材，包含一主要表 —複數個鰭式結構，突出該基材之該主要表面，i 每：鰭；結構皆包含一藉由一過渡位置所分離之」上部 及一下部，該過渡位置位於該鰭式結構之側壁 主要表面央角85度之處，其中該上部具有與：： 之該主要表面實質上垂直之側壁及一具有第一寬度之頂 立八令該下。P在s亥上部之兩側具有漸窄側壁，且該下 =有7底部’其中該底部具有一第二寬度大於該第二 見度，以及 複數個隔離結構’位於該些,鰭式結構之間，並 =離結構皆自該基材之該主要表面延伸至該過渡 上方之一點。 第-2宽利範圍第1項所述之半導體裝置，其中該 U! nm，該第二寬度為約至6〇咖。 第* 月專利乾圍帛1項所述之半導體裝置，其中該 第一見度與該第二寬度之比例為約0.3至0.5。 於兮利Γ圍第1項所述之半導體裝置，其中介 部及該頂面之間的第二第—偏移距離與介於該底 5如申-主直·^ 移距離之比例為約0.15至0.3。 5. 如申请專利範圍第1 於該點及該頂面之間的第：偏’…導體裝置’其中介 —偏移距離與介於該過渡位置 偏移距離之比例為約。·3至。.6。 6. 一種場效電晶體，包括： 0503-A34456TWF/jeff 201112421 一基材，包含一主要表面； 一鰭式結構，突出該基材之該主要表面並沿一縱向 延伸，其中該鰭式結構包含—與該縱向垂直之剖面，苴 中該剖面包含-藉由—過渡位置所分離之—上部及一 ^該過渡位置位於該鰭式結構之側壁與該基材之該主 要表面夾角85度之處，其中該上部具有與該基材之該主 要表面實質上垂直之側壁及一具有第一寬度之頂面，其 中該下部在該上部之兩側具有漸窄側壁 一底部，該底部具有-第二寬度大於該第—寬^其^ :上部包含-第一縱向部分、一第二縱向部分及位於該 第-縱向部分及該第二縱向部分之間的一第 分； 一通道區域，位於該上部之該第三縱向部分中： 一閘極結構，位於該通道區域上； 、-矽化物層，位於該第一及該第二縱向部分中，形 成源極/沒極區；以及 一隔離結構，圍繞賴式結構，其中該_結構自 該基材之該主要表面延伸至該過渡位置上方之一點。 =如申請專利範圍第6項所述之場效電晶體，其中該 第一寬度為約5至40nm’該第二寬度為約1〇至6〇nm。 8. 如申請專利範圍第6項所述之場效電晶體，其中該 第-寬度與該第二寬度之比例為約〇·3至〇 5。 9. 如申明專利範圍第6項所述之場效電晶體，其中介 於該過渡位置及該頂面之間的第—偏移距離與介於該底 部及該頂面之間的第二偏移距離之比例為約〇.15至0.3。 0503-A34456TWF/jeff 201112421 10.如申請專利範圍第6項所述之場效電晶體，其中 介於該點及該頂面之間的第三偏移距離與介於該過渡位 置及該頂面之間的第一偏移距離之比例為約0.3至0.6。
    0503-A34456TWF/jeff 19
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TWI517384B (zh) 2016-01-11
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US11158725B2 (en) 2021-10-26

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