CN102034868B - 半导体装置及场效应晶体管 - Google Patents

半导体装置及场效应晶体管 Download PDF

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CN102034868B
CN102034868B CN2010102881000A CN201010288100A CN102034868B CN 102034868 B CN102034868 B CN 102034868B CN 2010102881000 A CN2010102881000 A CN 2010102881000A CN 201010288100 A CN201010288100 A CN 201010288100A CN 102034868 B CN102034868 B CN 102034868B
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CN102034868A (zh
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袁锋
陈宏铭
李宗霖
张长昀
万幸仁
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明关于鳍式场效应晶体管的隔离结构。本发明公开了一种半导体装置及场效应晶体管，该鳍式场效应晶体管包括含一主要表面的基材；多个鳍式结构，突出此基材的主要表面，其中每个鳍式结构均包含由一过渡位置所分离的上部及下部，此过渡位置位于鳍式结构的侧壁与基材主要表面夹角85度处，其中此上部具有与此基材主要表面实质上垂直的侧壁及具有第一宽度的顶面，此下部具有位于此上部的两侧锥形侧壁及具有第二宽度的底部，此第二宽度大于此第一宽度；及多个隔离结构位于此些鳍式结构之间，其中每个隔离结构均自此基材的此主要表面延伸至过渡位置上方的一点。本发明可用以形成或制造用于无隔离凹陷的鳍式场效应晶体管的鳍式结构。

Description

半导体装置及场效应晶体管
技术领域
本发明涉及晶体管，尤其涉及一种具有隔离结构的鳍式场效应晶体管。
背景技术
半导体装置广泛使用于例如电脑、手机等等电子装置中。半导体装置包含集成电路，借由沉积多种形态的材料薄膜于半导体晶片上，并将这些材料薄膜图案化而形成集成电路。这些集成电路包含场效应晶体管(FET)，例如金属氧化物半导体场效应晶体管(MOSFET)。
半导体产业的目标为持续缩减各个金属氧化物半导体场效应晶体管的尺寸及增进其处理速度。为了达成此目标，目前已发展出三维(3D)或非平面晶体管结构，例如鳍式场效应晶体管，(FINFET)、多栅极晶体管或环绕式栅极晶体管(gate-all-around transistor)，以应用于次22纳米的晶体管节点(transistor nodes)。这些晶体管不仅增进单位密度，也增进了沟道的栅极控制。
然而，鳍式场晶体管的制造极为复杂且需克服许多难题，其中一项挑战为形成无凹陷(recess-free)的隔离结构。在形成隔离结构的早期阶段时，凹陷即可能形成于介电材料中。图1A至图1C显示用于鳍式场效应晶体管100的传统隔离结构于各种制造阶段的剖面图，凹陷126b出现在隔离结构120中。图1A显示蚀刻基材102以形成分离多个鳍式结构110的沟槽122，接着，再以例如高密度等离子体(HDP)氧化物、四乙氧基硅烷(TEOS)氧化物等介电材料124填充这些沟槽122而形成隔离结构(如图1B所示)。由于沟槽122的高深宽比，介电材料124可能会含有多个深细缝/凹陷(slims/recesses)126a。图1C显示在移除介电材料124的上部期间或之后，可能会沿着这些深细缝/凹陷126a形成凹陷126b于隔离结构120中。这些凹陷126b将会于各种情况下造成问题。例如，这些隔离结构120中的凹陷216b可在随后工艺中成为多晶硅或金属的储存空间，因而降低装置的稳定性及/或使装置失效。
发明内容
为了解决现有技术的问题，本发明提供一种半导体装置，包括：一基材，包含一主要表面；多个鳍式结构，突出此基材的此主要表面，其中每个鳍式结构均包含一借由一过渡位置所分离的一上部及一下部，此过渡位置位于此鳍式结构的侧壁与此基材的此主要表面夹角85度之处，其中此上部具有与此基材的此主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中此下部在此上部的两侧具有渐窄侧壁，且此下部具有一底部，其中此底部具有一第二宽度大于此第一宽度；以及多个隔离结构，位于此些鳍式结构之间，其中每个隔离结构均自此基材的此主要表面延伸至此过渡位置上方的一点。
本发明也提供一种场效应晶体管，包括：一基材，包含一主要表面；一鳍式结构，突出此基材的此主要表面并沿一纵向延伸，其中此鳍式结构包含一与此纵向垂直的剖面，其中此剖面包含一借由一过渡位置所分离的一上部及一下部，此过渡位置位于此鳍式结构的侧壁与此基材的此主要表面夹角85度之处，其中此上部具有与此基材的此主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中此下部在此上部的两侧具有渐窄侧壁，且此下部具有一底部，此底部具有一第二宽度大于此第一宽度，其中此上部包含一第一纵向部分、一第二纵向部分及位于此第一纵向部分及此第二纵向部分之间的一第三纵向部分；一沟道区域，位于此上部的此第三纵向部分中：一栅极结构，位于此沟道区域上；一硅化物层，位于此第一及此第二纵向部分中，形成源极/漏极区；以及一隔离结构，围绕此鳍式结构，其中此隔离结构自此基材的此主要表面延伸至此过渡位置上方的一点。
本发明可用以形成或制造用于无隔离凹陷的鳍式场效应晶体管的鳍式结构。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1A～图1C显示用于鳍式场效应晶体管的传统隔离结构的各种制造阶段，具有凹陷存在于隔离结构中；
图2A至图2H显示依照本发明实施例在基材上制造鳍式场效应晶体管，于各种制造阶段的剖面图；
图2I显示使用图2A至图2H所示步骤所制造的鳍式场效应晶体管的立体图；以及
图3A至图3D显示使用如图2A至图2H的步骤制造的具有多个隔离结构的完整鳍式场效应晶体管装置，其中图3A显示一立体图，且图3B至图3D各自显示沿着图3A的对应线段的剖面图。
其中，附图标记说明如下：
100～鳍式场效应晶体管102～基材
110～鳍式结构120～隔离结构
122～沟槽124～介电材料
126a～凹陷126b～凹陷
200～鳍式场效应晶体管202～基材
202a～主要表面202b～基材表面
204～垫氧化层206～硬掩模层
208～开口210～鳍式结构
210a～上部210b～下部
210c～顶面210d～过渡位置
210e～底部210g～纵向
210ga～第一纵向部分210gb～第二纵向部分
210gc～第三纵向部分212～夹角
214～夹角216a～第一宽度
216b～第一偏移距离216c～第三偏移距离
218a～第二宽度218b～第二偏移距离
220～隔离结构222～沟槽
224～介电材料224a～点
226a～浅缝隙226b～浅缝隙
226c～浅缝隙300～鳍式场效应晶体管
320～栅极结构320a～栅极电极
320b～栅极绝缘层330～沟道区
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。各特定实施例中的组成及配置将会在以下作描述以简化本发明。这些为实施例并非用于限定本发明。此外，一第一元件形成于一第二元件“上方”、“之上”、“之下”或“上”可包含实施例中的该第一元件与第二元件直接接触，或也可包含该第一元件与第二元件之间还有其他额外元件使该第一元件与第二元件无直接接触。此外，在本发明的各种举例的图示及实施例中，参考标记可能会有所重复以使表达能清晰简洁，但不代表各实施例及/或图示间有所关联。各种元件可能以任意不同比例显示以使图示清晰简洁。
图2A至图2H显示依照本发明实施例在一基材上制造鳍式场效应晶体管，于各种制造阶段的剖面图，及图2I显示使用图2A至图2H所示步骤所制造的鳍式场效应晶体管的立体图。可知的是，鳍式场效应晶体管200的部分元件可由一般的互补式金属氧化物半导体(CMOS)技术工艺制造，及因此某些工艺在此仅简略描述。此外，图2A至图2H已作简化以使本发明的概念易于明了。例如，虽然图示中仅显示鳍式场效应晶体管200，集成电路中也可包含其他装置，例如电阻、电容、电感、熔丝等。
参见图2A，鳍式场效应晶体管200可包含半导体基材202，例如硅基材。或者，基材202可包含锗化硅、砷化镓或其他合适半导体材料。基材202可还包含其他元件，例如各种掺杂区域、深埋层及/或外延层。此外，基材202可为绝缘层上覆半导体，例如绝缘层上覆硅(SOI)。在其他实施例中，半导体基材202可包含掺杂的外延层、梯度半导体层及/或还包含一半导体层覆于另一不同形态的半导体层上，例如硅层覆于锗化硅层上。在其他实施例中，化合物半导体基材202可包含多层的硅基材，或硅基材可包含多层的化合物半导体基材。
参见图2A，垫氧化层204形成于基材202的顶面上。垫氧化层204较佳为由热氧化工艺所生长形成的氧化硅，厚度为约80至例如，垫氧化层可由快速热氧化(RTO)工艺或含氧的传统退火工艺生长形成。硬掩模层206，例如氮化硅或氮氧化硅层，形成于垫氧化层204上。硬掩模层206可由例如化学气相沉积(CVD)工艺或低压化学气相沉积工艺(LPCVD)形成。所形成的硬掩模层206厚度较佳为约600至
Figure GSB00000375940600051
参见图2B，形成硬掩模层206之后，形成图案化光敏层(未显示)于硬掩模层206上。可使用例如反应性离子蚀刻(RIE)或高密度等离子体(HDP)工艺以各向异性蚀刻对硬掩模层206及垫氧化层204蚀刻，以形成开口208于硬掩模层206及垫氧化层204中，暴露部分的基材202。
参见图2C，可使用第一蚀刻工艺蚀刻基材202，以形成突出基材202的主要表面202a的鳍式结构210的上部210a。第一蚀刻工艺可在例如电源功率约550至650瓦、偏压功率约55至65瓦、压力约2至10mTorr的条件下，使用二氟甲烷、六氟化硫、氮气及氦气作为蚀刻气体进行。基材202包含一平行于基材表面202b的主要表面202a。每个鳍式结构210的上部210a均具有侧壁，且此侧壁实质上垂直于基材202的主要表面202a及顶面210c。
参见图2D，可使用第二蚀刻工艺进一步蚀刻基材202，以形成突出基材202的主要表面202a的鳍式结构210的下部210b。第二蚀刻工艺可例如在电源功率约1100至1250瓦、偏压功率约200至220瓦、压力约10至20mTorr的条件下，使用溴化氢、六氟化硫及氦气作为蚀刻气体进行。每个鳍式结构的上部210a及下部210b均由一过渡位置(transition location)210d所分离，该过渡位置210d位于鳍式结构的侧壁与基材202的主要表面202a的夹角212为85度之处。每个鳍式结构210的下部210b，于上部210a及底部210e的两侧，具有渐窄的(tapered)侧壁。每个鳍式结构210的下部210b的渐窄区域较佳与基材202的主要表面202a有约60至85度的夹角214。在一实施例中，多个低深宽比的沟槽222形成于渐窄的鳍式结构210中，其深宽比较形成于垂直鳍式结构110中的沟槽122低。低深宽比的沟槽222可较高深宽比的沟槽122有较佳的填充效果。
继续参见图2D，每个鳍式结构210的上部210a的顶面210c具有第一宽度216a，此第一宽度216a为约5至40nm。在一实施例中，每个鳍式结构210的下部210b的底部210e具有第二宽度218a，此第二宽度218a为约10至60nm。第一宽度216a与第二宽度218a的比例较佳为约0.3至0.5。
继续参见图2D，介于过渡位置210d与顶面210c之间的第一偏移距离(offset distance)216b为约40至100nm。在一实施例中，介于底部210e与顶面210c之间的第二偏移距离216b为约100至300nm。介于过渡位置210d及顶面210c之间的第一偏移距离216b与介于底部210e及顶面210c之间的第二偏移距离216b之间的比例较佳为约0.15至0.3。
参见图2E，在形成多个鳍式结构210之后，在多个鳍式结构210间的多个沟槽222中形成多个隔离结构220。衬层(未显示)可实质上顺应地形成于基材202上，包含沿着沟槽222的侧壁。衬层为由热氧化或化学气相沉积工艺形成的介电层(例如氧化物层、氮化物层、氮氧化物层或前述的组合)。较佳地，衬层的厚度为约30至
Figure GSB00000375940600061
在某些实施例中，衬层可具有减少鳍式结构210表面因如上所述的沟槽蚀刻工艺所造成的损伤。在某些实施例中，可不使用衬层。
继续参见图2E，在形成衬层之后，形成具有足够厚度的介电材料224于沟槽222中及其上。例如，介电材料224较佳沉积至一厚度，例如自底部210e起算4000至
Figure GSB00000375940600062
在一实施例中，可使用化学气相沉积工艺，例如高密度等离子体化学气相沉积工艺(HDP CVD process)或次大气压化学气相沉积(sub-atmospheric CVD，SACVD)工艺，来形成介电材料224。介电材料224可在低于5000W的低频功率、低于3500W的高频功率、压力小于10mTorr及温度介于500至1000℃之间的条件下，使用硅烷及氧气作为反应前驱物形成。在另一实施例中，介电材料224包含次大气压无掺杂硅玻璃(sub-atmospheric undoped-silicon glass，SAUSG)层。介电材料在压力为约500至700torr及温度为约500至600℃之间的条件下，使用四乙氧基硅烷(TEOS)及臭氧(O3)作为反应前驱物形成。由于沟槽222较低的深宽比，介电材料224可包含多个浅缝隙/凹陷226a。
继续参见图2E，在形成介电材料224于多个沟槽222中及其上之后，进行退火工艺以增加介电材料的密度。因此，衬层与介电材料224之间的界面在退火工艺后将会消失。退火工艺例如可在加热炉(furnace)、快速热工艺系统或其他热系统中进行，上述系统可提供对介电材料的热处理，以提供所欲的薄膜品质。在某些实施例中，退火工艺可在快速热退火系统中的含氮气、惰性气体或其他实质上不会与介电材料224进行反应的气体的环境下于1000℃下进行约20秒。
图2F显示图2E的基材202进行平坦化工艺(例如化学机械研磨工艺)以移除介电材料224超过硬掩模层206的部分，以暴露硬掩模层206，因而剩下填充于沟槽222的介电材料224。硬掩模层206也可作为停止层，使平坦化工艺停止在硬掩模层206上。在某些实施例中，介电材料224的顶面实质上与硬掩模层共平面。在平坦化工艺之后，介电材料224的多个浅缝隙226b将会变得较平坦化工艺之前的介电材料的浅缝隙226a更浅及更宽。
参见图2G，在平坦化工艺之后，以湿式化学蚀刻工艺移除硬掩模层206(例如以将基材202浸至热磷酸中)，以暴露垫氧化层204的顶面。由于湿式化学蚀刻工艺对于氮相较于氧具有高蚀刻选择性，此蚀刻工艺移除硬掩模层206的速率较介电材料224快。因此，剩余的介电材料224延伸超过垫氧化层204的顶面。在硬掩模层206的移除工艺后，以湿式蚀刻工艺移除垫氧化层204(例如将基材202浸至氢氟酸中)以暴露基材202的顶面。既然湿式化学蚀刻工艺对于垫氧化层204及介电材料224几乎没有选择性，介电材料224所损失的厚度可能几乎与垫氧化层204所损失的厚度相同。因此，介电材料224仍会突出超过每个鳍式结构210的表面，且介电材料224中的每个浅缝隙226c均几近消失。
图2H显示在图2G的基材202在进行干蚀刻工艺(例如将基材置于含四氟甲烷及三氟甲烷的等离子体中作蚀刻)以移除介电材料224的上部以暴露每个鳍式结构210的上部210a之后。鳍式结构也可为例如电阻、电容、电感、熔丝等其他装置的一部分。因此，在蚀刻工艺的尾端，介电材料224几乎无凹陷且作为各个半导体装置之间的隔离结构220。每个隔离结构220延伸超过基材表面202a至过渡位置210d上方的一点224a。应谨慎控制介于隔离结构220的点224a及顶面210c之间的第三偏移距离216c。如隔离结构220的点224a及顶面210c之间的第三偏移距离216c太小，浅缝隙/凹陷可能仍会存在于隔离结构220的点224a上。如隔离结构220的点224a及顶面210c之间的第三偏移距离216c太大，短沟道效应可能会降低装置效能。因此，介于隔离结构220的点224a及顶面210c之间的第三偏移距离216c较佳为约15至45nm。介于隔离结构220的点224a及顶面210c之间的第三偏移距离216c与介于过渡位置210d及顶面210c之间的第一偏移距离216b之间的比例较佳为0.3至0.6。图2I显示使用如图2A至图2H所制造的鳍式场效应晶体管的立体图。每个鳍式结构210沿着一纵向210g延伸。如前所述，图2I中的隔离结构220无凹陷存在。
图3A至图3D显示使用如图2A至图2H的步骤制造的具有多个隔离结构220的完整鳍式场效应晶体管装置300，其中图3A显示一立体图，且其中图3B至图3D各自显示沿着图3A的对应线段的剖面图。在图2及图3中，相似元件以相同标记表示，以使图示清晰简洁。
参见图3A，鳍式场效应晶体管300包含多个由隔离结构220分隔的鳍式结构210。每个鳍式结构210沿着一纵向210g延伸。含栅极电极320a及栅极绝缘层310b的栅极结构320置于鳍式结构210上。图3A也显示鳍式场效应晶体管300的源极/漏极区330a、330b。
图3B显示鳍式场效应晶体管300沿着图3A的线段b-b的剖面图。每个沿着纵向210g延伸的鳍式结构210，包含由过渡位置210d所分离的上部210a及下部210b，此过渡位置210d位在鳍式结构210的侧壁与基材202的主要表面202a夹角85度处，上部210a具有与顶面210c及基材202的主要表面202a实质上垂直的侧壁，此上部210a包含一第一纵向部分210ga、一第二纵向部分210gb、及位于第一纵向部分210ga与一第二纵向部分210gb之间的第三纵向部分210gc。沟道区330可位于上部210a的第三纵向部分210gc中。含栅极电极320a及栅极绝缘层310b的栅极结构320可置于沟道区330上方。硅化物层(未显示)可置于第一纵向部分210ga与一第二纵向部分210gb中，以形成鳍式场效应晶体管300中的源极/漏极区。上部210a下方的下部210b具有自下而上的渐窄侧壁，位于上部210及底部210e的两侧。
参见图3C，其为沿着图3A的线段c-c的剖面图，栅极结构320包含栅极电极320a及栅极绝缘层320b。栅极电极320置于栅极绝缘层320b上。当栅极绝缘层320b在鳍式结构320的整个表面上均具有均匀厚度时，可形成三栅极晶体管。三栅极晶体管的沟道330位于栅极结构320下方及鳍式结构210的上部210b的第三纵向部分210gc的顶面210c及侧壁中。然而，在某些实施例中，在栅极绝缘层310形成之前或之后，可形成额外的介电层(未显示)于上部210a的第三纵向部分210gc的顶面210c上，鳍式场效应晶体管300的沟道330仅沿着第三纵向部分210gc的侧壁形成，形成双栅极晶体管。
图3D为沿着图3A的线段c-c的剖面图。位于隔离结构220之间的鳍式结构210以纵向210g在下方基材202的连续部件(continuous pieces)中延伸。在某些实施例中，鳍式结构210可由绝缘层(未显示)来分离。鳍式结构210的上部210a的第一及第二纵向部分210ga、210gb包含重掺杂区(未显示)，且硅化物层(未显示)可位于第一及第二纵向部分210ga、210gb中以形成鳍式场效应晶体管300的源极/漏极区。在各种实施例中，重掺杂区(dopant-rich region)的厚度为约0.5nm至10nm。接着，在随后工艺中，包含内连线工艺，需于形成鳍式场效应晶体管300之后进行，以完成集成电路的制造。
虽然本发明已以数个优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。本发明可用以形成或制造用于无隔离凹陷的鳍式场效应晶体管的鳍式结构。

Claims (10)

1.一种半导体装置，包括：
一基材，包含一主要表面；
多个鳍式结构，突出该基材的该主要表面，其中每个鳍式结构均包含一借由一过渡位置所分离的一上部及一下部，该过渡位置位于该鳍式结构的侧壁与该基材的该主要表面夹角85度之处，其中该上部具有与该基材的该主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中该下部在该上部的两侧具有渐窄侧壁，且该下部具有一底部，其中该底部具有一第二宽度大于该第一宽度；以及
多个隔离结构，位于所述多个鳍式结构之间，其中每个隔离结构均自该基材的该主要表面延伸至该过渡位置上方的一点。
2.如权利要求1所述的半导体装置，其中该第一宽度为约5至40nm，该第二宽度为约10至60nm。
3.如权利要求1所述的半导体装置，其中该第一宽度与该第二宽度的比例为约0.3至0.5。
4.如权利要求1所述的半导体装置，其中介于该过渡位置及该顶面之间的第一偏移距离与介于该底部及该顶面之间的第二偏移距离的比例为约0.15至0.3。
5.如权利要求1所述的半导体装置，其中介于该点及该顶面之间的第三偏移距离与介于该过渡位置及该顶面之间的第一偏移距离的比例为约0.3至0.6。
6.一种场效应晶体管，包括：
一基材，包含一主要表面；
一鳍式结构，突出该基材的该主要表面并沿一纵向延伸，其中该鳍式结构包含一与该纵向垂直的剖面，其中该剖面包含一借由一过渡位置所分离的一上部及一下部，该过渡位置位于该鳍式结构的侧壁与该基材的该主要表面夹角85度之处，其中该上部具有与该基材的该主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中该下部在该上部的两侧具有渐窄侧壁，且该下部具有一底部，该底部具有一第二宽度大于该第一宽度，其中该上部包含一第一纵向部分、一第二纵向部分及位于该第一纵向部分及该第二纵向部分之间的一第三纵向部分；
一沟道区域，位于该上部的该第三纵向部分中：
一栅极结构，位于该沟道区域上；
一硅化物层，位于该第一及该第二纵向部分中，形成源极/漏极区；以及
一隔离结构，围绕该鳍式结构，其中该隔离结构自该基材的该主要表面延伸至该过渡位置上方的一点。
7.如权利要求6所述的场效应晶体管，其中该第一宽度为约5至40nm，该第二宽度为约10至60nm。
8.如权利要求6所述的场效应晶体管，其中该第一宽度与该第二宽度的比例为约0.3至0.5。
9.如权利要求6所述的场效应晶体管，其中介于该过渡位置及该顶面之间的第一偏移距离与介于该底部及该顶面之间的第二偏移距离的比例为约0.15至0.3。
10.如权利要求6所述的场效应晶体管，其中介于该点及该顶面之间的第三偏移距离与介于该过渡位置及该顶面之间的第一偏移距离的比例为约0.3至0.6。
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US11158725B2 (en) 2021-10-26
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