CN102034868B - 半导体装置及场效应晶体管 - Google Patents

半导体装置及场效应晶体管 Download PDF

Info

Publication number
CN102034868B
CN102034868B CN2010102881000A CN201010288100A CN102034868B CN 102034868 B CN102034868 B CN 102034868B CN 2010102881000 A CN2010102881000 A CN 2010102881000A CN 201010288100 A CN201010288100 A CN 201010288100A CN 102034868 B CN102034868 B CN 102034868B
Authority
CN
China
Prior art keywords
width
fin formula
base material
effect transistor
face
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN2010102881000A
Other languages
English (en)
Other versions
CN102034868A (zh
Inventor
袁锋
陈宏铭
李宗霖
张长昀
万幸仁
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN102034868A publication Critical patent/CN102034868A/zh
Application granted granted Critical
Publication of CN102034868B publication Critical patent/CN102034868B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7851—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET with the body tied to the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)

Abstract

本发明关于鳍式场效应晶体管的隔离结构。本发明公开了一种半导体装置及场效应晶体管，该鳍式场效应晶体管包括含一主要表面的基材；多个鳍式结构，突出此基材的主要表面，其中每个鳍式结构均包含由一过渡位置所分离的上部及下部，此过渡位置位于鳍式结构的侧壁与基材主要表面夹角85度处，其中此上部具有与此基材主要表面实质上垂直的侧壁及具有第一宽度的顶面，此下部具有位于此上部的两侧锥形侧壁及具有第二宽度的底部，此第二宽度大于此第一宽度；及多个隔离结构位于此些鳍式结构之间，其中每个隔离结构均自此基材的此主要表面延伸至过渡位置上方的一点。本发明可用以形成或制造用于无隔离凹陷的鳍式场效应晶体管的鳍式结构。

Description

半导体装置及场效应晶体管
技术领域
本发明涉及晶体管，尤其涉及一种具有隔离结构的鳍式场效应晶体管。
背景技术
半导体装置广泛使用于例如电脑、手机等等电子装置中。半导体装置包含集成电路，借由沉积多种形态的材料薄膜于半导体晶片上，并将这些材料薄膜图案化而形成集成电路。这些集成电路包含场效应晶体管(FET)，例如金属氧化物半导体场效应晶体管(MOSFET)。
半导体产业的目标为持续缩减各个金属氧化物半导体场效应晶体管的尺寸及增进其处理速度。为了达成此目标，目前已发展出三维(3D)或非平面晶体管结构，例如鳍式场效应晶体管，(FINFET)、多栅极晶体管或环绕式栅极晶体管(gate-all-around transistor)，以应用于次22纳米的晶体管节点(transistor nodes)。这些晶体管不仅增进单位密度，也增进了沟道的栅极控制。
然而，鳍式场晶体管的制造极为复杂且需克服许多难题，其中一项挑战为形成无凹陷(recess-free)的隔离结构。在形成隔离结构的早期阶段时，凹陷即可能形成于介电材料中。图1A至图1C显示用于鳍式场效应晶体管100的传统隔离结构于各种制造阶段的剖面图，凹陷126b出现在隔离结构120中。图1A显示蚀刻基材102以形成分离多个鳍式结构110的沟槽122，接着，再以例如高密度等离子体(HDP)氧化物、四乙氧基硅烷(TEOS)氧化物等介电材料124填充这些沟槽122而形成隔离结构(如图1B所示)。由于沟槽122的高深宽比，介电材料124可能会含有多个深细缝/凹陷(slims/recesses)126a。图1C显示在移除介电材料124的上部期间或之后，可能会沿着这些深细缝/凹陷126a形成凹陷126b于隔离结构120中。这些凹陷126b将会于各种情况下造成问题。例如，这些隔离结构120中的凹陷216b可在随后工艺中成为多晶硅或金属的储存空间，因而降低装置的稳定性及/或使装置失效。
发明内容
为了解决现有技术的问题，本发明提供一种半导体装置，包括：一基材，包含一主要表面；多个鳍式结构，突出此基材的此主要表面，其中每个鳍式结构均包含一借由一过渡位置所分离的一上部及一下部，此过渡位置位于此鳍式结构的侧壁与此基材的此主要表面夹角85度之处，其中此上部具有与此基材的此主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中此下部在此上部的两侧具有渐窄侧壁，且此下部具有一底部，其中此底部具有一第二宽度大于此第一宽度；以及多个隔离结构，位于此些鳍式结构之间，其中每个隔离结构均自此基材的此主要表面延伸至此过渡位置上方的一点。
本发明也提供一种场效应晶体管，包括：一基材，包含一主要表面；一鳍式结构，突出此基材的此主要表面并沿一纵向延伸，其中此鳍式结构包含一与此纵向垂直的剖面，其中此剖面包含一借由一过渡位置所分离的一上部及一下部，此过渡位置位于此鳍式结构的侧壁与此基材的此主要表面夹角85度之处，其中此上部具有与此基材的此主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中此下部在此上部的两侧具有渐窄侧壁，且此下部具有一底部，此底部具有一第二宽度大于此第一宽度，其中此上部包含一第一纵向部分、一第二纵向部分及位于此第一纵向部分及此第二纵向部分之间的一第三纵向部分；一沟道区域，位于此上部的此第三纵向部分中：一栅极结构，位于此沟道区域上；一硅化物层，位于此第一及此第二纵向部分中，形成源极/漏极区；以及一隔离结构，围绕此鳍式结构，其中此隔离结构自此基材的此主要表面延伸至此过渡位置上方的一点。
本发明可用以形成或制造用于无隔离凹陷的鳍式场效应晶体管的鳍式结构。
为让本发明的上述和其他目的、特征、和优点能更明显易懂，下文特举出优选实施例，并配合所附附图，作详细说明如下：
附图说明
图1A～图1C显示用于鳍式场效应晶体管的传统隔离结构的各种制造阶段，具有凹陷存在于隔离结构中；
图2A至图2H显示依照本发明实施例在基材上制造鳍式场效应晶体管，于各种制造阶段的剖面图；
图2I显示使用图2A至图2H所示步骤所制造的鳍式场效应晶体管的立体图；以及
图3A至图3D显示使用如图2A至图2H的步骤制造的具有多个隔离结构的完整鳍式场效应晶体管装置，其中图3A显示一立体图，且图3B至图3D各自显示沿着图3A的对应线段的剖面图。
其中，附图标记说明如下：
100～鳍式场效应晶体管102～基材
110～鳍式结构120～隔离结构
122～沟槽124～介电材料
126a～凹陷126b～凹陷
200～鳍式场效应晶体管202～基材
202a～主要表面202b～基材表面
204～垫氧化层206～硬掩模层
208～开口210～鳍式结构
210a～上部210b～下部
210c～顶面210d～过渡位置
210e～底部210g～纵向
210ga～第一纵向部分210gb～第二纵向部分
210gc～第三纵向部分212～夹角
214～夹角216a～第一宽度
216b～第一偏移距离216c～第三偏移距离
218a～第二宽度218b～第二偏移距离
220～隔离结构222～沟槽
224～介电材料224a～点
226a～浅缝隙226b～浅缝隙
226c～浅缝隙300～鳍式场效应晶体管
320～栅极结构320a～栅极电极
320b～栅极绝缘层330～沟道区
具体实施方式
本发明接下来将会提供许多不同的实施例以实施本发明中不同的特征。各特定实施例中的组成及配置将会在以下作描述以简化本发明。这些为实施例并非用于限定本发明。此外，一第一元件形成于一第二元件“上方”、“之上”、“之下”或“上”可包含实施例中的该第一元件与第二元件直接接触，或也可包含该第一元件与第二元件之间还有其他额外元件使该第一元件与第二元件无直接接触。此外，在本发明的各种举例的图示及实施例中，参考标记可能会有所重复以使表达能清晰简洁，但不代表各实施例及/或图示间有所关联。各种元件可能以任意不同比例显示以使图示清晰简洁。
图2A至图2H显示依照本发明实施例在一基材上制造鳍式场效应晶体管，于各种制造阶段的剖面图，及图2I显示使用图2A至图2H所示步骤所制造的鳍式场效应晶体管的立体图。可知的是，鳍式场效应晶体管200的部分元件可由一般的互补式金属氧化物半导体(CMOS)技术工艺制造，及因此某些工艺在此仅简略描述。此外，图2A至图2H已作简化以使本发明的概念易于明了。例如，虽然图示中仅显示鳍式场效应晶体管200，集成电路中也可包含其他装置，例如电阻、电容、电感、熔丝等。
参见图2A，鳍式场效应晶体管200可包含半导体基材202，例如硅基材。或者，基材202可包含锗化硅、砷化镓或其他合适半导体材料。基材202可还包含其他元件，例如各种掺杂区域、深埋层及/或外延层。此外，基材202可为绝缘层上覆半导体，例如绝缘层上覆硅(SOI)。在其他实施例中，半导体基材202可包含掺杂的外延层、梯度半导体层及/或还包含一半导体层覆于另一不同形态的半导体层上，例如硅层覆于锗化硅层上。在其他实施例中，化合物半导体基材202可包含多层的硅基材，或硅基材可包含多层的化合物半导体基材。
参见图2A，垫氧化层204形成于基材202的顶面上。垫氧化层204较佳为由热氧化工艺所生长形成的氧化硅，厚度为约80至例如，垫氧化层可由快速热氧化(RTO)工艺或含氧的传统退火工艺生长形成。硬掩模层206，例如氮化硅或氮氧化硅层，形成于垫氧化层204上。硬掩模层206可由例如化学气相沉积(CVD)工艺或低压化学气相沉积工艺(LPCVD)形成。所形成的硬掩模层206厚度较佳为约600至
Figure GSB00000375940600051
参见图2B，形成硬掩模层206之后，形成图案化光敏层(未显示)于硬掩模层206上。可使用例如反应性离子蚀刻(RIE)或高密度等离子体(HDP)工艺以各向异性蚀刻对硬掩模层206及垫氧化层204蚀刻，以形成开口208于硬掩模层206及垫氧化层204中，暴露部分的基材202。
参见图2C，可使用第一蚀刻工艺蚀刻基材202，以形成突出基材202的主要表面202a的鳍式结构210的上部210a。第一蚀刻工艺可在例如电源功率约550至650瓦、偏压功率约55至65瓦、压力约2至10mTorr的条件下，使用二氟甲烷、六氟化硫、氮气及氦气作为蚀刻气体进行。基材202包含一平行于基材表面202b的主要表面202a。每个鳍式结构210的上部210a均具有侧壁，且此侧壁实质上垂直于基材202的主要表面202a及顶面210c。
参见图2D，可使用第二蚀刻工艺进一步蚀刻基材202，以形成突出基材202的主要表面202a的鳍式结构210的下部210b。第二蚀刻工艺可例如在电源功率约1100至1250瓦、偏压功率约200至220瓦、压力约10至20mTorr的条件下，使用溴化氢、六氟化硫及氦气作为蚀刻气体进行。每个鳍式结构的上部210a及下部210b均由一过渡位置(transition location)210d所分离，该过渡位置210d位于鳍式结构的侧壁与基材202的主要表面202a的夹角212为85度之处。每个鳍式结构210的下部210b，于上部210a及底部210e的两侧，具有渐窄的(tapered)侧壁。每个鳍式结构210的下部210b的渐窄区域较佳与基材202的主要表面202a有约60至85度的夹角214。在一实施例中，多个低深宽比的沟槽222形成于渐窄的鳍式结构210中，其深宽比较形成于垂直鳍式结构110中的沟槽122低。低深宽比的沟槽222可较高深宽比的沟槽122有较佳的填充效果。
继续参见图2D，每个鳍式结构210的上部210a的顶面210c具有第一宽度216a，此第一宽度216a为约5至40nm。在一实施例中，每个鳍式结构210的下部210b的底部210e具有第二宽度218a，此第二宽度218a为约10至60nm。第一宽度216a与第二宽度218a的比例较佳为约0.3至0.5。
继续参见图2D，介于过渡位置210d与顶面210c之间的第一偏移距离(offset distance)216b为约40至100nm。在一实施例中，介于底部210e与顶面210c之间的第二偏移距离216b为约100至300nm。介于过渡位置210d及顶面210c之间的第一偏移距离216b与介于底部210e及顶面210c之间的第二偏移距离216b之间的比例较佳为约0.15至0.3。
参见图2E，在形成多个鳍式结构210之后，在多个鳍式结构210间的多个沟槽222中形成多个隔离结构220。衬层(未显示)可实质上顺应地形成于基材202上，包含沿着沟槽222的侧壁。衬层为由热氧化或化学气相沉积工艺形成的介电层(例如氧化物层、氮化物层、氮氧化物层或前述的组合)。较佳地，衬层的厚度为约30至
Figure GSB00000375940600061
在某些实施例中，衬层可具有减少鳍式结构210表面因如上所述的沟槽蚀刻工艺所造成的损伤。在某些实施例中，可不使用衬层。
继续参见图2E，在形成衬层之后，形成具有足够厚度的介电材料224于沟槽222中及其上。例如，介电材料224较佳沉积至一厚度，例如自底部210e起算4000至
Figure GSB00000375940600062
在一实施例中，可使用化学气相沉积工艺，例如高密度等离子体化学气相沉积工艺(HDP CVD process)或次大气压化学气相沉积(sub-atmospheric CVD，SACVD)工艺，来形成介电材料224。介电材料224可在低于5000W的低频功率、低于3500W的高频功率、压力小于10mTorr及温度介于500至1000℃之间的条件下，使用硅烷及氧气作为反应前驱物形成。在另一实施例中，介电材料224包含次大气压无掺杂硅玻璃(sub-atmospheric undoped-silicon glass，SAUSG)层。介电材料在压力为约500至700torr及温度为约500至600℃之间的条件下，使用四乙氧基硅烷(TEOS)及臭氧(O3)作为反应前驱物形成。由于沟槽222较低的深宽比，介电材料224可包含多个浅缝隙/凹陷226a。
继续参见图2E，在形成介电材料224于多个沟槽222中及其上之后，进行退火工艺以增加介电材料的密度。因此，衬层与介电材料224之间的界面在退火工艺后将会消失。退火工艺例如可在加热炉(furnace)、快速热工艺系统或其他热系统中进行，上述系统可提供对介电材料的热处理，以提供所欲的薄膜品质。在某些实施例中，退火工艺可在快速热退火系统中的含氮气、惰性气体或其他实质上不会与介电材料224进行反应的气体的环境下于1000℃下进行约20秒。
图2F显示图2E的基材202进行平坦化工艺(例如化学机械研磨工艺)以移除介电材料224超过硬掩模层206的部分，以暴露硬掩模层206，因而剩下填充于沟槽222的介电材料224。硬掩模层206也可作为停止层，使平坦化工艺停止在硬掩模层206上。在某些实施例中，介电材料224的顶面实质上与硬掩模层共平面。在平坦化工艺之后，介电材料224的多个浅缝隙226b将会变得较平坦化工艺之前的介电材料的浅缝隙226a更浅及更宽。
参见图2G，在平坦化工艺之后，以湿式化学蚀刻工艺移除硬掩模层206(例如以将基材202浸至热磷酸中)，以暴露垫氧化层204的顶面。由于湿式化学蚀刻工艺对于氮相较于氧具有高蚀刻选择性，此蚀刻工艺移除硬掩模层206的速率较介电材料224快。因此，剩余的介电材料224延伸超过垫氧化层204的顶面。在硬掩模层206的移除工艺后，以湿式蚀刻工艺移除垫氧化层204(例如将基材202浸至氢氟酸中)以暴露基材202的顶面。既然湿式化学蚀刻工艺对于垫氧化层204及介电材料224几乎没有选择性，介电材料224所损失的厚度可能几乎与垫氧化层204所损失的厚度相同。因此，介电材料224仍会突出超过每个鳍式结构210的表面，且介电材料224中的每个浅缝隙226c均几近消失。
图2H显示在图2G的基材202在进行干蚀刻工艺(例如将基材置于含四氟甲烷及三氟甲烷的等离子体中作蚀刻)以移除介电材料224的上部以暴露每个鳍式结构210的上部210a之后。鳍式结构也可为例如电阻、电容、电感、熔丝等其他装置的一部分。因此，在蚀刻工艺的尾端，介电材料224几乎无凹陷且作为各个半导体装置之间的隔离结构220。每个隔离结构220延伸超过基材表面202a至过渡位置210d上方的一点224a。应谨慎控制介于隔离结构220的点224a及顶面210c之间的第三偏移距离216c。如隔离结构220的点224a及顶面210c之间的第三偏移距离216c太小，浅缝隙/凹陷可能仍会存在于隔离结构220的点224a上。如隔离结构220的点224a及顶面210c之间的第三偏移距离216c太大，短沟道效应可能会降低装置效能。因此，介于隔离结构220的点224a及顶面210c之间的第三偏移距离216c较佳为约15至45nm。介于隔离结构220的点224a及顶面210c之间的第三偏移距离216c与介于过渡位置210d及顶面210c之间的第一偏移距离216b之间的比例较佳为0.3至0.6。图2I显示使用如图2A至图2H所制造的鳍式场效应晶体管的立体图。每个鳍式结构210沿着一纵向210g延伸。如前所述，图2I中的隔离结构220无凹陷存在。
图3A至图3D显示使用如图2A至图2H的步骤制造的具有多个隔离结构220的完整鳍式场效应晶体管装置300，其中图3A显示一立体图，且其中图3B至图3D各自显示沿着图3A的对应线段的剖面图。在图2及图3中，相似元件以相同标记表示，以使图示清晰简洁。
参见图3A，鳍式场效应晶体管300包含多个由隔离结构220分隔的鳍式结构210。每个鳍式结构210沿着一纵向210g延伸。含栅极电极320a及栅极绝缘层310b的栅极结构320置于鳍式结构210上。图3A也显示鳍式场效应晶体管300的源极/漏极区330a、330b。
图3B显示鳍式场效应晶体管300沿着图3A的线段b-b的剖面图。每个沿着纵向210g延伸的鳍式结构210，包含由过渡位置210d所分离的上部210a及下部210b，此过渡位置210d位在鳍式结构210的侧壁与基材202的主要表面202a夹角85度处，上部210a具有与顶面210c及基材202的主要表面202a实质上垂直的侧壁，此上部210a包含一第一纵向部分210ga、一第二纵向部分210gb、及位于第一纵向部分210ga与一第二纵向部分210gb之间的第三纵向部分210gc。沟道区330可位于上部210a的第三纵向部分210gc中。含栅极电极320a及栅极绝缘层310b的栅极结构320可置于沟道区330上方。硅化物层(未显示)可置于第一纵向部分210ga与一第二纵向部分210gb中，以形成鳍式场效应晶体管300中的源极/漏极区。上部210a下方的下部210b具有自下而上的渐窄侧壁，位于上部210及底部210e的两侧。
参见图3C，其为沿着图3A的线段c-c的剖面图，栅极结构320包含栅极电极320a及栅极绝缘层320b。栅极电极320置于栅极绝缘层320b上。当栅极绝缘层320b在鳍式结构320的整个表面上均具有均匀厚度时，可形成三栅极晶体管。三栅极晶体管的沟道330位于栅极结构320下方及鳍式结构210的上部210b的第三纵向部分210gc的顶面210c及侧壁中。然而，在某些实施例中，在栅极绝缘层310形成之前或之后，可形成额外的介电层(未显示)于上部210a的第三纵向部分210gc的顶面210c上，鳍式场效应晶体管300的沟道330仅沿着第三纵向部分210gc的侧壁形成，形成双栅极晶体管。
图3D为沿着图3A的线段c-c的剖面图。位于隔离结构220之间的鳍式结构210以纵向210g在下方基材202的连续部件(continuous pieces)中延伸。在某些实施例中，鳍式结构210可由绝缘层(未显示)来分离。鳍式结构210的上部210a的第一及第二纵向部分210ga、210gb包含重掺杂区(未显示)，且硅化物层(未显示)可位于第一及第二纵向部分210ga、210gb中以形成鳍式场效应晶体管300的源极/漏极区。在各种实施例中，重掺杂区(dopant-rich region)的厚度为约0.5nm至10nm。接着，在随后工艺中，包含内连线工艺，需于形成鳍式场效应晶体管300之后进行，以完成集成电路的制造。
虽然本发明已以数个优选实施例揭示如上，然其并非用以限定本发明，任何本领域普通技术人员，在不脱离本发明的精神和范围内，当可作任意的更动与润饰，因此本发明的保护范围当视所附的权利要求所界定的范围为准。本发明可用以形成或制造用于无隔离凹陷的鳍式场效应晶体管的鳍式结构。

Claims (10)

1.一种半导体装置，包括：
一基材，包含一主要表面；
多个鳍式结构，突出该基材的该主要表面，其中每个鳍式结构均包含一借由一过渡位置所分离的一上部及一下部，该过渡位置位于该鳍式结构的侧壁与该基材的该主要表面夹角85度之处，其中该上部具有与该基材的该主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中该下部在该上部的两侧具有渐窄侧壁，且该下部具有一底部，其中该底部具有一第二宽度大于该第一宽度；以及
多个隔离结构，位于所述多个鳍式结构之间，其中每个隔离结构均自该基材的该主要表面延伸至该过渡位置上方的一点。
2.如权利要求1所述的半导体装置，其中该第一宽度为约5至40nm，该第二宽度为约10至60nm。
3.如权利要求1所述的半导体装置，其中该第一宽度与该第二宽度的比例为约0.3至0.5。
4.如权利要求1所述的半导体装置，其中介于该过渡位置及该顶面之间的第一偏移距离与介于该底部及该顶面之间的第二偏移距离的比例为约0.15至0.3。
5.如权利要求1所述的半导体装置，其中介于该点及该顶面之间的第三偏移距离与介于该过渡位置及该顶面之间的第一偏移距离的比例为约0.3至0.6。
6.一种场效应晶体管，包括：
一基材，包含一主要表面；
一鳍式结构，突出该基材的该主要表面并沿一纵向延伸，其中该鳍式结构包含一与该纵向垂直的剖面，其中该剖面包含一借由一过渡位置所分离的一上部及一下部，该过渡位置位于该鳍式结构的侧壁与该基材的该主要表面夹角85度之处，其中该上部具有与该基材的该主要表面实质上垂直的侧壁及一具有第一宽度的顶面，其中该下部在该上部的两侧具有渐窄侧壁，且该下部具有一底部，该底部具有一第二宽度大于该第一宽度，其中该上部包含一第一纵向部分、一第二纵向部分及位于该第一纵向部分及该第二纵向部分之间的一第三纵向部分；
一沟道区域，位于该上部的该第三纵向部分中：
一栅极结构，位于该沟道区域上；
一硅化物层，位于该第一及该第二纵向部分中，形成源极/漏极区；以及
一隔离结构，围绕该鳍式结构，其中该隔离结构自该基材的该主要表面延伸至该过渡位置上方的一点。
7.如权利要求6所述的场效应晶体管，其中该第一宽度为约5至40nm，该第二宽度为约10至60nm。
8.如权利要求6所述的场效应晶体管，其中该第一宽度与该第二宽度的比例为约0.3至0.5。
9.如权利要求6所述的场效应晶体管，其中介于该过渡位置及该顶面之间的第一偏移距离与介于该底部及该顶面之间的第二偏移距离的比例为约0.15至0.3。
10.如权利要求6所述的场效应晶体管，其中介于该点及该顶面之间的第三偏移距离与介于该过渡位置及该顶面之间的第一偏移距离的比例为约0.3至0.6。
CN2010102881000A 2009-09-24 2010-09-19 半导体装置及场效应晶体管 Active CN102034868B (zh)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US24548509P 2009-09-24 2009-09-24
US61/245,485 2009-09-24
US12/766,233 US9484462B2 (en) 2009-09-24 2010-04-23 Fin structure of fin field effect transistor
US12/766,233 2010-04-23

Publications (2)

Publication Number Publication Date
CN102034868A CN102034868A (zh) 2011-04-27
CN102034868B true CN102034868B (zh) 2013-11-06

Family

ID=43755880

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2010102881000A Active CN102034868B (zh) 2009-09-24 2010-09-19 半导体装置及场效应晶体管

Country Status (5)

Country Link
US (3) US9484462B2 (zh)
JP (1) JP5356344B2 (zh)
KR (1) KR101295425B1 (zh)
CN (1) CN102034868B (zh)
TW (1) TWI517384B (zh)

Families Citing this family (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI587382B (zh) * 2011-10-19 2017-06-11 聯華電子股份有限公司 半導體結構及其製程
US9318431B2 (en) 2011-11-04 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated circuit having a MOM capacitor and method of making same
US8748989B2 (en) * 2012-02-28 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Fin field effect transistors
US8546891B2 (en) 2012-02-29 2013-10-01 Taiwan Semiconductor Manufacturing Company, Ltd. Fin profile structure and method of making same
US8742509B2 (en) 2012-03-01 2014-06-03 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
US9559099B2 (en) * 2012-03-01 2017-01-31 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for FinFETs
CN103377922B (zh) * 2012-04-23 2015-12-16 中芯国际集成电路制造(上海)有限公司 一种鳍式场效应晶体管及其形成方法
US8586455B1 (en) * 2012-05-15 2013-11-19 International Business Machines Corporation Preventing shorting of adjacent devices
US8735252B2 (en) 2012-06-07 2014-05-27 Taiwan Semiconductor Manufacturing Company, Ltd. Method of semiconductor integrated circuit fabrication
US9425212B2 (en) * 2012-06-29 2016-08-23 Intel Corporation Isolated and bulk semiconductor devices formed on a same bulk substrate
JP5856545B2 (ja) * 2012-07-06 2016-02-09 株式会社東芝 半導体装置及びその製造方法
TWI553858B (zh) * 2012-07-11 2016-10-11 聯華電子股份有限公司 多閘極場效電晶體及其製程
US8716803B2 (en) * 2012-10-04 2014-05-06 Flashsilicon Incorporation 3-D single floating gate non-volatile memory device
EP2717316B1 (en) * 2012-10-05 2019-08-14 IMEC vzw Method for producing strained germanium fin structures
KR101994079B1 (ko) * 2012-10-10 2019-09-30 삼성전자 주식회사 반도체 장치 및 그 제조 방법
CN103811323B (zh) * 2012-11-13 2016-05-25 中芯国际集成电路制造(上海)有限公司 鳍部的制作方法、鳍式场效应晶体管及其制作方法
KR102003023B1 (ko) * 2012-12-24 2019-07-24 에스케이하이닉스 주식회사 반도체 소자 및 그 제조 방법
KR102013842B1 (ko) 2013-02-08 2019-08-26 삼성전자주식회사 반도체 소자의 제조 방법
US9076870B2 (en) * 2013-02-21 2015-07-07 United Microelectronics Corp. Method for forming fin-shaped structure
US9159832B2 (en) 2013-03-08 2015-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor fin structures and methods for forming the same
KR102073967B1 (ko) * 2013-07-30 2020-03-02 삼성전자주식회사 전계 효과 트랜지스터를 포함하는 반도체 소자
JP2015037091A (ja) * 2013-08-12 2015-02-23 東京エレクトロン株式会社 エッチング方法
KR102130056B1 (ko) * 2013-11-15 2020-07-03 삼성전자주식회사 핀 전계 효과 트랜지스터를 포함하는 반도체 소자 및 그 제조 방법
EP3087586B1 (en) 2013-12-23 2021-09-29 Intel Corporation Advanced etching techniques for straight, tall and uniform fins across multiple fin pitch structures
US9324717B2 (en) * 2013-12-28 2016-04-26 Texas Instruments Incorporated High mobility transistors
KR102168969B1 (ko) * 2014-02-28 2020-10-22 삼성전자주식회사 반도체 장치 및 그 제조 방법
US9847329B2 (en) 2014-09-04 2017-12-19 Taiwan Semiconductor Manufacturing Company, Ltd. Structure of fin feature and method of making same
KR102245133B1 (ko) 2014-10-13 2021-04-28 삼성전자 주식회사 이종 게이트 구조의 finFET를 구비한 반도체 소자 및 그 제조방법
US9653462B2 (en) * 2014-12-26 2017-05-16 Samsung Electronics Co., Ltd. Semiconductor device and method for fabricating the same
KR102274750B1 (ko) 2015-01-27 2021-07-07 삼성전자주식회사 반도체 장치 제조 방법
US9704969B1 (en) * 2015-12-31 2017-07-11 Taiwan Semiconductor Manufacturing Co., Ltd. Fin semiconductor device having multiple gate width structures
JP6856651B2 (ja) * 2016-01-05 2021-04-07 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ 半導体アプリケーション用の水平ゲートオールアラウンドデバイスのためのナノワイヤ製造方法
US10134893B2 (en) 2017-02-22 2018-11-20 International Business Machines Corporation Fabrication of a vertical field effect transistor device with a modified vertical fin geometry
CN109585358B (zh) * 2018-11-06 2020-11-06 上海集成电路研发中心有限公司 一种形成浅沟槽隔离的方法

Family Cites Families (182)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0414868A (ja) * 1990-05-09 1992-01-20 Hitachi Ltd 半導体記憶装置とその製造方法
JP2833946B2 (ja) * 1992-12-08 1998-12-09 日本電気株式会社 エッチング方法および装置
JP3144967B2 (ja) * 1993-11-08 2001-03-12 株式会社日立製作所 半導体集積回路およびその製造方法
KR0146203B1 (ko) * 1995-06-26 1998-12-01 김광호 반도체 집적회로의 회로소자값 조정회로
US5963789A (en) * 1996-07-08 1999-10-05 Kabushiki Kaisha Toshiba Method for silicon island formation
US6065481A (en) * 1997-03-26 2000-05-23 Fsi International, Inc. Direct vapor delivery of enabling chemical for enhanced HF etch process performance
TW468273B (en) * 1997-04-10 2001-12-11 Hitachi Ltd Semiconductor integrated circuit device and method for manufacturing the same
JP3660783B2 (ja) * 1997-06-30 2005-06-15 松下電器産業株式会社 半導体集積回路
TW466405B (en) * 1998-03-17 2001-12-01 Via Tech Inc Device and method of cache in computer system
US6740247B1 (en) * 1999-02-05 2004-05-25 Massachusetts Institute Of Technology HF vapor phase wafer cleaning and oxide etching
JP4037029B2 (ja) 2000-02-21 2008-01-23 株式会社ルネサステクノロジ 半導体集積回路装置
JP4044721B2 (ja) 2000-08-15 2008-02-06 株式会社ルネサステクノロジ 半導体集積回路装置の製造方法
US6558477B1 (en) * 2000-10-16 2003-05-06 Micron Technology, Inc. Removal of photoresist through the use of hot deionized water bath, water vapor and ozone gas
US6830994B2 (en) * 2001-03-09 2004-12-14 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device having a crystallized semiconductor film
US6531412B2 (en) * 2001-08-10 2003-03-11 International Business Machines Corporation Method for low temperature chemical vapor deposition of low-k films using selected cyclosiloxane and ozone gases for semiconductor applications
FR2830984B1 (fr) * 2001-10-17 2005-02-25 St Microelectronics Sa Tranchee d'isolement et procede de realisation
US6737302B2 (en) * 2001-10-31 2004-05-18 Semiconductor Energy Laboratory Co., Ltd. Manufacturing method for field-effect transistor
US6621131B2 (en) * 2001-11-01 2003-09-16 Intel Corporation Semiconductor transistor having a stressed channel
JP4118045B2 (ja) * 2001-12-07 2008-07-16 富士通株式会社 半導体装置
US6642090B1 (en) * 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
JP2004014737A (ja) * 2002-06-06 2004-01-15 Renesas Technology Corp 半導体装置およびその製造方法
US6812103B2 (en) * 2002-06-20 2004-11-02 Micron Technology, Inc. Methods of fabricating a dielectric plug in MOSFETS to suppress short-channel effects
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
US20040011917A1 (en) * 2002-07-18 2004-01-22 Saeks Richard E. Shock wave modification via shock induced ion doping
US7358121B2 (en) 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
JP4031329B2 (ja) * 2002-09-19 2008-01-09 株式会社東芝 半導体装置及びその製造方法
US6791155B1 (en) * 2002-09-20 2004-09-14 Integrated Device Technology, Inc. Stress-relieved shallow trench isolation (STI) structure and method for forming the same
US6833588B2 (en) * 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6946373B2 (en) * 2002-11-20 2005-09-20 International Business Machines Corporation Relaxed, low-defect SGOI for strained Si CMOS applications
KR100450686B1 (ko) * 2002-12-12 2004-10-01 삼성전자주식회사 자기정렬 콘택플러그를 구비한 반도체 소자 및 그 제조방법
US7087499B2 (en) * 2002-12-20 2006-08-08 International Business Machines Corporation Integrated antifuse structure for FINFET and CMOS devices
US20040192067A1 (en) * 2003-02-28 2004-09-30 Bruno Ghyselen Method for forming a relaxed or pseudo-relaxed useful layer on a substrate
DE10310740A1 (de) * 2003-03-10 2004-09-30 Forschungszentrum Jülich GmbH Verfahren zur Herstellung einer spannungsrelaxierten Schichtstruktur auf einem nicht gitterangepassten Substrat, sowie Verwendung eines solchen Schichtsystems in elektronischen und/oder optoelektronischen Bauelementen
US6762448B1 (en) * 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6838322B2 (en) * 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6872647B1 (en) * 2003-05-06 2005-03-29 Advanced Micro Devices, Inc. Method for forming multiple fins in a semiconductor device
US7906441B2 (en) 2003-05-13 2011-03-15 Texas Instruments Incorporated System and method for mitigating oxide growth in a gate dielectric
TWI242232B (en) * 2003-06-09 2005-10-21 Canon Kk Semiconductor substrate, semiconductor device, and method of manufacturing the same
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7101742B2 (en) 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
KR100496891B1 (ko) * 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
JP2005064500A (ja) 2003-08-14 2005-03-10 Samsung Electronics Co Ltd マルチ構造のシリコンフィンおよび製造方法
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
JP4212435B2 (ja) * 2003-08-29 2009-01-21 株式会社東芝 半導体装置およびその製造方法
US7078312B1 (en) * 2003-09-02 2006-07-18 Novellus Systems, Inc. Method for controlling etch process repeatability
US6881668B2 (en) * 2003-09-05 2005-04-19 Mosel Vitel, Inc. Control of air gap position in a dielectric layer
US7303949B2 (en) * 2003-10-20 2007-12-04 International Business Machines Corporation High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture
KR100585111B1 (ko) * 2003-11-24 2006-06-01 삼성전자주식회사 게르마늄 채널 영역을 가지는 비평면 트랜지스터 및 그제조 방법
US7153744B2 (en) * 2003-12-03 2006-12-26 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming self-aligned poly for embedded flash
KR100513405B1 (ko) * 2003-12-16 2005-09-09 삼성전자주식회사 핀 트랜지스터의 형성 방법
KR100702552B1 (ko) 2003-12-22 2007-04-04 인터내셔널 비지네스 머신즈 코포레이션 이중 게이트 ＦｉｎＦＥＴ 디자인을 위한 자동화 레이어생성 방법 및 장치
KR100552058B1 (ko) * 2004-01-06 2006-02-20 삼성전자주식회사 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 제조 방법
KR100587672B1 (ko) * 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
US6956277B1 (en) * 2004-03-23 2005-10-18 Taiwan Semiconductor Manufacturing Company, Ltd. Diode junction poly fuse
US7154118B2 (en) * 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050221591A1 (en) * 2004-04-06 2005-10-06 International Business Machines Corporation Method of forming high-quality relaxed SiGe alloy layers on bulk Si substrates
KR100568448B1 (ko) * 2004-04-19 2006-04-07 삼성전자주식회사 감소된 불순물을 갖는 고유전막의 제조방법
JP4239890B2 (ja) 2004-04-26 2009-03-18 セイコーエプソン株式会社 有機ｅｌ装置、電子機器
US7300837B2 (en) 2004-04-30 2007-11-27 Taiwan Semiconductor Manufacturing Co., Ltd FinFET transistor device on SOI and method of fabrication
KR100605104B1 (ko) * 2004-05-04 2006-07-26 삼성전자주식회사 핀-펫 소자 및 그 제조 방법
JP4493398B2 (ja) * 2004-05-13 2010-06-30 富士通マイクロエレクトロニクス株式会社 半導体装置
US7157351B2 (en) * 2004-05-20 2007-01-02 Taiwan Semiconductor Manufacturing Co., Ltd. Ozone vapor clean method
US20060153995A1 (en) * 2004-05-21 2006-07-13 Applied Materials, Inc. Method for fabricating a dielectric stack
JP4796329B2 (ja) * 2004-05-25 2011-10-19 三星電子株式会社 マルチ−ブリッジチャンネル型ｍｏｓトランジスタの製造方法
US6940747B1 (en) * 2004-05-26 2005-09-06 Hewlett-Packard Development Company, L.P. Magnetic memory device
US7015150B2 (en) * 2004-05-26 2006-03-21 International Business Machines Corporation Exposed pore sealing post patterning
JP5056011B2 (ja) * 2004-06-10 2012-10-24 日本電気株式会社 半導体装置及びその製造方法、ＦｉｎＦＥＴの製造方法
KR100604870B1 (ko) * 2004-06-16 2006-07-31 삼성전자주식회사 접합 영역의 어브럽트니스를 개선시킬 수 있는 전계 효과트랜지스터 및 그 제조방법
US7361563B2 (en) 2004-06-17 2008-04-22 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device using a selective epitaxial growth technique
KR100594282B1 (ko) * 2004-06-28 2006-06-30 삼성전자주식회사 ＦｉｎＦＥＴ을 포함하는 반도체 소자 및 그 제조방법
JP5203558B2 (ja) * 2004-08-20 2013-06-05 三星電子株式会社 トランジスタ及びこれの製造方法
TWI283066B (en) * 2004-09-07 2007-06-21 Samsung Electronics Co Ltd Field effect transistor (FET) having wire channels and method of fabricating the same
US7067400B2 (en) * 2004-09-17 2006-06-27 International Business Machines Corporation Method for preventing sidewall consumption during oxidation of SGOI islands
BRPI0515714A (pt) 2004-09-27 2008-07-29 Dow Global Technologies Inc processo para preparar um revestimento em múltiplas camadas na superfìcie de um substrato polimérico orgánico por meio de uma deposição por plasma à pressão atmosférica
US7018901B1 (en) * 2004-09-29 2006-03-28 Freescale Semiconductor, Inc. Method for forming a semiconductor device having a strained channel and a heterojunction source/drain
KR100585161B1 (ko) * 2004-10-02 2006-05-30 삼성전자주식회사 다중채널 트랜지스터 소자 제조 방법 및 이에 의한 소자
US6949768B1 (en) * 2004-10-18 2005-09-27 International Business Machines Corporation Planar substrate devices integrated with finfets and method of manufacture
KR100652381B1 (ko) * 2004-10-28 2006-12-01 삼성전자주식회사 다수의 나노 와이어 채널을 구비한 멀티 브릿지 채널 전계효과 트랜지스터 및 그 제조방법
KR100605499B1 (ko) * 2004-11-02 2006-07-28 삼성전자주식회사 리세스된 게이트 전극을 갖는 모스 트랜지스터 및 그제조방법
KR100693783B1 (ko) * 2004-11-04 2007-03-12 주식회사 하이닉스반도체 내부전원 발생장치
US7235472B2 (en) * 2004-11-12 2007-06-26 Infineon Technologies Ag Method of making fully silicided gate electrode
US7923339B2 (en) * 2004-12-06 2011-04-12 Nxp B.V. Method of producing an epitaxial layer on semiconductor substrate and device produced with such a method
US7026232B1 (en) * 2004-12-23 2006-04-11 Texas Instruments Incorporated Systems and methods for low leakage strained-channel transistor
US7351662B2 (en) 2005-01-07 2008-04-01 Dupont Air Products Nanomaterials Llc Composition and associated method for catalyzing removal rates of dielectric films during chemical mechanical planarization
US20060151808A1 (en) * 2005-01-12 2006-07-13 Chien-Hao Chen MOSFET device with localized stressor
US7282766B2 (en) * 2005-01-17 2007-10-16 Fujitsu Limited Fin-type semiconductor device with low contact resistance
JP4958797B2 (ja) * 2005-02-24 2012-06-20 ソイテック ＳｉＧｅ層の表面領域を酸化させる方法、ＳＧＯＩ構造体内の少なくとも１つの接合境界面を安定化させる方法、及びＳｉＧｅ層を半導体材料製の基板層と接合する方法
JP2006303451A (ja) * 2005-03-23 2006-11-02 Renesas Technology Corp 半導体装置及び半導体装置の製造方法
US7338614B2 (en) 2005-04-05 2008-03-04 Analog Devices, Inc. Vapor HF etch process mask and method
JP2006324628A (ja) * 2005-05-16 2006-11-30 Interuniv Micro Electronica Centrum Vzw 完全ケイ化ゲート形成方法及び当該方法によって得られたデバイス
JP4427489B2 (ja) * 2005-06-13 2010-03-10 株式会社東芝 半導体装置の製造方法
US7547637B2 (en) * 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7960791B2 (en) 2005-06-24 2011-06-14 International Business Machines Corporation Dense pitch bulk FinFET process by selective EPI and etch
KR100655788B1 (ko) * 2005-06-30 2006-12-08 삼성전자주식회사 반도체 소자의 세정방법 및 이를 이용한 반도체 소자의제조방법.
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7265008B2 (en) 2005-07-01 2007-09-04 Synopsys, Inc. Method of IC production using corrugated substrate
US7605449B2 (en) 2005-07-01 2009-10-20 Synopsys, Inc. Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material
US7247887B2 (en) 2005-07-01 2007-07-24 Synopsys, Inc. Segmented channel MOS transistor
US8466490B2 (en) 2005-07-01 2013-06-18 Synopsys, Inc. Enhanced segmented channel MOS transistor with multi layer regions
US7190050B2 (en) 2005-07-01 2007-03-13 Synopsys, Inc. Integrated circuit on corrugated substrate
US7807523B2 (en) 2005-07-01 2010-10-05 Synopsys, Inc. Sequential selective epitaxial growth
US7508031B2 (en) 2005-07-01 2009-03-24 Synopsys, Inc. Enhanced segmented channel MOS transistor with narrowed base regions
EP1744351A3 (en) 2005-07-11 2008-11-26 Interuniversitair Microelektronica Centrum ( Imec) Method for forming a fully silicided gate MOSFET and devices obtained thereof
JP4774247B2 (ja) 2005-07-21 2011-09-14 Ｏｋｉセミコンダクタ株式会社 電圧レギュレータ
KR101172853B1 (ko) 2005-07-22 2012-08-10 삼성전자주식회사 반도체 소자의 형성 방법
JP4749076B2 (ja) 2005-07-27 2011-08-17 ルネサスエレクトロニクス株式会社 半導体装置
US20070029576A1 (en) 2005-08-03 2007-02-08 International Business Machines Corporation Programmable semiconductor device containing a vertically notched fusible link region and methods of making and using same
KR101155097B1 (ko) * 2005-08-24 2012-06-11 삼성전자주식회사 반도체 장치의 제조 방법 및 그에 의해 제조된 반도체 장치
US7589387B2 (en) 2005-10-05 2009-09-15 Taiwan Semiconductor Manufacturing Company, Ltd. SONOS type two-bit FinFET flash memory cell
US7425740B2 (en) 2005-10-07 2008-09-16 Taiwan Semiconductor Manufacturing Company, Ltd. Method and structure for a 1T-RAM bit cell and macro
US8513066B2 (en) 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US7767541B2 (en) 2005-10-26 2010-08-03 International Business Machines Corporation Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods
DE102005052055B3 (de) 2005-10-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Eingebettete Verformungsschicht in dünnen SOI-Transistoren und Verfahren zur Herstellung desselben
US20070102756A1 (en) * 2005-11-10 2007-05-10 Bohumil Lojek FinFET transistor fabricated in bulk semiconducting material
US7718500B2 (en) 2005-12-16 2010-05-18 Chartered Semiconductor Manufacturing, Ltd Formation of raised source/drain structures in NFET with embedded SiGe in PFET
US7525160B2 (en) 2005-12-27 2009-04-28 Intel Corporation Multigate device with recessed strain regions
US20070152276A1 (en) 2005-12-30 2007-07-05 International Business Machines Corporation High performance CMOS circuits, and methods for fabricating the same
US7410844B2 (en) 2006-01-17 2008-08-12 International Business Machines Corporation Device fabrication by anisotropic wet etch
JP2007194336A (ja) * 2006-01-18 2007-08-02 Sumco Corp 半導体ウェーハの製造方法
KR100827435B1 (ko) 2006-01-31 2008-05-06 삼성전자주식회사 반도체 소자에서 무산소 애싱 공정을 적용한 게이트 형성방법
JP2007258485A (ja) * 2006-03-23 2007-10-04 Toshiba Corp 半導体装置及びその製造方法
JP4791868B2 (ja) * 2006-03-28 2011-10-12 株式会社東芝 Ｆｉｎ−ＮＡＮＤ型フラッシュメモリ
US7407847B2 (en) 2006-03-31 2008-08-05 Intel Corporation Stacked multi-gate transistor design and method of fabrication
KR100813527B1 (ko) 2006-04-06 2008-03-17 주식회사 하이닉스반도체 반도체 메모리의 내부 전압 발생 장치
US8076189B2 (en) 2006-04-11 2011-12-13 Freescale Semiconductor, Inc. Method of forming a semiconductor device and semiconductor device
EP1868233B1 (fr) * 2006-06-12 2009-03-11 Commissariat A L'energie Atomique Procédé de réalisation de zones à base de Si1-yGey de différentes teneurs en Ge sur un même substrat par condensation de germanium
JP4271210B2 (ja) 2006-06-30 2009-06-03 株式会社東芝 電界効果トランジスタ、集積回路素子、及びそれらの製造方法
KR100876778B1 (ko) * 2006-07-28 2009-01-07 주식회사 하이닉스반도체 반도체 소자 및 그의 형성 방법
US8211761B2 (en) * 2006-08-16 2012-07-03 Globalfoundries Singapore Pte. Ltd. Semiconductor system using germanium condensation
US7685911B2 (en) * 2006-09-05 2010-03-30 Proxene Tools Co., Ltd. Monkey wrench
US7554110B2 (en) 2006-09-15 2009-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. MOS devices with partial stressor channel
US7494862B2 (en) 2006-09-29 2009-02-24 Intel Corporation Methods for uniform doping of non-planar transistor structures
US7410854B2 (en) 2006-10-05 2008-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making FUSI gate and resulting structure
CN100527380C (zh) 2006-11-06 2009-08-12 北京北方微电子基地设备工艺研究中心有限责任公司 硅片浅沟槽隔离刻蚀的方法
US7534689B2 (en) 2006-11-21 2009-05-19 Advanced Micro Devices, Inc. Stress enhanced MOS transistor and methods for its fabrication
US7943469B2 (en) 2006-11-28 2011-05-17 Intel Corporation Multi-component strain-inducing semiconductor regions
JP2008147414A (ja) * 2006-12-11 2008-06-26 Matsushita Electric Ind Co Ltd 半導体装置および半導体装置の製造方法
US7538387B2 (en) 2006-12-29 2009-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Stack SiGe for short channel improvement
US20080157225A1 (en) * 2006-12-29 2008-07-03 Suman Datta SRAM and logic transistors with variable height multi-gate transistor architecture
US7803680B2 (en) * 2007-01-12 2010-09-28 Spansion Llc Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications
US7456087B2 (en) 2007-02-09 2008-11-25 United Microelectronics Corp. Semiconductor device and method of fabricating the same
JP2008227026A (ja) 2007-03-12 2008-09-25 Toshiba Corp 半導体装置の製造方法
KR100844938B1 (ko) 2007-03-16 2008-07-09 주식회사 하이닉스반도체 반도체 소자 및 그 제조 방법
US7727842B2 (en) 2007-04-27 2010-06-01 Texas Instruments Incorporated Method of simultaneously siliciding a polysilicon gate and source/drain of a semiconductor device, and related device
TW200847292A (en) * 2007-05-29 2008-12-01 Nanya Technology Corp Method of manufacturing a self-aligned FinFET device
US7939862B2 (en) 2007-05-30 2011-05-10 Synopsys, Inc. Stress-enhanced performance of a FinFet using surface/channel orientations and strained capping layers
TW200901368A (en) 2007-06-23 2009-01-01 Promos Technologies Inc Shallow trench isolation structure and method for forming thereof
JP2009016418A (ja) 2007-07-02 2009-01-22 Nec Electronics Corp 半導体装置
US7851865B2 (en) 2007-10-17 2010-12-14 International Business Machines Corporation Fin-type field effect transistor structure with merged source/drain silicide and method of forming the structure
US8063437B2 (en) 2007-07-27 2011-11-22 Panasonic Corporation Semiconductor device and method for producing the same
US7692213B2 (en) * 2007-08-07 2010-04-06 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing a condensation process
US20090053883A1 (en) 2007-08-24 2009-02-26 Texas Instruments Incorporated Method of setting a work function of a fully silicided semiconductor device, and related device
JP2009054705A (ja) 2007-08-24 2009-03-12 Toshiba Corp 半導体基板、半導体装置およびその製造方法
JP4361102B2 (ja) 2007-09-12 2009-11-11 富士フイルム株式会社 圧電素子の製造方法
JP2009088522A (ja) * 2007-09-28 2009-04-23 Hynix Semiconductor Inc 半導体装置のリセスゲート製造方法
KR100915085B1 (ko) * 2007-10-29 2009-09-07 주식회사 하이닉스반도체 반도체 소자의 형성 방법
US7985633B2 (en) * 2007-10-30 2011-07-26 International Business Machines Corporation Embedded DRAM integrated circuits with extremely thin silicon-on-insulator pass transistors
US7795097B2 (en) 2007-11-20 2010-09-14 Texas Instruments Incorporated Semiconductor device manufactured by removing sidewalls during replacement gate integration scheme
US7767579B2 (en) * 2007-12-12 2010-08-03 International Business Machines Corporation Protection of SiGe during etch and clean operations
CN101459116B (zh) 2007-12-13 2010-06-09 中芯国际集成电路制造(上海)有限公司 浅沟槽隔离结构的制造方法
US20090166625A1 (en) * 2007-12-28 2009-07-02 United Microelectronics Corp. Mos device structure
US8189376B2 (en) * 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
EP2257974A1 (en) 2008-02-26 2010-12-08 Nxp B.V. Method for manufacturing semiconductor device and semiconductor device
US8003466B2 (en) 2008-04-08 2011-08-23 Advanced Micro Devices, Inc. Method of forming multiple fins for a semiconductor device
WO2009144874A1 (en) 2008-05-29 2009-12-03 Panasonic Corporation Finfet with impurity blocking portion on an upper surface of fin
DE102008030864B4 (de) 2008-06-30 2010-06-17 Advanced Micro Devices, Inc., Sunnyvale Halbleiterbauelement als Doppelgate- und Tri-Gatetransistor, die auf einem Vollsubstrat aufgebaut sind und Verfahren zur Herstellung des Transistors
US8000240B2 (en) * 2008-07-07 2011-08-16 Verizon Patent And Licensing Inc. Method and system for providing auto-bandwidth adjustment
KR101113794B1 (ko) * 2008-08-04 2012-02-27 주식회사 하이닉스반도체 반도체 장치 제조 방법
US7923321B2 (en) 2008-11-03 2011-04-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method for gap filling in a gate last process
US8247285B2 (en) 2008-12-22 2012-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. N-FET with a highly doped source/drain and strain booster
US8361871B2 (en) * 2008-12-24 2013-01-29 Intel Corporation Trigate static random-access memory with independent source and drain engineering, and devices made therefrom
US8120063B2 (en) 2008-12-29 2012-02-21 Intel Corporation Modulation-doped multi-gate devices
CA2659912C (en) 2009-03-24 2012-04-24 Sarah Mary Brunet Nasal prong protector
US8236658B2 (en) 2009-06-03 2012-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming a transistor with a strained channel
US8759943B2 (en) * 2010-10-08 2014-06-24 Taiwan Semiconductor Manufacturing Company, Ltd. Transistor having notched fin structure and method of making the same
US8043920B2 (en) 2009-09-17 2011-10-25 International Business Machines Corporation finFETS and methods of making same
US7993999B2 (en) 2009-11-09 2011-08-09 International Business Machines Corporation High-K/metal gate CMOS finFET with improved pFET threshold voltage
US8114761B2 (en) 2009-11-30 2012-02-14 Applied Materials, Inc. Method for doping non-planar transistors
US8785286B2 (en) 2010-02-09 2014-07-22 Taiwan Semiconductor Manufacturing Company, Ltd. Techniques for FinFET doping
US8088685B2 (en) 2010-02-09 2012-01-03 Taiwan Semiconductor Manufacturing Company, Ltd. Integration of bottom-up metal film deposition
US20110256682A1 (en) 2010-04-15 2011-10-20 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple Deposition, Multiple Treatment Dielectric Layer For A Semiconductor Device

Also Published As

Publication number Publication date
US9484462B2 (en) 2016-11-01
US20110068405A1 (en) 2011-03-24
US10355108B2 (en) 2019-07-16
US20190341473A1 (en) 2019-11-07
JP5356344B2 (ja) 2013-12-04
US20170117388A1 (en) 2017-04-27
KR20110033039A (ko) 2011-03-30
KR101295425B1 (ko) 2013-08-09
US11158725B2 (en) 2021-10-26
TW201112421A (en) 2011-04-01
TWI517384B (zh) 2016-01-11
JP2011071520A (ja) 2011-04-07
CN102034868A (zh) 2011-04-27

Similar Documents

Publication Publication Date Title
CN102034868B (zh) 半导体装置及场效应晶体管
US10134761B2 (en) Semiconductor device and FinFET transistor
KR101637679B1 (ko) Ｆⅰｎｆｅｔ을 형성하기 위한 메커니즘들을 포함하는 반도체 디바이스및 그 형성 방법
US6855588B1 (en) Method of fabricating a double gate MOSFET device
US8373199B2 (en) Semiconductor device having a SiGe feature and a metal gate stack
US9741810B2 (en) Strained channel of gate-all-around transistor
US20070093010A1 (en) Method of making an inverted-T channel transistor
US20080230852A1 (en) Fabrication of FinFETs with multiple fin heights
CN102117829A (zh) 鳍式晶体管结构及其制作方法
US11011618B2 (en) Circuit devices with gate seals
US20190355720A1 (en) Semiconductor structure and fabrication method thereof
TWI710030B (zh) 半導體元件及半導體元件的製造方法
CN106935505B (zh) 鳍式场效应晶体管的形成方法
CN104332410A (zh) 一种鳍式场效应晶体管的制造方法
US10930785B2 (en) Semiconductor device
US9905480B1 (en) Semiconductor devices and methods for forming the same
CN107579108B (zh) 半导体结构的形成方法
EP3291291B1 (en) Semiconductor device and fabrication method thereof
JP2007519217A (ja) 半導体デバイスおよびその製造方法
JP2006196736A (ja) 半導体装置及びその製造方法
CN104362097A (zh) 一种鳍式场效应晶体管的制造方法
KR100714929B1 (ko) 변형된 ＦｉｎＦＥＴ ＣＭＯＳ 장치 구조
CN104347427A (zh) 一种鳍式场效应晶体管的制造方法
CN104078355A (zh) 鳍式场效应晶体管的形成方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant