TW200737383A - Substrate with built-in chip and method for manufacturing substrate with built-in chip - Google Patents

Substrate with built-in chip and method for manufacturing substrate with built-in chip

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Publication number
TW200737383A
TW200737383A TW095146596A TW95146596A TW200737383A TW 200737383 A TW200737383 A TW 200737383A TW 095146596 A TW095146596 A TW 095146596A TW 95146596 A TW95146596 A TW 95146596A TW 200737383 A TW200737383 A TW 200737383A
Authority
TW
Taiwan
Prior art keywords
substrate
chip
built
wiring
manufacturing
Prior art date
Application number
TW095146596A
Other languages
English (en)
Other versions
TWI361467B (zh
Inventor
Takaharu Yamano
Hajime Iizuka
Hideaki Sakaguchi
Toshio Kobayashi
Tadashi Arai
Kobayashi Tsuyoshi
Koyama Tetsuya
Iida Kiyoaki
Mashima Tomoaki
Tanaka Koichi
Kunimoto Yuji
Yanagisawa Takashi
Original Assignee
Shinko Electric Ind Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Ind Co filed Critical Shinko Electric Ind Co
Publication of TW200737383A publication Critical patent/TW200737383A/zh
Application granted granted Critical
Publication of TWI361467B publication Critical patent/TWI361467B/zh

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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H01L21/4814—Conductive parts
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    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10T29/49117—Conductor or circuit manufacturing
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    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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  • Power Engineering (AREA)
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TW095146596A 2005-12-14 2006-12-13 Substrate with built-in chip and method for manufacturing substrate with built-in chip TW200737383A (en)

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JP2006117618 2006-04-21

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