TWI567886B - 晶片封裝結構以及晶片封裝結構的製作方法 - Google Patents
晶片封裝結構以及晶片封裝結構的製作方法 Download PDFInfo
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- 238000000034 method Methods 0.000 title claims description 40
- 239000000758 substrate Substances 0.000 claims description 77
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 239000000945 filler Substances 0.000 claims description 10
- 239000000463 material Substances 0.000 claims description 10
- 238000000059 patterning Methods 0.000 claims description 10
- 238000000206 photolithography Methods 0.000 claims description 10
- 239000004642 Polyimide Substances 0.000 claims description 6
- 229920001721 polyimide Polymers 0.000 claims description 6
- 229910000679 solder Inorganic materials 0.000 claims description 6
- 238000003825 pressing Methods 0.000 claims description 4
- 238000009713 electroplating Methods 0.000 claims description 3
- 230000035939 shock Effects 0.000 claims 1
- 239000010410 layer Substances 0.000 description 114
- 235000012431 wafers Nutrition 0.000 description 29
- 230000035945 sensitivity Effects 0.000 description 7
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 5
- 239000002335 surface treatment layer Substances 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- 239000003292 glue Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- 239000000084 colloidal system Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- MSNOMDLPLDYDME-UHFFFAOYSA-N gold nickel Chemical compound [Ni].[Au] MSNOMDLPLDYDME-UHFFFAOYSA-N 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- BSIDXUHWUKTRQL-UHFFFAOYSA-N nickel palladium Chemical compound [Ni].[Pd] BSIDXUHWUKTRQL-UHFFFAOYSA-N 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
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- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H01L2224/812—Applying energy for connecting
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- H01L2224/812—Applying energy for connecting
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- H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
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- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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Description
本發明是有關於一種半導體封裝結構以及半導體封裝結構的製作方法,且特別是有關於一種指紋感測晶片封裝結構以及指紋感測晶片封裝結構的製作方法。
指紋感測封裝構造能附加裝設於各式之電子產品,例如行動電話、筆記型電腦、平板電腦等,用以辨認使用者之指紋。目前指紋辨識器已可利用半導體製程製作並加以封裝,不同於傳統的IC封裝,指紋感測晶片應具有一外露的感測區,方可辨識指紋。
一般而言,指紋感測封裝構造主要包含基板、一指紋感測晶片以及一填充膠體。指紋感測晶片之一主動面上具有一感測區,其中,指紋感測晶片設置在基板之上表面,並例如透過金線電性連接指紋感測晶片的焊墊至基板上的訊號傳輸線路。填充膠體係形成於指紋感測晶片表面之局部以包覆金線,但由於指紋感測區為裸露狀態,因此容易因碰撞而損壞或受潮。並且,為防止
金線外露,填充膠體的厚度較厚,因而導致指紋感測區與膠體表面的高度差增加,甚而導致指紋辨識的靈敏度降低。
本發明提供一種晶片封裝結構,其具有覆蓋指紋感測線路的圖案化介電層,此圖案化介電層的厚度可薄化且厚度均勻,並可提升指紋辨識之靈敏度。
本發明提供一種晶片封裝結構的製作方法,其所製作出的晶片封裝結構具有覆蓋指紋感測線路的圖案化介電層,此圖案化介電層的厚度可薄化且厚度均勻,並可提升指紋辨識之靈敏度。
本發明的晶片封裝結構包括一可撓性基材、一圖案化線路層、一指紋感測晶片、多個凸塊、一圖案化介電層及一填充膠層。圖案化線路層設置於可撓性基材上並包括一指紋感測線路以及多個接點。指紋感測晶片設置於可撓性基材上並電性連接指紋感測線路。指紋感測晶片包括一主動表面、一背面及多個設置於主動表面的焊墊。凸塊設置於指紋感測晶片與圖案化線路層之間,以分別電性連接焊墊與接點。圖案化介電層包括相對的一第一表面及一第二表面。圖案化介電層以第一表面至少覆蓋指紋感測線路。第二表面具有一指紋感應區。填充膠層填充於可撓性基材與指紋感測晶片之間,並包覆凸塊。
本發明的晶片封裝結構的製作方法包括下列步驟。首先,提供一可撓性基材。接著,形成一導電層於可撓性基材上。
接著,對導電層進行一圖案化製程,以形成一圖案化線路層於可撓性基材上。圖案化線路層包括一指紋感測線路。接著,形成一介電層於可撓性基材上。介電層覆蓋圖案化線路層。之後,對介電層進行一圖案化製程,以形成一圖案化介電層。圖案化介電層包括相對的一第一表面以及一第二表面,圖案化介電層以第一表面至少覆蓋指紋感測線路,第二表面具有一指紋感應區。接著,設置一指紋感測晶片於可撓性基材上,並透過多個凸塊將指紋感測晶片電性連接至指紋感測線路。接著,填充一填充膠層於可撓性基材與指紋感測晶片之間,填充膠層包覆凸塊。
在本發明的一實施例中,上述的可撓性基材的一厚度大於圖案化介電層的一厚度。
在本發明的一實施例中,上述的圖案化介電層的厚度實質上不大於10微米。
在本發明的一實施例中,上述的圖案化介電層的厚度實質上介於4至8微米。
在本發明的一實施例中,上述的晶片封裝結構更包括一種子層,設置於可撓性基材與圖案化線路層之間。
在本發明的一實施例中,上述的圖案化介電層以及可撓性基材的材料包括聚醯亞胺。
在本發明的一實施例中,上述的填充膠層包括底部填充膠、非導電性膠、非導電性薄膜、異方性導電膠或異方性導電薄膜。
在本發明的一實施例中,上述的形成導電層於可撓性基材上的步驟更包括:形成一種子層於可撓性基材上,以及以種子層做為電極進行一電鍍製程,以形成導電層於可撓性基材上。
在本發明的一實施例中,上述的對導電層進行圖案化製程的步驟更包括:對導電層以及種子層進行圖案化製程。
在本發明的一實施例中,上述的對介電層進行一圖案化製程的步驟包括一光微影蝕刻製程。
在本發明的一實施例中,上述的設置指紋感測晶片於可撓性基材上的方法包括熱壓合。
在本發明的一實施例中,上述的設置指紋感測晶片於可撓性基材上的方法包括透過壓合將指紋感測晶片設置於可撓性基材上,並在壓合的過程中施加一超音波震盪。
基於上述,本發明例如透過光微影蝕刻製程來形成覆蓋指紋感測線路的圖案化介電層,以防止指紋感測線路損壞或受潮。如此,由於圖案化介電層的厚度可由光阻層所控制,因而得以形成厚度較薄且厚度均勻的圖案化介電層,進而可提升指紋辨識的靈敏度。
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。
100‧‧‧晶片封裝結構
110‧‧‧可撓性基材
115‧‧‧種子層
120‧‧‧導電層
122‧‧‧圖案化線路層
122a‧‧‧指紋感測線路
122b‧‧‧接點
130‧‧‧介電層
132‧‧‧圖案化介電層
132a‧‧‧第一表面
132b‧‧‧第二表面
140‧‧‧指紋感測晶片
142‧‧‧主動表面
144‧‧‧背面
146‧‧‧焊墊
150‧‧‧凸塊
160‧‧‧填充膠層
170‧‧‧表面處理層
R1‧‧‧指紋感應區
圖1A至圖1H是依照本發明的一實施例的一種晶片封裝結構的製作方法的流程剖面示意圖。
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之各實施例的詳細說明中,將可清楚的呈現。以下實施例中所提到的方向用語,例如:「上」、「下」、「前」、「後」、「左」、「右」等,僅是參考附加圖式的方向。因此,使用的方向用語是用來說明,而並非用來限制本發明。並且,在下列各實施例中,相同或相似的元件將採用相同或相似的標號。
圖1A至圖1H是依照本發明的一實施例的一種晶片封裝
結構的製作方法的流程剖面示意圖。本實施例的晶片封裝結構的製作方法可包括下列步驟:首先,如圖1A所示,提供一可撓性基材110。在本實施例中,可撓性基材110可為薄膜覆晶(chip on film,COF)基材或是其他的可撓性基材,其材料可為聚醯亞胺(Polyimide,PI)或其他適當材料。此外,本實施例的可撓性基材110的厚度實質上可介於25至38微米(μm)之間。當然,任何所屬技術領域中具有通常知識者應了解,本實施例僅用以舉例說明,使用者可依實際產品需求自行對可撓性基材110的厚度作調整。接著,再如圖1B所示,形成一導電層120於可撓性基材110上。詳細來說,可例如先於可撓性基材110上形成如圖1B所示的種子層115,之後,再以此種子層115做為電極來進行電鍍製程,
以於可撓性基材110上形成如圖1B所示的導電層120。在本實施例中,導電層120可例如為一銅層,當然,本實施例僅用以舉例說明,本發明並不以此為限。
接著,請參照圖1C,對如圖1B所示的導電層120以及種子層115進行一圖案化製程,以形成如圖1C所示的圖案化線路層122於可撓性基材110上,其中,圖案化線路層122包括指紋感測線路122a以及多個用於電性連接的接點122b。之後,可再於圖案化線路層122上形成如圖1D所示的表面處理層170。本實施例中,表面處理層170可為金層、錫層、鎳金層、鎳鈀金層或有機防焊層等。當然,本實施例僅用以舉例說明,本發明並不限制表面處理層170的材料及種類。
接著,請參照圖1E,形成一介電層130於可撓性基材110上,其中,介電層130覆蓋圖案化線路層122以及被圖案化線路層122所暴露的部份可撓性基材110。之後,再對介電層130進行一圖案化製程,以形成如圖1F所示的圖案化介電層132。在本實施例中,圖案化介電層132的材料可例如為聚醯亞胺,而前述的圖案化製程可為光微影蝕刻(Photolithography)製程。因此,透過光微影蝕刻製程所形成的圖案化介電層132,其厚度可由光微影蝕刻製程中的光阻層所控制,因而得以形成相對於可撓性基材110來說厚度較薄的圖案化介電層132,也就是說,依此製程所形成的圖案化介電層132的厚度實質上小於可撓性基材110的厚度。舉例而言,圖案化介電層132的厚度實質上不大於10微米。更具體
來說,圖案化介電層132的厚度約可介於4至8微米之間。此外,透過光微影蝕刻製程所形成之圖案化介電層132的厚度也較為均勻。除此之外,圖案化介電層132包括相對的一第一表面132a及一第二表面132b,而圖案化介電層130以其第一表面132a至少覆蓋指紋感測線路122a,並暴露出接點122b。
接著,請參照圖1G,設置一指紋感測晶片140於可撓性基材110上,並透過多個凸塊150將指紋感測晶片140電性連接至指紋感測線路122a。具體而言,指紋感測晶片140包括一主動表面142、一背面144及多個設置於主動表面142的焊墊146,而凸塊150則是設置於指紋感測晶片140與圖案化線路層122之間,以分別電性連接焊墊146與接點122b,以將指紋感測晶片140電性連接至指紋感測線路122a。在本實施例中,設置指紋感測晶片140於可撓性基材110的方法可例如透過熱壓合(Thermocompression Bonding)、超音波接合(Ultrasonic Bonding)或熱超音波接合(Thermosonic Bonding)等方式。
接著,再如圖1H所示,填充一填充膠層160於可撓性基材110與指紋感測晶片140之間,且填充膠層160如圖1H所示包覆凸塊150。在本發明的一實施例中,填充膠層160可為底部填充膠(underfill),於指紋感測晶片140透過例如熱壓合的方式設置於可撓性基板110上之後,再將填充膠層160利用例如點膠的方式及毛細現象填充於可撓性基材110與指紋感測晶片140之間。在本發明的另一實施例中,填充膠層160可為非導電性膠
(Non-Conductive Paste,NCP)或非導電性薄膜(Non-Conductive Film,NCF),而在此實施例中,可例如先將填充膠層160塗佈於可撓性基材110上,再將指紋感測晶片140透過例如熱壓合的方式設置於可撓性基板110上,而使填充膠層160填充於可撓性基材110與指紋感測晶片140之間。
在本發明的另一實施例中,指紋感測晶片140亦可透過超音波接合或熱超音波接合的方式設置於可撓性基材110上,亦即,在壓合/熱壓合指紋感測晶片140於可撓性基材110上的過程中施加一超音波(Ultrasonic)震盪,以進行金屬介面之接合。在本實施例中,填充膠層160可為非導電性膠、非導電性薄膜、異方性導電膠(Anisotropic Conductive Paste,ACP)或異方性導電薄膜(Anisotropic Conductive Film,ACF)等,且可先將填充膠層160塗佈於可撓性基材110上,再將指紋感測晶片140設置於可撓性基板110上,而使填充膠層160填充於可撓性基材110與指紋感測晶片140之間。
當然,在本發明的另一實施例中,填充膠層160亦可為異方性導電膠或異方性導電薄膜,在此實施例中,可例如先將填充膠層160塗佈於可撓性基材110上,再直接壓合指紋感測晶片140於可撓性基材110上,而無須施加熱及/或超音波震盪,如此,即可利用異方性導電膠或異方性導電薄膜中的導電粒子使指紋感測晶片140與可撓性基板110做電性連接,並利用異方性導電膠或異方性導電薄膜的介電膠將指紋感測晶片140與可撓性基板110
做結構性連接並包覆凸塊150。
如此配置,即大致完成晶片封裝結構100的製作。依上述製程所製作出的晶片封裝結構100如圖1H所示包括可撓性基材110、圖案化線路層122、指紋感測晶片140、多個凸塊150、圖案化介電層132以及填充膠層160,其中,圖案化線路層122設置於可撓性基材110上,並包括指紋感測線路122a以及多個接點122b。指紋感測晶片140設置於可撓性基材110上並電性連接指紋感測線路122a。指紋感測晶片140包括主動表面142、背面144及多個設置於主動表面142的焊墊146。凸塊150如圖1H所示之設置於指紋感測晶片140與圖案化線路層122之間,以分別電性連接焊墊146與接點122b。
承上述,圖案化介電層132包括相對的第一表面132a及第二表面132b,並以其第一表面132a至少覆蓋指紋感測線路122a,而第二表面132b如圖1H所示之具有一指紋感應區R1,用以接收使用者的指紋,使指紋感測線路122a產生電荷變化並傳遞訊號至指紋感測晶片140進行演算,以辨識指紋。因此,可依據圖案化介電層132的材料特性,例如介電常數(k值)等,來選擇有助於指紋感測線路122a感應使用者之指紋的材質,以提升指紋辨識之靈敏度。而填充膠層160則填充於可撓性基材110與指紋感測晶片140之間,並包覆凸塊150。
綜上所述,本發明將光微影蝕刻製程應用至指紋感測晶片的封裝結構上,也就是透過光微影蝕刻製程來形成圖案化介電
層,以此覆蓋指紋感測線路,避免指紋感測線路損壞或受潮。並且,由於圖案化介電層的厚度可由光微影蝕刻製程中的光阻層所控制,因而得以形成厚度較薄且較為均勻的圖案化介電層,進而可減少本發明的晶片封裝結構的厚度以及提升指紋辨識的靈敏度。再者,透過對圖案化介電層材料特性的選擇,亦可提升指紋辨識的靈敏度。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
100‧‧‧晶片封裝結構
110‧‧‧可撓性基材
115‧‧‧種子層
122‧‧‧圖案化線路層
122a‧‧‧指紋感測線路
122b‧‧‧接點
132‧‧‧圖案化介電層
132a‧‧‧第一表面
132b‧‧‧第二表面
140‧‧‧指紋感測晶片
142‧‧‧主動表面
144‧‧‧背面
146‧‧‧焊墊
150‧‧‧凸塊
160‧‧‧填充膠層
R1‧‧‧指紋感應區
Claims (15)
- 一種晶片封裝結構,包括:一可撓性基材;一圖案化線路層,設置於該可撓性基材上,該圖案化線路層包括一指紋感測線路以及多個接點;一指紋感測晶片,設置於該可撓性基材上並電性連接該指紋感測線路,該指紋感測晶片包括一主動表面、一背面以及多個焊墊,該些焊墊設置於該主動表面;多個凸塊,設置於該指紋感測晶片與該圖案化線路層之間,以分別電性連接該些焊墊與該些接點;一圖案化介電層,包括相對的一第一表面以及一第二表面,該圖案化介電層以該第一表面至少覆蓋該指紋感測線路,該第二表面具有一指紋感應區,其中該可撓性基材的一厚度大於該圖案化介電層的一厚度;以及一填充膠層,填充於該可撓性基材與該指紋感測晶片之間,並且包覆該些凸塊。
- 如申請專利範圍第1項所述的晶片封裝結構,其中該圖案化介電層的厚度實質上不大於10微米。
- 如申請專利範圍第1項所述的晶片封裝結構,其中該圖案化介電層的厚度實質上介於4至8微米。
- 如申請專利範圍第1項所述的晶片封裝結構,更包括一種子層,設置於該可撓性基材與該圖案化線路層之間。
- 如申請專利範圍第1項所述的晶片封裝結構,其中該圖案化介電層以及該可撓性基材的材料包括聚醯亞胺(Polyimide,PI)。
- 如申請專利範圍第1項所述的晶片封裝結構,其中該填充膠層包括底部填充膠(underfill)、非導電性膠(Non-Conductive Paste,NCP)、非導電性薄膜(Non-Conductive Film,NCF)、異方性導電膠(Anisotropic Conductive Paste,ACP)或異方性導電薄膜(Anisotropic Conductive Film,ACF)。
- 一種晶片封裝結構的製作方法,包括:提供一可撓性基材;形成一導電層於該可撓性基材上;對該導電層進行一圖案化製程,以形成一圖案化線路層於該可撓性基材上,該圖案化線路層包括一指紋感測線路;形成一介電層於該可撓性基材上,該介電層覆蓋該圖案化線路層;對該介電層進行一圖案化製程,以形成一圖案化介電層,該圖案化介電層包括相對的一第一表面以及一第二表面,該圖案化介電層以該第一表面至少覆蓋該指紋感測線路,該第二表面具有一指紋感應區;設置一指紋感測晶片於該可撓性基材上,並透過多個凸塊將該指紋感測晶片電性連接至該指紋感測線路;以及填充一填充膠層於該可撓性基材與該指紋感測晶片之間,該 填充膠層包覆該些凸塊。
- 如申請專利範圍第7項所述的晶片封裝結構的製作方法,其中形成該導電層於該可撓性基材上的步驟更包括:形成一種子層於該可撓性基材上;以及以該種子層做為電極進行一電鍍製程,以形成該導電層於該可撓性基材上。
- 如申請專利範圍第8項所述的晶片封裝結構的製作方法,其中對該導電層進行該圖案化製程的步驟更包括:對該導電層以及該種子層進行該圖案化製程。
- 如申請專利範圍第7項所述的晶片封裝結構的製作方法,其中對該介電層進行一圖案化製程的步驟包括一光微影蝕刻製程。
- 如申請專利範圍第7項所述的晶片封裝結構的製作方法,其中設置該指紋感測晶片於該可撓性基材上的方法包括熱壓合。
- 如申請專利範圍第11項所述的晶片封裝結構的製作方法,其中該填充膠層包括底部填充膠、非導電性膠或非導電性薄膜。
- 如申請專利範圍第7項所述的晶片封裝結構的製作方法,其中設置該指紋感測晶片於該可撓性基材上的方法包括透過壓合將該指紋感測晶片設置於該可撓性基材上,並在壓合的過程 中施加一超音波(Ultrasonic)震盪。
- 如申請專利範圍第13項所述的晶片封裝結構的製作方法,其中該填充膠層包括非導電性膠、非導電性薄膜、異方性導電膠或異方性導電薄膜。
- 如申請專利範圍第7項所述的晶片封裝結構的製作方法,其中該填充膠層包括異方性導電膠或異方性導電薄膜。
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TW103118657A TWI567886B (zh) | 2014-05-28 | 2014-05-28 | 晶片封裝結構以及晶片封裝結構的製作方法 |
CN201410403960.2A CN105280577A (zh) | 2014-05-28 | 2014-08-15 | 芯片封装结构以及芯片封装结构的制作方法 |
US14/477,870 US20150347806A1 (en) | 2014-05-28 | 2014-09-05 | Chip package structure and method for manufacturing chip package structure |
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