TWI449271B - 具有連接介面的電子裝置、其電路基板以及其製造方法 - Google Patents

具有連接介面的電子裝置、其電路基板以及其製造方法 Download PDF

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Publication number
TWI449271B
TWI449271B TW100141895A TW100141895A TWI449271B TW I449271 B TWI449271 B TW I449271B TW 100141895 A TW100141895 A TW 100141895A TW 100141895 A TW100141895 A TW 100141895A TW I449271 B TWI449271 B TW I449271B
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Taiwan
Prior art keywords
opening
layer
circuit layer
circuit
pads
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TW100141895A
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English (en)
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TW201322559A (zh
Inventor
Diann Fang Lin
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Dawning Leading Technology Inc
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Application filed by Dawning Leading Technology Inc filed Critical Dawning Leading Technology Inc
Priority to TW100141895A priority Critical patent/TWI449271B/zh
Priority to CN2012104057476A priority patent/CN103117262A/zh
Priority to US13/678,898 priority patent/US20130120947A1/en
Publication of TW201322559A publication Critical patent/TW201322559A/zh
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Publication of TWI449271B publication Critical patent/TWI449271B/zh

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    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4007Surface contacts, e.g. bumps
    • H05K3/4015Surface contacts, e.g. bumps using auxiliary conductive elements, e.g. pieces of metal foil, metallic spheres
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K7/00Constructional details common to different types of electric apparatus
    • H05K7/02Arrangements of circuit components or wiring on supporting structure
    • H05K7/06Arrangements of circuit components or wiring on supporting structure on insulating boards, e.g. wiring harnesses
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486Via connections through the substrate with or without pins
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    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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    • H05K1/111Pads for surface mounting, e.g. lay-out
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    • H05K3/305Affixing by adhesive
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Description

具有連接介面的電子裝置、其電路基板以及其製造方法
本發明係關於一種電子裝置、其電路基板以及其製造方法,尤指一種具有連接介面的電子裝置、其電路基板與製造方法。
隨著可攜式電子裝置、電子卡、或其他電子設備不斷推陳出新,其連接器介面規格亦不斷地迭替,如通用序列匯流排(Universal Serial Bus,簡稱「USB」),其規格從早期USB1.0至USB2.0,時至今日已發展至USB3.0,往後亦會不斷繼續發展下去。
目前常見的連接介面可參閱於2011年10月11日公開之台灣發明專利申請M413989號所揭示的一種具有端子模組之連接介面,其包含電路基板以及端子模組,其中,該連接介面的端子模組與電路基板兩者係各自獨立組裝後,再對位堆疊使端子模組的導電片與彈性端子與電路基板的電性接點連接,以組設成完整的連接介面。
由此可知,目前連接介面內的彈性端子大多設至於端子模組內,再經由端子模組與電路基板的堆疊組裝,達到彈性端子連接電性接點的目的,而非將彈性端子直接組設於電路基板,因此額外需要進行端子模組的組裝步驟等,反而增加組裝步驟與額外的成本開銷。
有鑑於上述,本發明之主要目的係在提供一種具有連接介面的電子裝置,其中電路基板上形成有開孔,因此可以讓導電元件可以直接設置於電路基板上,而無需額外組裝端子模組,簡化相關組裝流程,增加製程可靠性。
為達成上述目的,本發明之一態樣提供一種具有連接介面的電子裝置,包括:一電路基板、一半導體晶片、以及一導電元件。該電路基板具有一第一表面及一相對的第二表面,該第一表面設有一第一線路層,該第二表面設有一第二線路層,該第一線路層具有複數個電性連接墊,該第二線路層具有複數個金屬接觸墊及複數個終端墊,其中,該些終端墊分別設有一開口,該開口延伸至該第一線路層且設置一金屬層於該開口內,該金屬層形成有一開孔且連接該第一線路層與該終端墊。該半導體晶片設置於該第一表面上且具有複數個電極墊,且該半導體晶片之該些電極墊係分別電性連接至該第一電路層之該些電性連接墊。該導電元件具有一栓狀體,且該栓狀體係嵌入該開孔。
於一較佳具體實施例中,本發明之具有連接介面的電子裝置,可選擇性更包括:一接著層,該接著層設置於該導電元件之該栓狀體與該金屬層及/或該第一線路層之間,如此可讓該導電元件之該栓狀體固定於該電路基板上,避免該導電元件因為外力而脫落。除此之外,亦可選擇性更包括:一黏著膜,該黏著膜設置於該半導體晶片與該電路基板之該第一表面之間,以將該半導體晶片固著於電路基板上;若有數個半導體晶片相互堆疊,則堆疊的半導體晶片之間亦可以設置該黏著層,使該些半導體晶片之間得以相互固著。
本發明具有連接介面的電子裝置中,該導電元件可選擇性更具有一彈性結構,該彈性結構舉例可為彎折狀、弧狀、未封閉拋物線狀、雙曲線狀、不規則凸起狀、蕈狀等形狀,以因應各種需求,並增加外觀的識別性。
於一較佳具體實施例中,本發明具有連接介面的電子裝置中,設置於電路基板終端墊開口內之該金屬層,其中該開孔貫穿該金屬層,因此該開孔延伸入該第一線路層,亦即該開孔顯露該第一線路層。不過,該開孔的深度與形狀沒有特別限制,只要可讓該導電元件之該栓狀體嵌入並固定於其中即可,較佳是根據該導電元件之該栓狀體的形狀及長度,此表示該開孔也可以沒有顯露該第一線路層。此外,上述金屬接觸墊可做為金手指接觸點(golden finger)。
此外,本發明之具有連接介面的電子裝置,可選擇性更包括:一絕緣層,位於該第一線路層及/或第二線路層表面,其中,該絕緣層形成有複數接觸窗,以暴露該些電性連接墊、該些金屬接觸墊、或該些終端墊。此絕緣層主要用於絕緣保護第一線路層與該第二線路層,並針對該些電性連接墊、該些金屬接觸墊、或該些終端墊開設出接觸窗,如此可暴露出後續需進行電性連接的部分,例如需為打線接合而進行電鍍的電性連接墊,因此降低需要電鍍之面積,便可降低製造成本。於另一較佳具體實施例中,該絕緣層設於該第一線路層以及該第二線路層兩者表面,但該絕緣層之設置不局限於此,也可以僅設於該第一線路層以及該第二線路層其中一者之表面。
本發明之另一目的係在提供一種具有連接介面的電子裝置之製造方法,其中於形成有開孔之電路基板上,讓導電元件可以直接設置於電路基板上,而無需額外組裝端子模組,簡化相關組裝流程。
為達上述目的,本發明之另一態樣提供一種具有連接介面的電子裝置之製造方法,包括以下步驟:提供一電路基板,該電路基板具有一第一表面及一相對的第二表面,該第一表面設有一第一線路層,該第二表面設有一第二線路層,該第一線路層具有複數個電性連接墊,該第二線路層具有複數個金屬接觸墊及終端墊,其中,該些終端墊分別設有一開口,該開口延伸至該第一線路層且設置一金屬層於該開口內,該金屬層連接該第一線路層及該終端墊且形成有一開孔於該金屬層中;於該電路基板之該第一表面上設置一半導體晶片,該半導體晶片具有複數個電極墊,其中,該半導體晶片之該些電極墊係分別電性連接至該第一電路層之該些電性連接墊;以及於該電路基板之該開孔內設置一導電元件,其中,該導電元件具有一栓狀體,該栓狀體係嵌入該開孔。
本發明上述具有連接介面的電子裝置之製造方法中,該電路基板之該開口、該開孔與該金屬層係由一包含以下步驟之方法所形成:於該電路基板之該些終端墊分別開設一開口,其中,該開口延伸至該第一線路層;於該開口內電鍍一金屬;以及於該金屬開設一開孔,以形成一金屬層覆蓋該開口內之側壁表面。由上述可知,在電路基板上利用兩次開設孔洞的方式,於電路基板上設計出可以容置導電元件的區域,如此可以讓導電元件直接設在電路基板,而無需額外的模組。
本發明上述具有連接介面的電子裝置之製造方法可以選擇性更包括一以下步驟:於該導電元件之該栓狀體與該金屬層及/或該第一線路層之間,設置一接著層。此外,亦可選擇性更包括一以下步驟:於該半導體晶片與該電路基板之該第一表面之間,設置一黏著膜,該黏著膜亦可用於固著兩相鄰半導體晶片。另外,亦可選擇性更包括一以下步驟:於該第一線路層及/或第二線路層表面,形成一絕緣層,其中,該絕緣層形成有複數接觸窗,以暴露該些電性連接墊、該些金屬接觸墊、或該些終端墊。於一較佳具體實施例中,該絕緣層的形成步驟係於設置該半導體晶片2之前執行,但此步驟的執行順序不限於此,可以依需求而調整。
本發明之再另一目的係在提供一種供導電元件嵌設的電路基板及其製造方法,其中電路基板上利用兩次開孔技術設製出可以供導電元件嵌置的空間,因此使用此電路基板的電子裝置無需額外組裝端子模組,故可簡化相關組裝流程。
為達上述目的,本發明之另一態樣提供一種供導電元件嵌設的電路基板,包括:一第一表面;一第二表面,相對於該第一表面;一第一線路層,設於該第一表面,其中,該第一線路層具有複數個電性連接墊;以及一第二線路層,設於該第二表面,其中,該第二線路層具有複數個金屬接觸墊及終端墊,該終端墊設有一開口,該開口延伸至該第一線路層且內壁表面設置一金屬層,該金屬層連接該第一線路層及該終端墊且設有一開孔,該開孔係供該導電元件嵌設於其中。
本發明之再另一態樣提供一種供導電元件嵌設的電路基板之製造方法,包括以下步驟:提供一電路基板,該電路基板具有一第一表面及一相對的第二表面,該第一表面設有一第一線路層,該第二表面設有一第二線路層,該第一線路層具有複數個電性連接墊,該第二線路層具有複數個金屬接觸墊及終端墊;於該電路基板之該些終端墊分別開設一開口,其中,該開口延伸至該第一線路層;於該開口內電鍍一金屬;以及於該金屬’開設一開孔,以形成一金屬層覆蓋該開口之內壁表面,其中,該開孔係供該導電元件嵌設於其中。
上述的連接介面可適用各種規格,例如:週邊組件互連(peripheral component interconnection bus,PCI)匯流排、工業標準架構(industry standard architecture,ISA)匯流排或通用序列匯流排(Universal Serial Bus,以下簡稱USB)或其等效介面,較佳可為USB3.0。
由上述可知,本發明在電路基板上設計出可供導電元件置放的空間,且導電元件可以固定於該空間中,而無需額外組裝端子模組,簡化相關組裝流程。
以下係藉由特定的具體實施例說明本發明之實施方式,熟習此技藝之人士可由本說明書所揭示之內容輕易地了解本發明之其他優點與功效。本發明亦可藉由其他不同的具體實施例加以施行或應用,本說明書中的各項細節亦可基於不同觀點與應用,在不悖離本發明之精神下進行各種修飾與變更。
本發明之實施例中該等圖式均為簡化之示意圖。惟該等圖示僅顯示與本發明有關之元件,其所顯示之元件非為實際實施時之態樣,其實際實施時之元件數目、形狀等比例為一選擇性之設計,且其元件佈局型態可能更複雜。
實施例一
首先,參考圖1A至圖1D,其係本發明製造供導電元件嵌設的電路基板之流程示意圖。
如圖1A所示,提供一電路基板1。該電路基板1具有一第一表面10a及一相對的第二表面10b,該第一表面10a設有一第一線路層11,該第二表面10b設有一第二線路層12,該第一線路層11具有複數個電性連接墊13,該第二線路層12具有複數個金屬接觸墊14及終端墊16。此電路基板1的形成方式沒有特別限定,本領域通常知識者可以利用通常知識製得,舉例而言利用雙面銅箔基板經由微影蝕刻製程圖案化銅箔形成第一線路層11與第二線路層12。
接著,如圖1B所示,於該電路基板1之該些終端墊16分別開設一開口160,其中,該開口160延伸至該第一線路層11,而越過該第一線路層11表面。該開口160的開設方是沒有特別限定,例如以雷射穿孔的方式製成。
再者,如圖1C所示,於該開口160內電鍍一金屬160’,其中,可以使用阻層保護其他部份,而使用無電電鍍或有電電鍍形成金屬160’。
如圖1D所示,在於該金屬160’開設一開孔162,以形成一金屬層161覆蓋該開口160之內壁表面,其中,該開孔162係供一導電元件嵌設於其中。該開孔162之形成同樣可以使用阻層保護其他部份,而透過蝕刻形成該開孔162,或者使用雷射穿孔的方式形成。
據此,本發明之供導電元件嵌設的電路基板,包括:一第一表面10a;一第二表面10b,相對於該第一表面10a;一第一線路層11,設於該第一表面10a,其中,該第一線路層11具有複數個電性連接墊13;以及一第二線路層12,設於該第二表面10b,其中,該第二線路層12具有複數個金屬接觸墊14及終端墊16,該終端墊16設有一開口160,該開口160延伸至該第一線路層11且內壁表面設置一金屬層161,該金屬層161連接該第一線路層11及該終端墊16且設有一開孔162,該開孔162係供該導電元件嵌設於其中。
實施例二
首先,參考圖1D至圖1I,其係本發明製造具有連接介面的電子裝置之流程示意圖。
如圖1D所示,提供一電路基板1,該電路基板1具有一第一表面10a及一相對的第二表面10b,該第一表面10a設有一第一線路層11,該第二表面10b設有一第二線路層12,該第一線路層11具有複數個電性連接墊13,該第二線路層12具有複數個金屬接觸墊14及終端墊16,其中,該些終端墊16分別設有一開口160,該開口160延伸至該第一線路層11且設置一金屬層161於該開口160內,該金屬層161連接該第一線路層11及該終端墊16且形成有一開孔162於該金屬層161中。
接著,如圖1E所示,於該半導體晶片2與該電路基板1之該第一表面10a之間,設置一黏著膜32,而將一半導體晶片2設置於該電路基板1之該第一表面10a上,其中,該半導體晶片2具有複數個電極墊23。再者,如圖1F所示,利用打線技術,透過電線33使該些電極墊23分別電性連接至該第一電路層11之該些電性連接墊13。然後,如圖1G所示,利用封膠技術,使用封膠材料35如環氧樹脂等,保護該些半導體晶片2。
接著,如圖1H以及圖1I所示,經由導電元件支架5攜帶具有一栓狀體46之導電元件4,該導電元件支架5會引導該導電元件4之栓狀體46對準並嵌入該電路基板1之該開孔162,其中,該導電元件支架5可以一次攜帶複數個導電元件4,因此可以一次將數個導電元件設置於該電路基板1之該開孔162內。由此可知,導電元件4與開孔162之間的關係,如同栓與栓孔之間的關係。
據此,本發明之具有連接介面的電子裝置,包括:一電路基板1,具有一第一表面10a及一相對的第二表面10b,該第一表面10a設有一第一線路層11,該第二表面10b設有一第二線路層12,該第一線路層11具有複數個電性連接墊13,該第二線路層12具有複數個金屬接觸墊14及複數個終端墊16,其中,該些終端墊16分別設有一開口160,該開口160延伸至該第一線路層11且設置一金屬層161於該開口160內,該金屬層161形成有一開孔162且連接該第一線路層11與該終端墊16;一半導體晶片2,設置於該第一表面10a上且具有複數個電極墊23,其中,該半導體晶片2之該些電極墊23係分別電性連接至該第一電路層11之該些電性連接墊13;一導電元件4,具有一栓狀體46,該栓狀體46係嵌入該開孔162;以及一黏著膜32,設置於該半導體晶片2與該電路基板1之該第一表面10a之間。
實施例三至七
參考圖2至圖6,其分別是實施例三至實施例七之具有連接介面的電子裝置的結構示意圖。
如圖2所示,實施例三具有連接介面的電子裝置之結構大致上同實施例二所述,不同點在於該電路基板1之該開孔162設置該導電元件4前,先於該導電元件4之栓狀體46底部塗佈一接著層64,而後才將該導電元件4之栓狀體46對準並嵌入該電路基板1之該開孔162。除此之外,該電路基板1之該開孔162未延伸至該第一電路層11,亦即該開孔162沒有顯露該第一電路層11。因此,相較於實施例二之具有連接介面的電子裝置,實施例三之具有連接介面的電子裝置更包含一接著層64,設置於該導電元件4之該栓狀體46與該金屬層161之間。
如圖3所示,實施例四具有連接介面的電子裝置之結構大致上同實施例三所述,不同點在於該電路基板1之該開孔162延伸至該第一電路層11,亦即該開孔162有顯露該第一電路層11,因此接著層64係設置於該導電元件4之該栓狀體46與該第一線路層11之間。此外,半導體晶片2係設置於該第一線路層11表面而非電路基板1尚未設置線路的空白區域。
如圖4所示,實施例五具有連接介面的電子裝置之結構大致上同實施例二所述,不同點在於該電路基板1之該開孔162延伸至該第一電路層11,亦即該開孔162有顯露該第一電路層11,因此接著層64係設置於該導電元件4之該栓狀體46與該第一線路層11之間。此外,該導電元件4具有一弧狀彈性結構41,以吸收壓力。
如圖5所示,實施例五具有連接介面的電子裝置之結構大致上同實施例四所述,不同點在於接著層64係設置於該導電元件4之該栓狀體46與該第一線路層11以及該金屬層161之間。此外,該導電元件4具有一折形彈性結構41,以吸收壓力。
如圖6所示,實施例七具有連接介面的電子裝置之結構大致上同實施例三所述,不同點在於設置該半導體晶片2之前,先於該電路基板1之該第一表面10a與該第二表面10b上,形成一絕緣層17,覆蓋該第一線路層11以及該第二線路層12,且將該絕緣層17圖案化形成複數接觸窗171,以暴露該些電性連接墊13、該些金屬接觸墊14與該些終端墊16。
上述實施例僅係為了方便說明而舉例而已,本發明所主張之權利範圍自應以申請專利範圍所述為準,而非僅限於上述實施例。
1...電路基板
10a...第一表面
10b...第二表面
11...第一線路層
12...第二線路層
13...電性連接墊
14...金屬接觸墊
16...終端墊
160...開口
160’...金屬
161...金屬層
162...開孔
17...絕緣層
171...接觸窗
2...半導體晶片
23...電極墊
32...黏著膜
33...電線
35...封膠材料
4...導電元件
41...彈性結構
46...栓狀體
5...導電元件支架
64...接著層
圖1A至圖1D係本發明實施例一製造供導電元件嵌設的電路基板之流程示意圖。
圖1D至圖1I係本發明實施例二製造具有連接介面的電子裝置之流程示意圖。
圖2係本發明實施例三中具有連接介面的電子裝置之結構示意圖。
圖3係本發明實施例四中具有連接介面的電子裝置之結構示意圖。
圖4係本發明實施例五中具有連接介面的電子裝置之結構示意圖。
圖5係本發明實施例六中具有連接介面的電子裝置的結構示意圖。
圖6係本發明實施例七中具有連接介面的電子裝置的結構示意圖。
1...電路基板
10a...第一表面
10b...第二表面
12...第二線路層
13...電性連接墊
14...金屬接觸墊
16...終端墊
160...開口
161...金屬層
2...半導體晶片
23...電極墊
32...黏著膜
33...電線
35...封膠材料
4...導電元件
46...栓狀體
5...導電元件支架

Claims (15)

  1. 一種具有連接介面的電子裝置,包括:一電路基板,具有一第一表面及一相對的第二表面,該第一表面設有一第一線路層,該第二表面設有一第二線路層,該第一線路層具有複數個電性連接墊,該第二線路層具有複數個金屬接觸墊及複數個終端墊,其中,該些終端墊分別設有一開口,該開口延伸至該第一線路層且設置一金屬層於該開口內,該金屬層形成有一開孔且連接該第一線路層與該終端墊;一半導體晶片,設置於該第一表面上且具有複數個電極墊,其中,該半導體晶片之該些電極墊係分別電性連接至該第一電路層之該些電性連接墊;以及一導電元件,具有一栓狀體,該栓狀體係嵌入該開孔。
  2. 如申請專利範圍第1項所述之具有連接介面的電子裝置,更包括:一接著層,設置於該導電元件之該栓狀體與該金屬層及/或該第一線路層之間。
  3. 如申請專利範圍第2項所述之具有連接介面的電子裝置,更包括:一黏著膜,設置於該半導體晶片與該電路基板之該第一表面之間。
  4. 如申請專利範圍第3項所述之具有連接介面的電子裝置,其中,該導電元件更具有一彈性結構。
  5. 如申請專利範圍第1項至第4項中任一項所述之具有連接介面的電子裝置,其中,該開孔係貫穿該金屬層。
  6. 如申請專利範圍第1項至第4項中任一項所述之具有連接介面的電子裝置,更包括:一絕緣層,位於該第一線路層及/或第二線路層表面,其中,該絕緣層形成有複數接觸窗,以暴露該些電性連接墊、該些金屬接觸墊、或該些終端墊。
  7. 一種具有連接介面的電子裝置之製造方法,包括以下步驟:提供一電路基板,該電路基板具有一第一表面及一相對的第二表面,該第一表面設有一第一線路層,該第二表面設有一第二線路層,該第一線路層具有複數個電性連接墊,該第二線路層具有複數個金屬接觸墊及終端墊,其中,該些終端墊分別設有一開口,該開口延伸至該第一線路層且設置一金屬層於該開口內,該金屬層連接該第一線路層及該終端墊且形成有一開孔於該金屬層中;於該電路基板之該第一表面上設置一半導體晶片,該半導體晶片具有複數個電極墊,其中,該半導體晶片之該些電極墊係分別電性連接至該第一電路層之該些電性連接墊;以及於該電路基板之該開孔內設置一導電元件,其中,該導電元件具有一栓狀體,該栓狀體係嵌入該開孔。
  8. 如申請專利範圍第7項所述之具有連接介面的電子裝置之製造方法,其中,該電路基板之該開口、該開孔與該金屬層係由一包含以下步驟之方法所形成:於該電路基板之該些終端墊分別開設一開口,其中,該開口延伸至該第一線路層;於該開口內電鍍一金屬;以及於該金屬開設一開孔,以形成一金屬層覆蓋該開口內之側壁表面。
  9. 如申請專利範圍第8項所述之具有連接介面的電子裝置之製造方法,更包括一以下步驟:於該導電元件之該栓狀體與該金屬層及/或該第一線路層之間,設置一接著層。
  10. 如申請專利範圍第9項所述之具有連接介面的電子裝置之製造方法,更包括一以下步驟:於該半導體晶片與該電路基板之該第一表面之間,設置一黏著膜。
  11. 如申請專利範圍第10項所述之具有連接介面的電子裝置之製造方法,其中,該導電元件更具有一彈性結構。
  12. 如申請專利範圍第7至11項中任一項所述之具有連接介面的電子裝置之製造方法,其中,該開孔係貫穿該金屬層。
  13. 如申請專利範圍第7至11項中任一項所述之具有連接介面的電子裝置之製造方法,更包括一以下步驟:於該第一線路層及/或第二線路層表面,形成一絕緣層,其中,該絕緣層形成有複數接觸窗,以暴露該些電性連接墊、該些金屬接觸墊、或該些終端墊。
  14. 一種供導電元件嵌設的電路基板,包括:一第一表面;一第二表面,相對於該第一表面;一第一線路層,設於該第一表面,其中,該第一線路層具有複數個電性連接墊;以及一第二線路層,設於該第二表面,其中,該第二線路層具有複數個金屬接觸墊及終端墊,該終端墊設有一開口,該開口延伸至該第一線路層且內壁表面設置一金屬層,該金屬層連接該第一線路層及該終端墊且設有一開孔,該開孔係供該導電元件嵌設於其中。
  15. 一種供導電元件嵌設的電路基板之製造方法,包括以下步驟:提供一電路基板,該電路基板具有一第一表面及一相對的第二表面,該第一表面設有一第一線路層,該第二表面設有一第二線路層,該第一線路層具有複數個電性連接墊,該第二線路層具有複數個金屬接觸墊及終端墊;於該電路基板之該些終端墊分別開設一開口,其中,該開口延伸至該第一線路層;於該開口內電鍍一金屬;以及於該金屬’開設一開孔,以形成一金屬層覆蓋該開口之內壁表面,其中,該開孔係供該導電元件嵌設於其中。
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