WO2009028596A1 - 受動素子内蔵基板、製造方法、及び半導体装置 - Google Patents

受動素子内蔵基板、製造方法、及び半導体装置 Download PDF

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Publication number
WO2009028596A1
WO2009028596A1 PCT/JP2008/065380 JP2008065380W WO2009028596A1 WO 2009028596 A1 WO2009028596 A1 WO 2009028596A1 JP 2008065380 W JP2008065380 W JP 2008065380W WO 2009028596 A1 WO2009028596 A1 WO 2009028596A1
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WIPO (PCT)
Prior art keywords
substrate
passive element
connection pad
manufacturing
terminal electrode
Prior art date
Application number
PCT/JP2008/065380
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English (en)
French (fr)
Inventor
Akinobu Shibuya
Akira Ouchi
Yasuhiro Ishii
Tooru Mori
Koichi Takemura
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Nec Corporation
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Publication date
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Priority to JP2009530174A priority Critical patent/JPWO2009028596A1/ja
Publication of WO2009028596A1 publication Critical patent/WO2009028596A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G2/00—Details of capacitors not covered by a single one of groups H01G4/00-H01G11/00
    • H01G2/02—Mountings
    • H01G2/06—Mountings specially adapted for mounting on a printed-circuit support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
    • H01G4/00—Fixed capacitors; Processes of their manufacture
    • H01G4/002—Details
    • H01G4/228—Terminals
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01004—Beryllium [Be]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/0102—Calcium [Ca]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01025—Manganese [Mn]
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    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01057—Lanthanum [La]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097—Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701—Low temperature co-fired ceramic [LTCC]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/111—Pads for surface mounting, e.g. lay-out
    • H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

　破壊が起こりにくく、低コストで容易に製造可能な受動素子内蔵基板およびその製造方法を提供する。接続パッド２が形成された実装基板１と、基板７に薄膜受動素子４が形成されるとともに、接続パッド２に対向する薄膜受動素子４側の面に接続パッド２に対応した端子電極３が形成され、かつ、端子電極３が接続パッド２に接合され、基板７の厚さが１５μｍ以下である受動素子チップと、受動素子チップと実装基板１の間に充填されるとともに、受動素子チップの外周部に配された部分の上面が基板７の上面と一致するように形成された樹脂６と、基板７の上面に半導体素子又は半導体パッケージの端子に対応して形成されたＬＳＩ接続パッド９と、受動素子チップ内にて対応するＬＳＩ接続パッド９と端子電極３とを電気的に接続するように形成された貫通ビア８と、を備える。
PCT/JP2008/065380 2007-08-30 2008-08-28 受動素子内蔵基板、製造方法、及び半導体装置 WO2009028596A1 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009530174A JPWO2009028596A1 (ja) 2007-08-30 2008-08-28 受動素子内蔵基板、製造方法、及び半導体装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-224261 2007-08-30
JP2007224261 2007-08-30

Publications (1)

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WO2009028596A1 true WO2009028596A1 (ja) 2009-03-05

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Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014120519A (ja) * 2012-12-13 2014-06-30 Mitsubishi Electric Corp 半導体装置
WO2016117245A1 (ja) * 2015-01-21 2016-07-28 ソニー株式会社 インターポーザ、モジュールおよびインターポーザの製造方法
JP2019114723A (ja) * 2017-12-25 2019-07-11 凸版印刷株式会社 キャパシタ内蔵ガラス回路基板及びキャパシタ内蔵ガラス回路基板の製造方法
CN110024066A (zh) * 2017-02-21 2019-07-16 Tdk株式会社 薄膜电容器
WO2019225698A1 (ja) * 2018-05-24 2019-11-28 凸版印刷株式会社 回路基板
KR20200022792A (ko) * 2018-08-23 2020-03-04 주식회사 엘지화학 배터리 팩 기판 및 배터리 팩 기판 접속 시스템
JP2020087992A (ja) * 2018-11-16 2020-06-04 Tdk株式会社 薄膜キャパシタ及びその製造方法、並びに、薄膜キャパシタを内蔵する回路基板
JP7509035B2 (ja) 2018-05-24 2024-07-02 Ｔｏｐｐａｎホールディングス株式会社 回路基板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186238A (ja) * 2004-12-28 2006-07-13 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2007184324A (ja) * 2006-01-04 2007-07-19 Nec Corp キャパシタ、チップキャリア型キャパシタ、半導体装置および実装基板ならびにキャパシタの製造方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4240899B2 (ja) * 2001-03-26 2009-03-18 Ｎｅｃエレクトロニクス株式会社 半導体装置及び半導体装置の製造方法
JP4100936B2 (ja) * 2002-03-01 2008-06-11 Ｎｅｃエレクトロニクス株式会社 半導体装置の製造方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2006186238A (ja) * 2004-12-28 2006-07-13 Shinko Electric Ind Co Ltd 配線基板の製造方法
JP2007184324A (ja) * 2006-01-04 2007-07-19 Nec Corp キャパシタ、チップキャリア型キャパシタ、半導体装置および実装基板ならびにキャパシタの製造方法

Cited By (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014120519A (ja) * 2012-12-13 2014-06-30 Mitsubishi Electric Corp 半導体装置
WO2016117245A1 (ja) * 2015-01-21 2016-07-28 ソニー株式会社 インターポーザ、モジュールおよびインターポーザの製造方法
US20180019198A1 (en) * 2015-01-21 2018-01-18 Sony Corporation Interposer, module, and method of producing interposer
US10020250B2 (en) 2015-01-21 2018-07-10 Sony Corporation Interposer, module, and method of producing interposer
CN110024066A (zh) * 2017-02-21 2019-07-16 Tdk株式会社 薄膜电容器
JP2019114723A (ja) * 2017-12-25 2019-07-11 凸版印刷株式会社 キャパシタ内蔵ガラス回路基板及びキャパシタ内蔵ガラス回路基板の製造方法
WO2019225698A1 (ja) * 2018-05-24 2019-11-28 凸版印刷株式会社 回路基板
JPWO2019225698A1 (ja) * 2018-05-24 2021-07-01 凸版印刷株式会社 回路基板
US11303261B2 (en) 2018-05-24 2022-04-12 Toppan Printing Co., Ltd. Circuit board
JP7509035B2 (ja) 2018-05-24 2024-07-02 Ｔｏｐｐａｎホールディングス株式会社 回路基板
KR20200022792A (ko) * 2018-08-23 2020-03-04 주식회사 엘지화학 배터리 팩 기판 및 배터리 팩 기판 접속 시스템
KR102650086B1 (ko) * 2018-08-23 2024-03-20 주식회사 엘지에너지솔루션 배터리 팩 기판 및 배터리 팩 기판 접속 시스템
JP2020087992A (ja) * 2018-11-16 2020-06-04 Tdk株式会社 薄膜キャパシタ及びその製造方法、並びに、薄膜キャパシタを内蔵する回路基板
JP7225721B2 (ja) 2018-11-16 2023-02-21 Tdk株式会社 薄膜キャパシタ及びその製造方法、並びに、薄膜キャパシタを内蔵する回路基板

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