RU2008107034A - Способ и устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, и опора из микропроволоки - Google Patents
Способ и устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, и опора из микропроволоки Download PDFInfo
- Publication number
- RU2008107034A RU2008107034A RU2008107034/13A RU2008107034A RU2008107034A RU 2008107034 A RU2008107034 A RU 2008107034A RU 2008107034/13 A RU2008107034/13 A RU 2008107034/13A RU 2008107034 A RU2008107034 A RU 2008107034A RU 2008107034 A RU2008107034 A RU 2008107034A
- Authority
- RU
- Russia
- Prior art keywords
- microwires
- chemical
- microwire
- supports
- support
- Prior art date
Links
- 239000000126 substance Substances 0.000 title claims abstract 17
- 239000012530 fluid Substances 0.000 title claims abstract 10
- 238000004140 cleaning Methods 0.000 title claims abstract 4
- 238000000034 method Methods 0.000 title claims 6
- 230000004048 modification Effects 0.000 title claims 2
- 238000012986 modification Methods 0.000 title claims 2
- 238000000926 separation method Methods 0.000 title 1
- 239000011248 coating agent Substances 0.000 claims abstract 11
- 238000000576 coating method Methods 0.000 claims abstract 11
- 239000003446 ligand Substances 0.000 claims abstract 8
- 239000011521 glass Substances 0.000 claims abstract 6
- 239000000463 material Substances 0.000 claims abstract 6
- 229910052751 metal Inorganic materials 0.000 claims abstract 6
- 239000002184 metal Substances 0.000 claims abstract 6
- 239000002245 particle Substances 0.000 claims abstract 6
- 239000000919 ceramic Substances 0.000 claims abstract 3
- 230000003100 immobilizing effect Effects 0.000 claims abstract 3
- 229920000307 polymer substrate Polymers 0.000 claims abstract 3
- 108090000623 proteins and genes Proteins 0.000 claims 5
- 102000004169 proteins and genes Human genes 0.000 claims 5
- 239000003054 catalyst Substances 0.000 claims 4
- 150000001413 amino acids Chemical class 0.000 claims 3
- 239000000427 antigen Substances 0.000 claims 3
- 102000036639 antigens Human genes 0.000 claims 3
- 108091007433 antigens Proteins 0.000 claims 3
- 239000005515 coenzyme Substances 0.000 claims 3
- 150000002632 lipids Chemical class 0.000 claims 3
- 239000000203 mixture Chemical group 0.000 claims 3
- 102000039446 nucleic acids Human genes 0.000 claims 3
- 108020004707 nucleic acids Proteins 0.000 claims 3
- 150000007523 nucleic acids Chemical class 0.000 claims 3
- 239000002773 nucleotide Substances 0.000 claims 3
- 125000003729 nucleotide group Chemical group 0.000 claims 3
- 102000004196 processed proteins & peptides Human genes 0.000 claims 3
- 108090000765 processed proteins & peptides Proteins 0.000 claims 3
- 235000000346 sugar Nutrition 0.000 claims 3
- 150000008163 sugars Chemical class 0.000 claims 3
- 125000000022 2-aminoethyl group Chemical group [H]C([*])([H])C([H])([H])N([H])[H] 0.000 claims 2
- 108010035532 Collagen Proteins 0.000 claims 2
- 102000008186 Collagen Human genes 0.000 claims 2
- 108010010803 Gelatin Proteins 0.000 claims 2
- AFVFQIVMOAPDHO-UHFFFAOYSA-M Methanesulfonate Chemical group CS([O-])(=O)=O AFVFQIVMOAPDHO-UHFFFAOYSA-M 0.000 claims 2
- LOUPRKONTZGTKE-WZBLMQSHSA-N Quinine Chemical compound C([C@H]([C@H](C1)C=C)C2)C[N@@]1[C@@H]2[C@H](O)C1=CC=NC2=CC=C(OC)C=C21 LOUPRKONTZGTKE-WZBLMQSHSA-N 0.000 claims 2
- MZVQCMJNVPIDEA-UHFFFAOYSA-N [CH2]CN(CC)CC Chemical group [CH2]CN(CC)CC MZVQCMJNVPIDEA-UHFFFAOYSA-N 0.000 claims 2
- 239000003242 anti bacterial agent Substances 0.000 claims 2
- 229940088710 antibiotic agent Drugs 0.000 claims 2
- 125000000484 butyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 claims 2
- 125000002057 carboxymethyl group Chemical group [H]OC(=O)C([H])([H])[*] 0.000 claims 2
- 229920001436 collagen Polymers 0.000 claims 2
- 150000001875 compounds Chemical class 0.000 claims 2
- 125000000524 functional group Chemical group 0.000 claims 2
- 229920000159 gelatin Polymers 0.000 claims 2
- 239000008273 gelatin Substances 0.000 claims 2
- 235000019322 gelatine Nutrition 0.000 claims 2
- 235000011852 gelatine desserts Nutrition 0.000 claims 2
- 239000005556 hormone Substances 0.000 claims 2
- 229940088597 hormone Drugs 0.000 claims 2
- 125000002347 octyl group Chemical group [H]C([*])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])C([H])([H])[H] 0.000 claims 2
- 125000001997 phenyl group Chemical group [H]C1=C([H])C([H])=C(*)C([H])=C1[H] 0.000 claims 2
- 229920000642 polymer Polymers 0.000 claims 2
- 125000001453 quaternary ammonium group Chemical group 0.000 claims 2
- -1 sulfopropyl Chemical group 0.000 claims 2
- 235000001258 Cinchona calisaya Nutrition 0.000 claims 1
- PEEHTFAAVSWFBL-UHFFFAOYSA-N Maleimide Chemical compound O=C1NC(=O)C=C1 PEEHTFAAVSWFBL-UHFFFAOYSA-N 0.000 claims 1
- 150000004982 aromatic amines Chemical class 0.000 claims 1
- 150000001735 carboxylic acids Chemical class 0.000 claims 1
- LOUPRKONTZGTKE-UHFFFAOYSA-N cinchonine Natural products C1C(C(C2)C=C)CCN2C1C(O)C1=CC=NC2=CC=C(OC)C=C21 LOUPRKONTZGTKE-UHFFFAOYSA-N 0.000 claims 1
- MGNCLNQXLYJVJD-UHFFFAOYSA-N cyanuric chloride Chemical compound ClC1=NC(Cl)=NC(Cl)=N1 MGNCLNQXLYJVJD-UHFFFAOYSA-N 0.000 claims 1
- 125000002485 formyl group Chemical class [H]C(*)=O 0.000 claims 1
- 239000012535 impurity Substances 0.000 claims 1
- 230000003993 interaction Effects 0.000 claims 1
- 239000012948 isocyanate Substances 0.000 claims 1
- 150000002513 isocyanates Chemical class 0.000 claims 1
- HXITXNWTGFUOAU-UHFFFAOYSA-N phenylboronic acid Chemical compound OB(O)C1=CC=CC=C1 HXITXNWTGFUOAU-UHFFFAOYSA-N 0.000 claims 1
- 229960000948 quinine Drugs 0.000 claims 1
- 239000000725 suspension Substances 0.000 claims 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/642—Capacitive arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/232—Terminals electrically connecting two or more layers of a stacked or rolled capacitor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01G—CAPACITORS; CAPACITORS, RECTIFIERS, DETECTORS, SWITCHING DEVICES, LIGHT-SENSITIVE OR TEMPERATURE-SENSITIVE DEVICES OF THE ELECTROLYTIC TYPE
- H01G4/00—Fixed capacitors; Processes of their manufacture
- H01G4/002—Details
- H01G4/228—Terminals
- H01G4/236—Terminals leading through the housing, i.e. lead-through
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49833—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the chip support structure consisting of a plurality of insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
- H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
- H05K1/0231—Capacitors or dielectric substances
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/183—Components mounted in and supported by recessed areas of the printed circuit board
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
- H01L2224/16268—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component the bump connector connecting to a bonding area protruding from the surface of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01046—Palladium [Pd]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01068—Erbium [Er]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1515—Shape
- H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/15165—Monolayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/1517—Multilayer substrate
- H01L2924/15192—Resurf arrangement of the internal vias
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/10515—Stacked components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10431—Details of mounted components
- H05K2201/10507—Involving several components
- H05K2201/1053—Mounted components directly electrically connected to each other, i.e. not via the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10734—Ball grid array [BGA]; Bump grid array
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/04—Soldering or other types of metallurgic bonding
- H05K2203/047—Soldering with different solders, e.g. two different solders on two sides of the PCB
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
- H05K3/4602—Manufacturing multilayer circuits characterized by a special circuit board as base or central core whereon additional circuit layers are built or additional circuit boards are laminated
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Electromagnetism (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
- Ceramic Capacitors (AREA)
- Apparatus Associated With Microorganisms And Enzymes (AREA)
- Solid-Sorbent Or Filter-Aiding Compositions (AREA)
Abstract
1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия. ! 2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический, керамический, полимерный и пластиковый материал. ! 3. Устройство по п.2, в котором центральный стержень указанных опор из микропроволоки выполнен из металла, а по меньшей мере один покрывающий слой указанных опор из микропроволоки выполнен из стекла. ! 4. Устройство по п.1, которое имеет максимальный размер поперечного сечения в интервале от 0,5 см до 1,5 м, а ее длина находится в интервале от 0,5 см до 10 м. ! 5. Устройство по п.4, которое имеет максимальный размер поперечного сечения в интервале от 0,5 см до 50 см, а ее длина находится в интервале от 5 см до 1,5 м. ! 6. Устройство по п.1, в котором опоры из микропроволоки имеют максим�
Claims (24)
1. Устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством связывания химического или биологического объекта с функциональным покрытием или лигандами, находящимися на поверхности опор из микропроволоки при отсутствии воздействия магнитного поля, создаемого между опорами из микропроволоки и частицами, находящимися в текучей среде, на разделение названных частиц, которое содержит по меньшей мере одну опору из микропроволоки, закрепленную своими концами и имеющую многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя и пригодную для связывания химических или биологических объектов, при этом поверхность микропроволоки модифицирована путем присоединения лигандов или нанесением на нее функционального покрытия.
2. Устройство по п.1, в котором центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический, керамический, полимерный и пластиковый материал.
3. Устройство по п.2, в котором центральный стержень указанных опор из микропроволоки выполнен из металла, а по меньшей мере один покрывающий слой указанных опор из микропроволоки выполнен из стекла.
4. Устройство по п.1, которое имеет максимальный размер поперечного сечения в интервале от 0,5 см до 1,5 м, а ее длина находится в интервале от 0,5 см до 10 м.
5. Устройство по п.4, которое имеет максимальный размер поперечного сечения в интервале от 0,5 см до 50 см, а ее длина находится в интервале от 5 см до 1,5 м.
6. Устройство по п.1, в котором опоры из микропроволоки имеют максимальный размер поперечного сечения в интервале от 1 до 1000 мкм, а отношение их длины к максимальному размеру поперечного сечения составляет более 5.
7. Устройство по п.6, в котором опоры из микропроволоки имеют максимальный размер поперечного сечения в интервале от 1 до 100 мкм, а соотношение их длины к максимальному размеру поперечного сечения составляет более 50.
8. Устройство по п.7, в котором для опор из микропроволоки соотношение длины к максимальному размеру их поперечного сечения составляет более 500.
9. Устройство по п.8, в котором для опор из микропроволоки соотношение длины к максимальному размеру их поперечного сечения составляет более 1000.
10. Устройство по п.1, в котором любая опора из микропроволоки, взятая в отдельности, образует угол от 0 до 45° с любой другой смежной опорой из микропроволоки.
11. Устройство по п.1, в котором угол между любой опорой из микропроволоки, взятой в отдельности, и любой другой смежной опорой из микропроволоки составляет от 0 до 10°.
12. Устройство по п.1, в котором поверхность опор из микропроволоки модифицирована путем нанесения на нее функционального покрытия, выбранного из группы, включающей полимерное, белковое, желатиновое и коллагеновое покрытие.
13. Устройство по п.1, в котором лиганд выбран из группы, включающей клетки, биологические ткани, антитела, антибиотики, антигены, нуклеиновые кислоты, пептиды, гормоны, коферменты, биологические катализаторы, химические катализаторы, химические реагенты, липиды, сахара, аминокислоты, белки, нуклеотиды, соединение, содержащее функциональную группу, выбираемую из нижеследующих: диэтиламиноэтил, четвертичный аминоэтил, четвертичный аммоний, карбоксиметил, сульфопропил, метилсульфонат, бутил, октил, фенил и их смеси.
14. Устройство по п.1, в котором лиганд выбран из группы, включающей клетки, биологические ткани, антитела, антибиотики, антигены, нуклеиновые кислоты, пептиды, гормоны, коферменты, биологические катализаторы, химические катализаторы, химические реагенты, липиды, сахара, аминокислоты, белки, нуклеотиды и их смеси.
15. Устройство по п.1, в котором указанные лиганды связаны с опорой из микропроволоки через линкер, который выбран из группы, включающей полимерное покрытие, белковое покрытие, желатиновое покрытие, коллагеновое покрытие, клетки, антитела, антигены, нуклеиновые кислоты, пептиды, коферменты, липиды, сахара, аминокислоты, белки, нуклеотиды, циануровый хлорид, хинин, п-ртутьбензоат, фенилборную кислоту, и соединение, содержащее функциональную группу, выбираемую из нижеследующих: альдегид, ароматический амин, нитрен, малеимид, карбоновая кислота, изоцианат, диэтиламиноэтил, четвертичный аминоэтил, четвертичный аммоний, карбоксиметил, сульфопропил, метилсульфонат, бутил, октил, фенил и их смеси.
16. Опора из микропроволоки, закрепленная своими концами и предназначенная для использования в составе устройства по п.1, имеющая многослойную структуру, состоящую из центрального стержня и по меньшей мере одного покрывающего слоя, при этом поверхность микропроволоки модифицирована путем присоединения лигандов непосредственно или через линкер или нанесения на нее функционального покрытия, которое может ковалентно или нековалентно связываться с объектом и при этом не является полимерным.
17. Опора по п.16, в которой центральный стержень и покрывающие слои выполнены из материала, выбранного из группы, включающей стеклянный, металлический, керамический, полимерный и пластиковый материал.
18. Опора по п.16, в которой стержень выполнен из металла, а по меньшей мере один покрывающий слой выполнен из стекла.
19. Опора по п.16, которая имеет максимальный размер поперечного сечения в интервале от 1 до 1000 мкм, а соотношение ее длины к максимальному размеру поперечного сечения составляет более 5.
20. Способ очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, посредством устройства по п.1, в котором вначале осуществляют загрузку текучей среды, содержащей химические или биологические объекты, во внутренний объем канала, в который помещают вышеуказанное устройство, затем проводят связывание химических или биологических объектов с опорой вышеназванного устройства, после чего необязательно осуществляют химическую или биологическую модификацию объекта, необязательно промывают канал и сливают нежелательные компоненты и примеси текучей среды и после этого проводят элюирование полученных химических или биологических объектов, при этом, если магнитное поле оказывает влияние на указанное устройство, то его не используют для разделения восприимчивых к магнитному полю частиц, находящихся в текучей среде посредством магнитного взаимодействия между опорами из микропроволоки и указанными частицами.
21. Способ по п.20, в котором к указанному устройству подводят электрический ток.
22. Способ по п.20, в котором к указанному устройству прикладывают магнитное поле для встряхивания и/или нагревания системы.
23. Способ по п.20, в котором иммобилизуют и культивируют клетки.
24. Способ по п.23, в котором стадия загрузки текучей среды, содержащей химические или биологические объекты, во внутренний объем канала с указанным устройством включает в себя загрузку среды для культивирования и суспензии по меньшей мере одной клеточной линии, и необязательно последующую непрерывную загрузку среды для культивирования во внутренний объем канала с указанным устройством.
Applications Claiming Priority (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8949099 | 1999-03-30 | ||
JP21688799A JP3792445B2 (ja) | 1999-03-30 | 1999-07-30 | コンデンサ付属配線基板 |
EP05016861A EP1608016B1 (en) | 1999-03-30 | 2000-03-29 | Capacitor-built-in-type printed wiring substrate, printed wiring substrate, and capacitor |
EP0516861.7 | 2005-07-26 | ||
EP05106861.7 | 2005-07-26 |
Publications (2)
Publication Number | Publication Date |
---|---|
RU2008107034A true RU2008107034A (ru) | 2009-09-10 |
RU2411291C2 RU2411291C2 (ru) | 2011-02-10 |
Family
ID=26430907
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
RU2008107034/13A RU2411291C2 (ru) | 1999-03-30 | 2006-07-21 | Способ и устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, и опора из микропроволоки |
Country Status (6)
Country | Link |
---|---|
US (2) | US6952049B1 (ru) |
EP (2) | EP1041631B1 (ru) |
JP (1) | JP3792445B2 (ru) |
DE (1) | DE60035307T2 (ru) |
RU (1) | RU2411291C2 (ru) |
TW (1) | TWI224486B (ru) |
Families Citing this family (202)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6869870B2 (en) * | 1998-12-21 | 2005-03-22 | Megic Corporation | High performance system-on-chip discrete components using post passivation process |
JP4012652B2 (ja) * | 1999-07-22 | 2007-11-21 | 京セラ株式会社 | 半導体装置 |
US6400574B1 (en) * | 2000-05-11 | 2002-06-04 | Micron Technology, Inc. | Molded ball grid array |
US7247932B1 (en) * | 2000-05-19 | 2007-07-24 | Megica Corporation | Chip package with capacitor |
JP4859270B2 (ja) * | 2000-12-27 | 2012-01-25 | イビデン株式会社 | コンデンサ、多層プリント配線板および多層プリント配線板の製造方法 |
JP4753470B2 (ja) * | 2000-12-27 | 2011-08-24 | イビデン株式会社 | コンデンサ、多層プリント配線板および多層プリント配線板の製造方法 |
TW575949B (en) | 2001-02-06 | 2004-02-11 | Hitachi Ltd | Mixed integrated circuit device, its manufacturing method and electronic apparatus |
KR100411811B1 (ko) * | 2001-04-02 | 2003-12-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
US6608375B2 (en) * | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
US6657133B1 (en) * | 2001-05-15 | 2003-12-02 | Xilinx, Inc. | Ball grid array chip capacitor structure |
US20020175402A1 (en) * | 2001-05-23 | 2002-11-28 | Mccormack Mark Thomas | Structure and method of embedding components in multi-layer substrates |
KR20030012238A (ko) * | 2001-07-31 | 2003-02-12 | 주식회사 글로텍 | 수동소자 내장형 패키지 |
JP3492348B2 (ja) | 2001-12-26 | 2004-02-03 | 新光電気工業株式会社 | 半導体装置用パッケージの製造方法 |
TW503496B (en) | 2001-12-31 | 2002-09-21 | Megic Corp | Chip packaging structure and manufacturing process of the same |
TW584950B (en) | 2001-12-31 | 2004-04-21 | Megic Corp | Chip packaging structure and process thereof |
JP2003347741A (ja) * | 2002-05-30 | 2003-12-05 | Taiyo Yuden Co Ltd | 複合多層基板およびそれを用いたモジュール |
CA2464078C (en) * | 2002-08-09 | 2010-01-26 | Casio Computer Co., Ltd. | Semiconductor device and method of manufacturing the same |
JP4243117B2 (ja) * | 2002-08-27 | 2009-03-25 | 新光電気工業株式会社 | 半導体パッケージとその製造方法および半導体装置 |
TW575931B (en) * | 2002-10-07 | 2004-02-11 | Advanced Semiconductor Eng | Bridge connection type of chip package and process thereof |
TWI277992B (en) * | 2002-10-30 | 2007-04-01 | Matsushita Electric Ind Co Ltd | Sheet capacitor, IC socket using the same, and manufacturing method of sheet capacitor |
US7298046B2 (en) * | 2003-01-10 | 2007-11-20 | Kyocera America, Inc. | Semiconductor package having non-ceramic based window frame |
US20040160753A1 (en) * | 2003-01-10 | 2004-08-19 | Vrtis Joan K. | System and method for packaging electronic components |
JP4489411B2 (ja) * | 2003-01-23 | 2010-06-23 | 新光電気工業株式会社 | 電子部品実装構造の製造方法 |
JP4137659B2 (ja) | 2003-02-13 | 2008-08-20 | 新光電気工業株式会社 | 電子部品実装構造及びその製造方法 |
CN101373783B (zh) * | 2003-03-10 | 2010-06-23 | 浜松光子学株式会社 | 光电二极管阵列及其制造方法 |
US7327554B2 (en) | 2003-03-19 | 2008-02-05 | Ngk Spark Plug Co., Ltd. | Assembly of semiconductor device, interposer and substrate |
EP1636842B1 (en) * | 2003-06-03 | 2011-08-17 | Casio Computer Co., Ltd. | Stackable semiconductor device and method of manufacturing the same |
JP4377617B2 (ja) | 2003-06-20 | 2009-12-02 | 日本特殊陶業株式会社 | コンデンサ、コンデンサ付き半導体素子、コンデンサ付き配線基板、および、半導体素子とコンデンサと配線基板とを備える電子ユニット |
JP2005039217A (ja) * | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 中間基板 |
JP2005039243A (ja) | 2003-06-24 | 2005-02-10 | Ngk Spark Plug Co Ltd | 中間基板 |
US7271476B2 (en) * | 2003-08-28 | 2007-09-18 | Kyocera Corporation | Wiring substrate for mounting semiconductor components |
JP2005129899A (ja) * | 2003-08-28 | 2005-05-19 | Kyocera Corp | 配線基板および半導体装置 |
TWI221336B (en) * | 2003-08-29 | 2004-09-21 | Advanced Semiconductor Eng | Integrated circuit with embedded passive component in flip-chip connection and method for manufacturing the same |
US7112524B2 (en) * | 2003-09-29 | 2006-09-26 | Phoenix Precision Technology Corporation | Substrate for pre-soldering material and fabrication method thereof |
US7265446B2 (en) * | 2003-10-06 | 2007-09-04 | Elpida Memory, Inc. | Mounting structure for semiconductor parts and semiconductor device |
TWI278048B (en) * | 2003-11-10 | 2007-04-01 | Casio Computer Co Ltd | Semiconductor device and its manufacturing method |
US20050270748A1 (en) * | 2003-12-16 | 2005-12-08 | Phoenix Precision Technology Corporation | Substrate structure integrated with passive components |
JP4343082B2 (ja) * | 2003-12-25 | 2009-10-14 | アルプス電気株式会社 | 電子回路ユニット、及びその製造方法 |
KR100541655B1 (ko) * | 2004-01-07 | 2006-01-11 | 삼성전자주식회사 | 패키지 회로기판 및 이를 이용한 패키지 |
JP4841806B2 (ja) * | 2004-02-02 | 2011-12-21 | 新光電気工業株式会社 | キャパシタ装置とそれを備えた半導体装置、及びキャパシタ装置の製造方法 |
KR100971104B1 (ko) * | 2004-02-24 | 2010-07-20 | 이비덴 가부시키가이샤 | 반도체 탑재용 기판 |
JP3925809B2 (ja) * | 2004-03-31 | 2007-06-06 | カシオ計算機株式会社 | 半導体装置およびその製造方法 |
TWI309456B (en) * | 2004-04-27 | 2009-05-01 | Advanced Semiconductor Eng | Chip package structure and process for fabricating the same |
CN100367491C (zh) * | 2004-05-28 | 2008-02-06 | 日本特殊陶业株式会社 | 中间基板 |
CN101695216B (zh) * | 2004-06-25 | 2012-01-04 | 揖斐电株式会社 | 印刷配线板及其制造方法 |
DE102004031878B3 (de) * | 2004-07-01 | 2005-10-06 | Epcos Ag | Elektrisches Mehrschichtbauelement mit zuverlässigem Lötkontakt |
US7375288B1 (en) * | 2004-07-30 | 2008-05-20 | Intel Corp. | Apparatuses and methods for improving ball-grid-array solder joint reliability |
KR100688501B1 (ko) * | 2004-09-10 | 2007-03-02 | 삼성전자주식회사 | 미러링 구조를 갖는 스택 boc 패키지 및 이를 장착한양면 실장형 메모리 모듈 |
US7123465B2 (en) | 2004-09-24 | 2006-10-17 | Silicon Bandwidth, Inc. | Decoupling capacitor for an integrated circuit and method of manufacturing thereof |
KR100573302B1 (ko) * | 2004-10-07 | 2006-04-24 | 삼성전자주식회사 | 와이어 본딩을 이용한 패키지 스택 및 그 제조 방법 |
TWI242855B (en) * | 2004-10-13 | 2005-11-01 | Advanced Semiconductor Eng | Chip package structure, package substrate and manufacturing method thereof |
US7420282B2 (en) * | 2004-10-18 | 2008-09-02 | Sharp Kabushiki Kaisha | Connection structure for connecting semiconductor element and wiring board, and semiconductor device |
US7667323B2 (en) * | 2004-11-12 | 2010-02-23 | Analog Devices, Inc. | Spaced, bumped component structure |
US7105920B2 (en) * | 2004-11-12 | 2006-09-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Substrate design to improve chip package reliability |
TWI283050B (en) * | 2005-02-04 | 2007-06-21 | Phoenix Prec Technology Corp | Substrate structure embedded method with semiconductor chip and the method for making the same |
TWI414218B (zh) | 2005-02-09 | 2013-11-01 | Ngk Spark Plug Co | 配線基板及配線基板內建用之電容器 |
US7294904B1 (en) * | 2005-02-10 | 2007-11-13 | Xilinx, Inc. | Integrated circuit package with improved return loss |
EP1878050A1 (en) * | 2005-04-28 | 2008-01-16 | Nxp B.V. | Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip |
EP1729552A3 (en) * | 2005-06-03 | 2009-01-07 | Ngk Spark Plug Co., Ltd. | Wiring board and manufacturing method of wiring board |
US20080023821A1 (en) * | 2005-07-20 | 2008-01-31 | Shih-Ping Hsu | Substrate structure integrated with passive components |
US20080024998A1 (en) * | 2005-07-20 | 2008-01-31 | Shih-Ping Hsu | Substrate structure integrated with passive components |
TWI320219B (en) | 2005-07-22 | 2010-02-01 | Method for forming a double embossing structure | |
TW200721426A (en) * | 2005-07-25 | 2007-06-01 | Koninkl Philips Electronics Nv | Air cavity package for flip-chip |
DE102005039365B4 (de) * | 2005-08-19 | 2022-02-10 | Infineon Technologies Ag | Gate-gesteuertes Fin-Widerstandselement, welches als pinch - resistor arbeitet, zur Verwendung als ESD-Schutzelement in einem elektrischen Schaltkreis und Einrichtung zum Schutz vor elektrostatischen Entladungen in einem elektrischen Schaltkreis |
US7358615B2 (en) * | 2005-09-30 | 2008-04-15 | Intel Corporation | Microelectronic package having multiple conductive paths through an opening in a support substrate |
US7705423B2 (en) | 2005-10-21 | 2010-04-27 | Georgia Tech Research Corporation | Device having an array of embedded capacitors for power delivery and decoupling of high speed input/output circuitry of an integrated circuit |
US7718904B2 (en) * | 2005-11-15 | 2010-05-18 | Intel Corporation | Enhancing shock resistance in semiconductor packages |
JP2007201254A (ja) * | 2006-01-27 | 2007-08-09 | Ibiden Co Ltd | 半導体素子内蔵基板、半導体素子内蔵型多層回路基板 |
US7791192B1 (en) | 2006-01-27 | 2010-09-07 | Xilinx, Inc. | Circuit for and method of implementing a capacitor in an integrated circuit |
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
US20090273004A1 (en) * | 2006-07-24 | 2009-11-05 | Hung-Yi Lin | Chip package structure and method of making the same |
JP4920335B2 (ja) * | 2006-08-07 | 2012-04-18 | 新光電気工業株式会社 | キャパシタ内蔵インターポーザ及びその製造方法と電子部品装置 |
JP4783692B2 (ja) * | 2006-08-10 | 2011-09-28 | 新光電気工業株式会社 | キャパシタ内蔵基板及びその製造方法と電子部品装置 |
TWI304719B (en) * | 2006-10-25 | 2008-12-21 | Phoenix Prec Technology Corp | Circuit board structure having embedded compacitor and fabrication method thereof |
US20080116564A1 (en) * | 2006-11-21 | 2008-05-22 | Advanced Chip Engineering Technology Inc. | Wafer level package with die receiving cavity and method of the same |
KR100840790B1 (ko) * | 2006-11-29 | 2008-06-23 | 삼성전자주식회사 | 반도체 모듈 및 그의 제조 방법 |
US8178964B2 (en) * | 2007-03-30 | 2012-05-15 | Advanced Chip Engineering Technology, Inc. | Semiconductor device package with die receiving through-hole and dual build-up layers over both side-surfaces for WLP and method of the same |
US8178963B2 (en) * | 2007-01-03 | 2012-05-15 | Advanced Chip Engineering Technology Inc. | Wafer level package with die receiving through-hole and method of the same |
US7812434B2 (en) * | 2007-01-03 | 2010-10-12 | Advanced Chip Engineering Technology Inc | Wafer level package with die receiving through-hole and method of the same |
US20080197469A1 (en) * | 2007-02-21 | 2008-08-21 | Advanced Chip Engineering Technology Inc. | Multi-chips package with reduced structure and method for forming the same |
US8159828B2 (en) * | 2007-02-23 | 2012-04-17 | Alpha & Omega Semiconductor, Inc. | Low profile flip chip power module and method of making |
DE102007020475A1 (de) * | 2007-04-27 | 2008-11-06 | Häusermann GmbH | Verfahren zur Herstellung einer Leiterplatte mit einer Kavität für die Integration von Bauteilen und Leiterplatte und Anwendung |
KR100835061B1 (ko) * | 2007-06-11 | 2008-06-03 | 삼성전기주식회사 | 반도체 칩 패키지 |
TW200910541A (en) * | 2007-08-21 | 2009-03-01 | Advanced Semiconductor Eng | Package structure and manufacturing method thereof |
KR100882608B1 (ko) * | 2007-09-28 | 2009-02-12 | 삼성전기주식회사 | 캐비티 캐패시터의 제작 방법 및 캐비티 캐패시터가 내장된인쇄회로기판 |
US8035216B2 (en) * | 2008-02-22 | 2011-10-11 | Intel Corporation | Integrated circuit package and method of manufacturing same |
JP2008153699A (ja) * | 2008-03-10 | 2008-07-03 | Fujitsu Ltd | 半導体装置及びその製造方法 |
JP5005603B2 (ja) * | 2008-04-03 | 2012-08-22 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US8395902B2 (en) * | 2008-05-21 | 2013-03-12 | International Business Machines Corporation | Modular chip stack and packaging technology with voltage segmentation, regulation, integrated decoupling capacitance and cooling structure and process |
JP5367306B2 (ja) * | 2008-06-10 | 2013-12-11 | 日本特殊陶業株式会社 | セラミック部品の製造方法 |
KR20100037300A (ko) * | 2008-10-01 | 2010-04-09 | 삼성전자주식회사 | 내장형 인터포저를 갖는 반도체장치의 형성방법 |
JP5505307B2 (ja) * | 2008-10-06 | 2014-05-28 | 日本電気株式会社 | 機能素子内蔵基板及びその製造方法、並びに電子機器 |
JP2010114434A (ja) * | 2008-10-08 | 2010-05-20 | Ngk Spark Plug Co Ltd | 部品内蔵配線基板及びその製造方法 |
KR100986832B1 (ko) * | 2009-01-05 | 2010-10-12 | 삼성전기주식회사 | 전자소자 내장형 인쇄회로기판 및 그 제조방법 |
WO2010094154A1 (en) * | 2009-02-20 | 2010-08-26 | Telefonaktiebolaget L M Ericsson (Publ) | Thermal pad and method of forming the same |
JP2010238691A (ja) * | 2009-03-30 | 2010-10-21 | Fujitsu Ltd | 中継部材およびプリント基板ユニット |
JP4947388B2 (ja) * | 2009-03-31 | 2012-06-06 | Tdk株式会社 | 電子部品内蔵モジュール |
JP5372579B2 (ja) * | 2009-04-10 | 2013-12-18 | 新光電気工業株式会社 | 半導体装置及びその製造方法、並びに電子装置 |
CN101887878A (zh) * | 2009-05-14 | 2010-11-17 | 艾普特佩克股份有限公司 | 光电传感器封装 |
JP5280945B2 (ja) * | 2009-06-19 | 2013-09-04 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
JP5280309B2 (ja) * | 2009-07-17 | 2013-09-04 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
KR101079429B1 (ko) * | 2009-09-11 | 2011-11-02 | 삼성전기주식회사 | 디바이스 패키지 기판 및 그 제조 방법 |
US20110082045A1 (en) * | 2009-10-02 | 2011-04-07 | Gilbert Douglas J | Extremely low resistance materials and methods for modifying and creating same |
US8211833B2 (en) | 2010-06-04 | 2012-07-03 | Ambature, Llc | Extremely low resistance composition and methods for creating same |
JP4930566B2 (ja) * | 2009-10-02 | 2012-05-16 | 富士通株式会社 | 中継基板、プリント基板ユニット、および、中継基板の製造方法 |
WO2011041766A1 (en) * | 2009-10-02 | 2011-04-07 | Ambature L.L.C. | High temperature superconducting films and methods for modifying and creating same |
JP4930567B2 (ja) * | 2009-10-02 | 2012-05-16 | 富士通株式会社 | 中継基板、プリント基板ユニットおよび中継基板の製造方法 |
JP5352437B2 (ja) * | 2009-11-30 | 2013-11-27 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
KR101095130B1 (ko) * | 2009-12-01 | 2011-12-16 | 삼성전기주식회사 | 전자부품 내장형 인쇄회로기판 및 그 제조방법 |
US8654538B2 (en) | 2010-03-30 | 2014-02-18 | Ibiden Co., Ltd. | Wiring board and method for manufacturing the same |
US8558392B2 (en) * | 2010-05-14 | 2013-10-15 | Stats Chippac, Ltd. | Semiconductor device and method of forming interconnect structure and mounting semiconductor die in recessed encapsulant |
US8913402B1 (en) * | 2010-05-20 | 2014-12-16 | American Semiconductor, Inc. | Triple-damascene interposer |
JP5960383B2 (ja) | 2010-06-01 | 2016-08-02 | スリーエム イノベイティブ プロパティズ カンパニー | 接触子ホルダ |
US8404620B2 (en) | 2011-03-30 | 2013-03-26 | Ambature, Llc | Extremely low resistance compositions and methods for creating same |
JP2012009586A (ja) * | 2010-06-24 | 2012-01-12 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及び配線基板の製造方法 |
KR101710178B1 (ko) | 2010-06-29 | 2017-02-24 | 삼성전자 주식회사 | 임베디이드 칩 온 칩 패키지 및 이를 포함하는 패키지 온 패키지 |
US20190157218A1 (en) * | 2010-07-02 | 2019-05-23 | Schott Ag | Interposer and method for producing holes in an interposer |
DE102010025966B4 (de) | 2010-07-02 | 2012-03-08 | Schott Ag | Interposer und Verfahren zum Herstellen von Löchern in einem Interposer |
US9337116B2 (en) * | 2010-10-28 | 2016-05-10 | Stats Chippac, Ltd. | Semiconductor device and method of forming stepped interposer for stacking and electrically connecting semiconductor die |
JP5512558B2 (ja) * | 2011-01-14 | 2014-06-04 | 日本特殊陶業株式会社 | 部品内蔵配線基板の製造方法 |
JP6157048B2 (ja) * | 2011-02-01 | 2017-07-05 | スリーエム イノベイティブ プロパティズ カンパニー | Icデバイス用ソケット |
US8338294B2 (en) | 2011-03-31 | 2012-12-25 | Soitec | Methods of forming bonded semiconductor structures including two or more processed semiconductor structures carried by a common substrate, and semiconductor structures formed by such methods |
US20120248621A1 (en) * | 2011-03-31 | 2012-10-04 | S.O.I.Tec Silicon On Insulator Technologies | Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods |
JP2012256675A (ja) * | 2011-06-08 | 2012-12-27 | Shinko Electric Ind Co Ltd | 配線基板、半導体装置及びその製造方法 |
EP2745317A4 (en) | 2011-08-16 | 2015-08-12 | Intel Corp | OFFSET INTERPOSTERS FOR LARGE BOTTOM HOUSINGS AND LARGE CHIP STRUCTURES HOUSING ON HOUSING |
US8988895B2 (en) * | 2011-08-23 | 2015-03-24 | Tessera, Inc. | Interconnection elements with encased interconnects |
JP5754333B2 (ja) * | 2011-09-30 | 2015-07-29 | イビデン株式会社 | 多層プリント配線板及び多層プリント配線板の製造方法 |
US8633398B2 (en) | 2011-10-25 | 2014-01-21 | Hewlett-Packard Development Company, L.P. | Circuit board contact pads |
JP5977021B2 (ja) * | 2011-11-30 | 2016-08-24 | 日本電波工業株式会社 | 表面実装型圧電発振器 |
US20130154106A1 (en) | 2011-12-14 | 2013-06-20 | Broadcom Corporation | Stacked Packaging Using Reconstituted Wafers |
WO2013095339A1 (en) | 2011-12-19 | 2013-06-27 | Intel Corporation | Pin grid interposer |
US9691636B2 (en) * | 2012-02-02 | 2017-06-27 | Taiwan Semiconductor Manufacturing Co., Ltd. | Interposer frame and method of manufacturing the same |
US8558395B2 (en) * | 2012-02-21 | 2013-10-15 | Broadcom Corporation | Organic interface substrate having interposer with through-semiconductor vias |
US8587132B2 (en) | 2012-02-21 | 2013-11-19 | Broadcom Corporation | Semiconductor package including an organic substrate and interposer having through-semiconductor vias |
US8749072B2 (en) | 2012-02-24 | 2014-06-10 | Broadcom Corporation | Semiconductor package with integrated selectively conductive film interposer |
US9842798B2 (en) | 2012-03-23 | 2017-12-12 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a PoP device with embedded vertical interconnect units |
US9837303B2 (en) * | 2012-03-23 | 2017-12-05 | STATS ChipPAC Pte. Ltd. | Semiconductor method and device of forming a fan-out device with PWB vertical interconnect units |
US8810024B2 (en) * | 2012-03-23 | 2014-08-19 | Stats Chippac Ltd. | Semiconductor method and device of forming a fan-out PoP device with PWB vertical interconnect units |
US10049964B2 (en) | 2012-03-23 | 2018-08-14 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming a fan-out PoP device with PWB vertical interconnect units |
US20130249101A1 (en) * | 2012-03-23 | 2013-09-26 | Stats Chippac, Ltd. | Semiconductor Method of Device of Forming a Fan-Out PoP Device with PWB Vertical Interconnect Units |
JP2014038890A (ja) * | 2012-08-10 | 2014-02-27 | Ibiden Co Ltd | 配線板及び配線板の製造方法 |
TWI543307B (zh) * | 2012-09-27 | 2016-07-21 | 欣興電子股份有限公司 | 封裝載板與晶片封裝結構 |
KR101420514B1 (ko) | 2012-10-23 | 2014-07-17 | 삼성전기주식회사 | 전자부품들이 구비된 기판구조 및 전자부품들이 구비된 기판구조의 제조방법 |
US9035194B2 (en) * | 2012-10-30 | 2015-05-19 | Intel Corporation | Circuit board with integrated passive devices |
US20140167900A1 (en) | 2012-12-14 | 2014-06-19 | Gregorio R. Murtagian | Surface-mount inductor structures for forming one or more inductors with substrate traces |
US10433421B2 (en) * | 2012-12-26 | 2019-10-01 | Intel Corporation | Reduced capacitance land pad |
KR20140083514A (ko) * | 2012-12-26 | 2014-07-04 | 삼성전기주식회사 | 코어기판 및 그 제조방법, 그리고 전자부품 내장기판 및 그 제조방법 |
US9312219B2 (en) * | 2012-12-28 | 2016-04-12 | Dyi-chung Hu | Interposer and packaging substrate having the interposer |
RU2558229C2 (ru) * | 2013-04-19 | 2015-07-27 | Общество с ограниченной ответственностью "Ген Эксперт" | Набор и способ для приготовления многослойных агарозных блоков на поверхности мини-стекол для микроскопии |
JP2014236188A (ja) * | 2013-06-05 | 2014-12-15 | イビデン株式会社 | 配線板及びその製造方法 |
KR102192356B1 (ko) * | 2013-07-29 | 2020-12-18 | 삼성전자주식회사 | 반도체 패키지 |
KR101863462B1 (ko) * | 2013-08-21 | 2018-05-31 | 인텔 코포레이션 | 범프리스 빌드업 층을 위한 범프리스 다이 패키지 인터페이스 |
KR101531097B1 (ko) * | 2013-08-22 | 2015-06-23 | 삼성전기주식회사 | 인터포저 기판 및 이의 제조방법 |
JP2015049985A (ja) * | 2013-08-30 | 2015-03-16 | 富士通株式会社 | Icソケット及び接続端子 |
KR102052294B1 (ko) * | 2013-09-27 | 2019-12-04 | 인텔 코포레이션 | 수동 부품용 중첩체 기판을 구비한 다이 패키지 |
US20150255411A1 (en) * | 2014-03-05 | 2015-09-10 | Omkar G. Karhade | Die-to-die bonding and associated package configurations |
KR102333083B1 (ko) * | 2014-05-30 | 2021-12-01 | 삼성전기주식회사 | 패키지 기판 및 패키지 기판 제조 방법 |
JP6323672B2 (ja) * | 2014-07-25 | 2018-05-16 | 株式会社ソシオネクスト | 半導体装置及びその製造方法 |
JP2016029681A (ja) | 2014-07-25 | 2016-03-03 | イビデン株式会社 | 多層配線板及びその製造方法 |
JP6473595B2 (ja) * | 2014-10-10 | 2019-02-20 | イビデン株式会社 | 多層配線板及びその製造方法 |
TWI554174B (zh) * | 2014-11-04 | 2016-10-11 | 上海兆芯集成電路有限公司 | 線路基板和半導體封裝結構 |
TWI672476B (zh) * | 2014-11-25 | 2019-09-21 | 美商康寧公司 | 用於熔化批料之設備、電極組合件、及用於在熔化爐中測量電極長度的方法 |
US10306777B2 (en) * | 2014-12-15 | 2019-05-28 | Bridge Semiconductor Corporation | Wiring board with dual stiffeners and dual routing circuitries integrated together and method of making the same |
US9601435B2 (en) * | 2015-01-22 | 2017-03-21 | Qualcomm Incorporated | Semiconductor package with embedded components and method of making the same |
KR102356810B1 (ko) | 2015-01-22 | 2022-01-28 | 삼성전기주식회사 | 전자부품내장형 인쇄회로기판 및 그 제조방법 |
US9711488B2 (en) * | 2015-03-13 | 2017-07-18 | Mediatek Inc. | Semiconductor package assembly |
US9786623B2 (en) | 2015-03-17 | 2017-10-10 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming PoP semiconductor device with RDL over top package |
RU2595846C1 (ru) * | 2015-04-27 | 2016-08-27 | Общество с ограниченной ответственностью "Нанолек" | Способ производства твердой дисперсной системы с диоксидом кремния |
JP6773367B2 (ja) | 2015-06-25 | 2020-10-21 | インテル・コーポレーション | パッケージオンパッケージのため凹型導電性コンタクトを有する集積回路構造及び方法 |
KR102484173B1 (ko) * | 2015-06-25 | 2023-01-02 | 인텔 코포레이션 | 리세스를 갖는 인터포저를 포함하는 집적 회로 구조물 |
US20170086298A1 (en) * | 2015-09-23 | 2017-03-23 | Tin Poay Chuah | Substrate including structures to couple a capacitor to a packaged device and method of making same |
DE112016004812T5 (de) * | 2015-10-22 | 2018-08-16 | Asahi Glass Company, Limited | Verfahren zur Herstellung eines Verdrahtungssubstrats |
US9648729B1 (en) | 2015-11-20 | 2017-05-09 | Raytheon Company | Stress reduction interposer for ceramic no-lead surface mount electronic device |
US9806061B2 (en) * | 2016-03-31 | 2017-10-31 | Altera Corporation | Bumpless wafer level fan-out package |
US11355427B2 (en) * | 2016-07-01 | 2022-06-07 | Intel Corporation | Device, method and system for providing recessed interconnect structures of a substrate |
TWI691062B (zh) * | 2016-09-20 | 2020-04-11 | 英屬開曼群島商鳳凰先驅股份有限公司 | 基板結構及其製作方法 |
MY192082A (en) | 2016-12-27 | 2022-07-26 | Intel Corp | Interconnect core |
KR20230156179A (ko) | 2016-12-29 | 2023-11-13 | 아데이아 세미컨덕터 본딩 테크놀로지스 인코포레이티드 | 집적된 수동 컴포넌트를 구비한 접합된 구조체 |
US20180240778A1 (en) * | 2017-02-22 | 2018-08-23 | Intel Corporation | Embedded multi-die interconnect bridge with improved power delivery |
US10242964B1 (en) | 2018-01-16 | 2019-03-26 | Bridge Semiconductor Corp. | Wiring substrate for stackable semiconductor assembly and stackable semiconductor assembly using the same |
JP2019153658A (ja) * | 2018-03-02 | 2019-09-12 | 富士通株式会社 | 基板モジュール及び基板モジュールの製造方法 |
US11758654B2 (en) * | 2018-04-09 | 2023-09-12 | Bitmain Development Pte. Ltd. | Circuit substrate, chip, series circuit, circuit board and electronic device |
US11432405B2 (en) * | 2018-06-29 | 2022-08-30 | Intel Corporation | Methods for attaching large components in a package substrate for advanced power delivery |
KR102624986B1 (ko) | 2018-12-14 | 2024-01-15 | 삼성전자주식회사 | 반도체 패키지 |
KR102595865B1 (ko) * | 2019-03-04 | 2023-10-30 | 삼성전자주식회사 | 하이브리드 인터포저를 갖는 반도체 패키지 |
US11901281B2 (en) | 2019-03-11 | 2024-02-13 | Adeia Semiconductor Bonding Technologies Inc. | Bonded structures with integrated passive component |
JP7455516B2 (ja) * | 2019-03-29 | 2024-03-26 | Tdk株式会社 | 素子内蔵基板およびその製造方法 |
US20220230931A1 (en) * | 2019-05-28 | 2022-07-21 | Epicmems (Xiamen) Co., Ltd. | Chip encapsulation structure and encapsulation method |
US11710726B2 (en) | 2019-06-25 | 2023-07-25 | Microsoft Technology Licensing, Llc | Through-board power control arrangements for integrated circuit devices |
US11071213B2 (en) * | 2019-07-24 | 2021-07-20 | The Boeing Company | Methods of manufacturing a high impedance surface (HIS) enhanced by discrete passives |
US10993325B2 (en) | 2019-07-31 | 2021-04-27 | Abb Power Electronics Inc. | Interposer printed circuit boards for power modules |
US11490517B2 (en) * | 2019-07-31 | 2022-11-01 | ABB Power Electronics, Inc. | Interposer printed circuit boards for power modules |
JP2021057668A (ja) * | 2019-09-27 | 2021-04-08 | セイコーエプソン株式会社 | 振動デバイス、電子機器および移動体 |
US10984957B1 (en) | 2019-12-03 | 2021-04-20 | International Business Machines Corporation | Printed circuit board embedded capacitor |
KR102643424B1 (ko) * | 2019-12-13 | 2024-03-06 | 삼성전자주식회사 | 반도체 패키지 |
US11410934B2 (en) * | 2020-04-16 | 2022-08-09 | Advanced Semiconductor Engineering, Inc. | Substrate and semiconductor device package and method for manufacturing the same |
EP3911132A1 (en) * | 2020-05-12 | 2021-11-17 | AT & S Austria Technologie & Systemtechnik Aktiengesellschaft | Component carrier with a solid body protecting a component carrier hole from foreign material ingression |
JP2022088990A (ja) * | 2020-12-03 | 2022-06-15 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
WO2023017727A1 (ja) * | 2021-08-13 | 2023-02-16 | 株式会社村田製作所 | インターポーザ |
WO2023074251A1 (ja) * | 2021-10-28 | 2023-05-04 | 株式会社村田製作所 | トラッカモジュール |
US20230137977A1 (en) * | 2021-10-29 | 2023-05-04 | Nxp B.V. | Stacking a semiconductor die and chip-scale-package unit |
WO2023121644A1 (en) * | 2021-12-20 | 2023-06-29 | Monde Wireless Inc. | Semiconductor device for rf integrated circuit |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS51150068A (en) * | 1975-06-19 | 1976-12-23 | Citizen Watch Co Ltd | Electronic circuit block |
US4328530A (en) * | 1980-06-30 | 1982-05-04 | International Business Machines Corporation | Multiple layer, ceramic carrier for high switching speed VLSI chips |
US4453176A (en) | 1981-12-31 | 1984-06-05 | International Business Machines Corporation | LSI Chip carrier with buried repairable capacitor with low inductance leads |
US5177670A (en) * | 1991-02-08 | 1993-01-05 | Hitachi, Ltd. | Capacitor-carrying semiconductor module |
JPH04356998A (ja) | 1991-06-01 | 1992-12-10 | Ibiden Co Ltd | マルチチップモジュール |
JPH06232301A (ja) * | 1993-02-01 | 1994-08-19 | Shinko Electric Ind Co Ltd | 液冷式集積回路実装用のチップコネクタと液冷式集積回路の実装構造 |
JPH06326472A (ja) | 1993-05-14 | 1994-11-25 | Toshiba Corp | チップコンデンサ内蔵基板 |
JPH07263619A (ja) | 1994-03-17 | 1995-10-13 | Toshiba Corp | 半導体装置 |
JP3123343B2 (ja) * | 1994-05-11 | 2001-01-09 | 富士電機株式会社 | 安定化電源装置とその製造方法 |
US5600175A (en) * | 1994-07-27 | 1997-02-04 | Texas Instruments Incorporated | Apparatus and method for flat circuit assembly |
JP2701802B2 (ja) * | 1995-07-17 | 1998-01-21 | 日本電気株式会社 | ベアチップ実装用プリント基板 |
US5866952A (en) | 1995-11-30 | 1999-02-02 | Lockheed Martin Corporation | High density interconnected circuit module with a compliant layer as part of a stress-reducing molded substrate |
WO1998044564A1 (en) * | 1997-04-02 | 1998-10-08 | Tessera, Inc. | Chip with internal signal routing in external element |
JP3051700B2 (ja) | 1997-07-28 | 2000-06-12 | 京セラ株式会社 | 素子内蔵多層配線基板の製造方法 |
US6043987A (en) * | 1997-08-25 | 2000-03-28 | Compaq Computer Corporation | Printed circuit board having a well structure accommodating one or more capacitor components |
JPH1174648A (ja) | 1997-08-27 | 1999-03-16 | Kyocera Corp | 配線基板 |
JPH11317490A (ja) | 1997-10-16 | 1999-11-16 | Hitachi Ltd | 半導体素子搭載基板 |
JPH11126978A (ja) | 1997-10-24 | 1999-05-11 | Kyocera Corp | 多層配線基板 |
US6023407A (en) * | 1998-02-26 | 2000-02-08 | International Business Machines Corporation | Structure for a thin film multilayer capacitor |
US6239485B1 (en) * | 1998-11-13 | 2001-05-29 | Fujitsu Limited | Reduced cross-talk noise high density signal interposer with power and ground wrap |
US6222246B1 (en) * | 1999-01-08 | 2001-04-24 | Intel Corporation | Flip-chip having an on-chip decoupling capacitor |
US6218729B1 (en) * | 1999-03-11 | 2001-04-17 | Atmel Corporation | Apparatus and method for an integrated circuit having high Q reactive components |
-
1999
- 1999-07-30 JP JP21688799A patent/JP3792445B2/ja not_active Expired - Lifetime
-
2000
- 2000-03-29 DE DE60035307T patent/DE60035307T2/de not_active Expired - Lifetime
- 2000-03-29 US US09/538,469 patent/US6952049B1/en not_active Expired - Lifetime
- 2000-03-29 EP EP00302581A patent/EP1041631B1/en not_active Expired - Lifetime
- 2000-03-29 EP EP05016861A patent/EP1608016B1/en not_active Expired - Lifetime
- 2000-03-29 TW TW089105842A patent/TWI224486B/zh not_active IP Right Cessation
-
2005
- 2005-07-07 US US11/175,154 patent/US7239014B2/en not_active Expired - Lifetime
-
2006
- 2006-07-21 RU RU2008107034/13A patent/RU2411291C2/ru not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
US7239014B2 (en) | 2007-07-03 |
EP1041631B1 (en) | 2007-06-27 |
US20050258548A1 (en) | 2005-11-24 |
US6952049B1 (en) | 2005-10-04 |
JP2000349225A (ja) | 2000-12-15 |
DE60035307T2 (de) | 2008-03-06 |
EP1608016B1 (en) | 2011-08-31 |
TWI224486B (en) | 2004-11-21 |
EP1608016A3 (en) | 2007-10-03 |
RU2411291C2 (ru) | 2011-02-10 |
EP1608016A2 (en) | 2005-12-21 |
JP3792445B2 (ja) | 2006-07-05 |
EP1041631A3 (en) | 2003-11-26 |
DE60035307D1 (de) | 2007-08-09 |
EP1041631A2 (en) | 2000-10-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
RU2008107034A (ru) | Способ и устройство для очистки, разделения, модификации и/или иммобилизации химических или биологических объектов, находящихся в текучей среде, и опора из микропроволоки | |
US5071909A (en) | Immobilization of proteins and peptides on insoluble supports | |
US4672040A (en) | Magnetic particles for use in separations | |
JP2003527569A (ja) | マイクロアレイおよびその製造 | |
JP2013514524A (ja) | タンパク質及びペプチドを結合するための特定の溶媒、及び、それを用いた分離方法 | |
Kim et al. | Immobilization methods for affinity chromatography | |
CN106405075A (zh) | 一种免疫磁珠及其制备方法 | |
JPS61140523A (ja) | 磁気微小球、それらを製造する方法、それらの使用および生物学的粒子の単離 | |
WO2002092834A2 (en) | High capacity assay platforms | |
Özkara et al. | Separation of human-immunoglobulin-G from human plasma with L-histidine immobilized pseudo-specific bioaffinity adsorbents | |
JPH07136505A (ja) | アフィニティー分離材料 | |
EP0352917B1 (en) | The selective removal of chemical species from a fluid | |
JPS6119103A (ja) | 磁性粒子 | |
US20170137773A1 (en) | Cell strainer with functionalized mesh to separate biological components | |
EP0350252B1 (en) | The separation of elements defining a fluid flow path | |
JP3970339B2 (ja) | 細胞分離用材料 | |
JP6230997B2 (ja) | 金属/金属酸化物表面に対する分子結合のための新しい方法 | |
Wilchek et al. | yanzone | |
Wilchek et al. | NHNH | |
JPH03503172A (ja) | 流体からの抗原物質の分離 | |
JP2007057518A (ja) | 生体物質構造体及び生体物質構造体の製造方法、並びに、生体物質担持体、対象物質の精製方法、アフィニティークロマトグラフィー用容器、分離用チップ、対象物質の解析方法、対象物質の解析用分離装置、及び、センサーチップ | |
JPS637786A (ja) | 蛋白質固定用担体 | |
WO2000014541A1 (en) | Method for screening ligand affinity and tool for use in the method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | The patent is invalid due to non-payment of fees |
Effective date: 20110722 |