JP4343082B2 - 電子回路ユニット、及びその製造方法 - Google Patents
電子回路ユニット、及びその製造方法 Download PDFInfo
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- JP4343082B2 JP4343082B2 JP2004303909A JP2004303909A JP4343082B2 JP 4343082 B2 JP4343082 B2 JP 4343082B2 JP 2004303909 A JP2004303909 A JP 2004303909A JP 2004303909 A JP2004303909 A JP 2004303909A JP 4343082 B2 JP4343082 B2 JP 4343082B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
- H05K1/112—Pads for surface mounting, e.g. lay-out directly combined with via connections
- H05K1/113—Via provided in pad; Pad over filled via
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/181—Printed circuits structurally associated with non-printed electric components associated with surface mounted components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/05568—Disposition the whole external layer protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05573—Single external layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19106—Disposition of discrete passive components in a mirrored arrangement on two different side of a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/09372—Pads and lands
- H05K2201/09436—Pads or lands on permanent coating which covers the other conductors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10636—Leadless chip, e.g. chip capacitor or resistor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
- H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
- H05K2201/10621—Components characterised by their electrical contacts
- H05K2201/10674—Flip chip
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/15—Position of the PCB during processing
- H05K2203/1572—Processing both sides of a PCB by the same process; Providing a similar arrangement of components on both sides; Making interlayer connections from two sides
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Description
また、第3の解決手段として、前記回路基板を形成する前記配線基板と前記絶縁板は、低温焼成のセラミック材によって形成された構成とした。
このように、回路基板の他面側である絶縁板の露出表面には、ソルダレジスト膜が存在しない状態で、チップ部品を接続するランド部が設けられたため、半導体チップの実装工程時、ソルダレジスト膜の存在しない絶縁板が支持治具によって支持できて、回路基板に傾きが生ぜず、従って、半導体チップの実装が確実となって、実装の信頼性の高いものが得られる。
このように、回路基板の他面側である絶縁板の露出表面には、ソルダレジスト膜が存在しない状態で、チップ部品が接続されるランド部が設けられたため、半導体チップの実装工程時、ソルダレジスト膜の存在しない絶縁板が支持治具によって支持されて、支持治具の表面に対して回路基板の傾きが生ぜず、従って、半導体チップの実装が確実となって、実装の信頼性の高いものが得られる。
また、回路基板1が低温焼成のセラミック材で形成されるものにあっては、グリーンシートが加圧、焼成されて形成されるため、精度の良い回路基板1が得られる。
そして、この導電パターン6と導電部6aは、上面1aに設けられた配線パターン4と適宜箇所で接続された構成となっている。
即ち、回路基板1の下面で1bである絶縁板3の下面の露出表面は、ソルダレジスト膜が存在しない状態で、ランド部7が設けられた状態となっている。
そして、回路基板1の表面1aにおいては、半導体チップ8に設けられたバンプ9が電極5に圧着(付着)されて、半導体チップ8が回路基板1に搭載されている。
なお、ここでは図示しないが、回路基板1の表面1aには、コンデンサ等のチップ部品が配線パターン4に半田付される等して、所望の電気回路が形成され、本発明の電子回路ユニットが形成されている。
そして、バンプ9が加熱されながら装着治具12によって電極5に加圧されると、バンプ9が電極5に圧着(付着)され、しかる後、装着治具12を元の位置に復帰させる。
1a:一面(上面)
1b:他面(下面)
2:配線基板
2b:下面
3:絶縁板
4:配線パターン
5:電極
6:導電パターン
6a:導体部
7:ランド部
8:半導体チップ
8a:本体部
8b:電極部
9:バンプ
10:チップ部品
11:支持治具
12:装着治具
13:接続導体
Claims (5)
- 複数枚の絶縁シートが積層されて形成された回路基板と、この回路基板の一面側に設けられた配線パターンの電極に、バンプが付着されて接続された半導体チップと、前記回路基板の他面側に設けられたランド部に半田付けされたチップ部品とを備え、前記回路基板は、一面側に前記電極が設けられ、他面側に導電部が設けられた配線基板と、前記導電部を覆った状態で、前記配線基板の前記他面側に積層された絶縁板とで形成され、前記回路基板の前記他面側である前記絶縁板の露出表面には、ソルダレジスト膜が存在しない状態で、前記導電部に接続導体を介して接続された前記ランド部が設けられており、
前記回路基板を形成する前記配線基板と前記絶縁板は、低温焼成のセラミック材によって形成されたことを特徴とする電子回路ユニット。 - 前記配線基板の前記他面側には、導電パターンが設けられ、前記導電部が前記導電パターンの一部で形成されたことを特徴とする請求項1記載の電子回路ユニット。
- 前記配線基板の一面側に設けられた前記配線パターンの前記電極のそれぞれは、同一面積で形成されると共に、それぞれの前記電極には、前記半導体チップを接続するための前記バンプが付着されたことを特徴とする請求項1、又は2記載の電子回路ユニット。
- 一面側に設けられた配線パターンの電極、及び他面側に設けられた導電部を有する配線基板と、前記導電部を覆った状態で、前記配線基板の前記他面側に積層された絶縁板とで形成された回路基板を有すると共に、前記絶縁板の露出表面には、ソルダレジスト膜が存在しない状態で、前記導電部に接続導体を介して接続されたランド部が設けられた構成を有し、前記回路基板は、前記ランド部を有する前記絶縁板の露出表面側が支持治具上に載置され、この状態で、半導体チップに設けられたバンプが前記電極に付着された後、チップ部品が前記ランド部に半田付けされたことを特徴とする電子回路ユニットの製造方法。
- 前記回路基板を形成する前記配線基板と前記絶縁板は、低温焼成のセラミック材によって形成されたことを特徴とする請求項4記載の電子回路ユニットの製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004303909A JP4343082B2 (ja) | 2003-12-25 | 2004-10-19 | 電子回路ユニット、及びその製造方法 |
US11/020,618 US7157362B2 (en) | 2003-12-25 | 2004-12-21 | Electronic circuit unit and method of fabricating the same |
EP04030634A EP1549119A3 (en) | 2003-12-25 | 2004-12-23 | Electronic circuit unit and method of fabricating the same |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003429217 | 2003-12-25 | ||
JP2004303909A JP4343082B2 (ja) | 2003-12-25 | 2004-10-19 | 電子回路ユニット、及びその製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2005210068A JP2005210068A (ja) | 2005-08-04 |
JP4343082B2 true JP4343082B2 (ja) | 2009-10-14 |
Family
ID=34554864
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004303909A Expired - Fee Related JP4343082B2 (ja) | 2003-12-25 | 2004-10-19 | 電子回路ユニット、及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7157362B2 (ja) |
EP (1) | EP1549119A3 (ja) |
JP (1) | JP4343082B2 (ja) |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6097089A (en) * | 1998-01-28 | 2000-08-01 | Mitsubishi Gas Chemical Company, Inc. | Semiconductor plastic package, metal plate for said package, and method of producing copper-clad board for said package |
US4740414A (en) * | 1986-11-17 | 1988-04-26 | Rockwell International Corporation | Ceramic/organic multilayer interconnection board |
US4910643A (en) * | 1988-06-06 | 1990-03-20 | General Electric Company | Thick film, multi-layer, ceramic interconnected circuit board |
JPH05243330A (ja) * | 1992-02-28 | 1993-09-21 | Nippondenso Co Ltd | 多層配線基板とフリップチップicの接続構造 |
JP3081559B2 (ja) * | 1997-06-04 | 2000-08-28 | ニッコー株式会社 | ボールグリッドアレイ型半導体装置およびその製造方法ならびに電子装置 |
US6222246B1 (en) * | 1999-01-08 | 2001-04-24 | Intel Corporation | Flip-chip having an on-chip decoupling capacitor |
US20030038366A1 (en) * | 1999-03-09 | 2003-02-27 | Kabushiki Kaisha Toshiba | Three-dimensional semiconductor device having plural active semiconductor components |
JP3792445B2 (ja) * | 1999-03-30 | 2006-07-05 | 日本特殊陶業株式会社 | コンデンサ付属配線基板 |
JP2000307212A (ja) | 1999-04-20 | 2000-11-02 | Denso Corp | 配線基板及びその製造方法 |
JP3585793B2 (ja) * | 1999-11-09 | 2004-11-04 | 富士通株式会社 | 両面薄膜配線基板の製造方法 |
JP3531573B2 (ja) * | 2000-03-17 | 2004-05-31 | 株式会社村田製作所 | 積層型セラミック電子部品およびその製造方法ならびに電子装置 |
JP2002134873A (ja) * | 2000-10-24 | 2002-05-10 | Nippon Dempa Kogyo Co Ltd | チップ素子の実装方法及び表面実装用の水晶発振器 |
JP2003124429A (ja) * | 2001-10-15 | 2003-04-25 | Matsushita Electric Ind Co Ltd | モジュール部品 |
JP2003264253A (ja) * | 2002-03-12 | 2003-09-19 | Shinko Electric Ind Co Ltd | 半導体装置及びその製造方法 |
DE10228328A1 (de) * | 2002-06-25 | 2004-01-22 | Epcos Ag | Elektronisches Bauelement mit einem Mehrlagensubstrat und Herstellungsverfahren |
US20040022038A1 (en) * | 2002-07-31 | 2004-02-05 | Intel Corporation | Electronic package with back side, cavity mounted capacitors and method of fabrication therefor |
JP4105524B2 (ja) * | 2002-10-23 | 2008-06-25 | 株式会社東芝 | 半導体装置 |
-
2004
- 2004-10-19 JP JP2004303909A patent/JP4343082B2/ja not_active Expired - Fee Related
- 2004-12-21 US US11/020,618 patent/US7157362B2/en active Active
- 2004-12-23 EP EP04030634A patent/EP1549119A3/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
JP2005210068A (ja) | 2005-08-04 |
US7157362B2 (en) | 2007-01-02 |
EP1549119A3 (en) | 2007-08-08 |
US20050140008A1 (en) | 2005-06-30 |
EP1549119A2 (en) | 2005-06-29 |
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