JP4947388B2 - 電子部品内蔵モジュール - Google Patents
電子部品内蔵モジュール Download PDFInfo
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- JP4947388B2 JP4947388B2 JP2009085465A JP2009085465A JP4947388B2 JP 4947388 B2 JP4947388 B2 JP 4947388B2 JP 2009085465 A JP2009085465 A JP 2009085465A JP 2009085465 A JP2009085465 A JP 2009085465A JP 4947388 B2 JP4947388 B2 JP 4947388B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/19—Manufacturing methods of high density interconnect preforms
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73267—Layer and HDI connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9222—Sequential connecting processes
- H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
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- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Description
図1は、本発明による電子部品内蔵モジュールの第1実施形態の構造を概略的に示す正面図、平面図(上面図)、及び側面図である。電子部品内蔵モジュール1は、第1電子部品が内蔵された電子部品内蔵基板2Aと、電子部品内蔵基板2A上に第2電子部品とを有するものである。電子部品内蔵基板2Aに内蔵される第1電子部品は、ICチップ等の能動部品で構成される電子部品4であり、電子部品内蔵基板2A上に載置される第2電子部品は、コンデンサ(キャパシタ)、インダクタ、サーミスタ、抵抗等の受動部品81,82で構成される電子部品である。
図10は、本発明による電子部品内蔵モジュールの第2実施形態の構造を概略的に示す正面図、平面図(上面図)、及び側面図である。電子部品内蔵モジュール10は、電子部品内蔵基板2Bの絶縁層21に形成される開口部23Bは、側壁にテーパ(テーパ部)を有しており、電子部品内蔵基板2B上に載置される受動部品81は電子部品4の中心45を通り且つ短軸44を跨ぐように配置され、受動部品81の接合端部81aが開口部23Bの領域より外側に配置されること以外は、上記の第1実施形態の電子部品内蔵モジュール10と同様に構成されたものである。なお、受動部品81は、電子部品4の短軸44を跨ぐように配置される場合を説明するが、電子部品4の長軸43を跨ぐように配置されていてもよい。また、受動部品81を電子部品内蔵基板2B上に載置していないが、第1実施形態の電子部品内蔵モジュール1と同様に受動部品82を載置してもよい。
図11〜図17は、本発明による電子部品内蔵モジュールの第3A〜第3G実施形態の要部を概略的に示すものであり、これらの実施形態の電子部品内蔵基板2C〜2Iに形成された開口部23C〜23Iの形状を概略的に示す平面図である。電子部品内蔵モジュールは、電子部品内蔵基板2C〜2Iの絶縁層21に形成される開口部23C〜23Iの形状が上記第1実施形態の電子部品内蔵基板2Aに形成される開口部23Aの形状と異なること以外は、上述した第1実施形態の電子部品内蔵モジュール1と同様に構成されたものである。
Claims (4)
- 矩形又は略矩形状をなす第1電子部品が収容された電子部品内蔵基板上に第2電子部品が載置されてなる電子部品内蔵モジュールであって、
前記電子部品内蔵基板には、前記第1電子部品が収容される収容部が設けられており、
前記第2電子部品は、前記第1電子部品の中心を通る長軸又は短軸を跨いで前記電子部品内蔵基板に接合されており、
前記電子部品内蔵基板と前記第2電子部品との接合部は、前記収容部の領域よりも外側に配置されており、
前記収容部は、前記第2電子部品側に画成された第1開口部の面積が、前記第1開口部と対向する第2開口部の面積より小さく、且つ、側壁にテーパを有している、
電子部品内蔵モジュール。 - 前記第2電子部品は、前記第1電子部品の中心を跨いで前記電子部品内蔵基板に接合されている、
請求項1記載の電子部品内蔵モジュール。 - 前記収容部の角部は、鈍角を有する又は弧状に形成されている、
請求項1又は2記載の電子部品内蔵モジュール。 - 前記第1開口部は、前記第2電子部品の搭載領域の内側に形成される、
請求項1〜3のいずれか1項記載の電子部品内蔵モジュール。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
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JP2009085465A JP4947388B2 (ja) | 2009-03-31 | 2009-03-31 | 電子部品内蔵モジュール |
Applications Claiming Priority (1)
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JP2009085465A JP4947388B2 (ja) | 2009-03-31 | 2009-03-31 | 電子部品内蔵モジュール |
Publications (2)
Publication Number | Publication Date |
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JP2010238923A JP2010238923A (ja) | 2010-10-21 |
JP4947388B2 true JP4947388B2 (ja) | 2012-06-06 |
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JP2009085465A Active JP4947388B2 (ja) | 2009-03-31 | 2009-03-31 | 電子部品内蔵モジュール |
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Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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JPS61247058A (ja) * | 1985-04-24 | 1986-11-04 | Nec Corp | コンデンサ付チツプキヤリア |
JPH04206860A (ja) * | 1990-11-30 | 1992-07-28 | Hitachi Cable Ltd | Lsiパッケージ |
JP2823029B2 (ja) * | 1992-03-30 | 1998-11-11 | 日本電気株式会社 | マルチチップモジュール |
JPH06236939A (ja) * | 1993-02-08 | 1994-08-23 | Sumitomo Kinzoku Ceramics:Kk | Icパッケージとその配線接続方法 |
JP3117377B2 (ja) * | 1994-11-29 | 2000-12-11 | 京セラ株式会社 | 半導体装置 |
JP3710003B2 (ja) * | 1995-09-27 | 2005-10-26 | ソニー株式会社 | 実装基板及び実装基板の製造方法 |
JPH1117055A (ja) * | 1997-06-25 | 1999-01-22 | Ngk Spark Plug Co Ltd | 配線基板とその製造方法 |
JP3792445B2 (ja) * | 1999-03-30 | 2006-07-05 | 日本特殊陶業株式会社 | コンデンサ付属配線基板 |
JP2004056115A (ja) * | 2002-05-31 | 2004-02-19 | Ngk Spark Plug Co Ltd | 多層配線基板 |
JP2005158770A (ja) * | 2003-11-20 | 2005-06-16 | Matsushita Electric Ind Co Ltd | 積層基板とその製造方法及び前記積層基板を用いたモジュールの製造方法とその製造装置 |
JP2007027788A (ja) * | 2006-09-27 | 2007-02-01 | Kyocera Corp | 半導体装置 |
JP5122846B2 (ja) * | 2007-03-27 | 2013-01-16 | 日本特殊陶業株式会社 | コンデンサ内蔵配線基板 |
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