JPS61247058A - コンデンサ付チツプキヤリア - Google Patents

コンデンサ付チツプキヤリア

Info

Publication number
JPS61247058A
JPS61247058A JP60087915A JP8791585A JPS61247058A JP S61247058 A JPS61247058 A JP S61247058A JP 60087915 A JP60087915 A JP 60087915A JP 8791585 A JP8791585 A JP 8791585A JP S61247058 A JPS61247058 A JP S61247058A
Authority
JP
Japan
Prior art keywords
capacitor
chip
integrated circuit
circuit chip
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60087915A
Other languages
English (en)
Inventor
Masanobu Sano
佐野　昌宣
Yuji Iwata
岩田　勇治
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60087915A priority Critical patent/JPS61247058A/ja
Publication of JPS61247058A publication Critical patent/JPS61247058A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/4912—Layout
    • H01L2224/49171—Fan-out arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、コンデンサ付チップキャリア、特に、高度に
集積された集積回路を実装し、かつ放熱効率の良好な超
小型でリードレスのコンデンサ付チップキャリアに関す
る。
〔従来の技術〕
従来のリードレスチップキャリアは一般に高度に集積化
した集積回路チップを搭載しており、このＩＣチップ保
保護ためセラミック等の絶縁体よりなる保護カバーを取
り付けて保護している。
また、チップキャリア搭載のＩＣチップは高速論理回路
等の回路構成となっており、これらの回路動作時、集積
回路チップ供給電源系にノイズが誘発され、回路に誤動
作の恐れがある。従ってこの誤動作を防止するため、こ
の電源ノイズを極力吸収する目的でコンデンサを挿入し
て防止しているが、このコンデ／すの実装は前記リード
レスチップキャリアの近傍の電源供給配線部分に取付部
分を設け、この部分に取付けるか、あるいは、直接リー
ドレスチップキャリア上にコンデンサ取付部分を設け、
この部分に取付けを行っていた。
〔発明が解決しようとする問題点〕
上述のように従来のリードレスチップキャリアは高度に
集積化し、かつ高速度動作回路構成のＩＣチップを搭載
しであるため、外的保護に対してＩＣチップ保護カバー
を備え、電気的を源ノイズ吸収のためには、前記リード
レステップキャリアとは別個の部品であるコンデンサ並
びにこれを取付ける実装スペースを設ける必要があり、
高密度実装の妨げとなっていた。
〔問題点を解決するための手段〕
前記の問題を解決する手段として本発明は、集積回路チ
ップと、この集積回路チップの接続端子に接続された接
続電線と、この接続電線に接続される基板接続端子が印
刷配線積層基板の表面に形成され、この接続端子の電極
電位を外部へ導く手段を含む印刷配線積層基板を有し、
この基板との間に、上記集積回路チップが収容され、こ
の集積回路チップの電源ノイズを有効に吸収し、チップ
保護用となるコンデンサを印刷配線積層基板に覆せ一体
的に固着して構成される。
〔実施例〕
次に、本発明の実施例について、図面を参照して詳細に
説明する。
第１図は本発明の一実施例の要部を示す外貌図で、懐成
貴件を明示するため、カバーとなるコンデンサを開いた
ときの外観図である。
また、第２図は第１図に示す実施例の断面図である。
第１図および第２図に示されるコンデンサ付チップキャ
リアはセラミック等の絶縁体に信号配線となる導体が印
刷配線された基板を積層し、この表面に形成され信号入
出力端子となる接続端子７を備えである印刷配＃ｉ１積
層基板１と、この印刷配線積層基板１との間に論理回路
等からなり、この表面に形成され信号の入出力端子とな
るチップ接続端子５を有する集積回路チップ２と、この
集積回路チップのチップ接続端子５と前記印刷配線積層
基板１の接続端子７は電専体よりなる接続電線６により
接続され、外部より集積回路チップ２への信号の送受を
行う。
集積回路チップ２との信号の送受の経路は、前記集積回
路チップ２のテップ接続端子５４−＋接続電線６→接続
端子７４＋印刷配線積層基板１の内部配線１２を通り外
部接続端子４により外部信号の送受を行う。また、前記
印Ａｔ＋ｌＩ配線檀層基板１の表面に形成された集積回
路チップ供給電源電極の一端であるコンデンサ接続電極
９が備えてあり、この電源ノイズを有効的に吸収し、チ
ップの保護用となり、前記コンデンサ接続電極９と電気
的に接続するだめのコンデンサ電極８を有するコンデン
サ３はコンデンサ接着剤１０により固着接続される。
これにより、電源ノイズの吸収並びにチップを保護する
。
〔発明の効果〕
本発明のコンデンサ付チップキャアはチップキャリアの
集ｆＲＩＰ回路チップ保護用カバーをコンデンサとし、
チップキャリアと一体的に固着することにより、集積回
路チップの電源とグランド間に発生するノイズを有効に
吸収し、かつ集積回路チップの保論が行え、また、プリ
ント配線板あるいはボードにおける配線領域の拡大と、
配線ならびに搭載部品の高密度化を実現できるという効
果がある０
【図面の簡単な説明】
第１図は本発明の一実施例を示す外観図、第２図は第１
図に示す実施例の断面図である。 ■・・・・・・印刷配線積層基板、２・・・・・・集積
回路チップ、３・・・・・・コンデンサ、４・・・・・
・外部接続端子、５・・・・・・チップ接続端子、６・
・・・・・接続電線、７・・・・・・接続端子、８・・
・・・・コンデンサ電極、９・・・・・・コンデンサ接
続電極、１０・・・・・・コンデンサ接着剤、１１・・
・・・・外装樹脂、１２・−・・・・内部配線。 −−−〆゛

Claims (1)

  1. 【特許請求の範囲】 集積回路チップと、この集積回路チップのチップ接続端
    子に接続された接続電線とこの接続電線と接続される基
    板接続端子が印刷配線積層基板の表面に形成され、 前記接続端子の電極電位を外部へ導く手段を含む印刷配
    線積層基板を有し、この印刷配線積層基板との間に形成
    される空間に上記集積回路チップが収容され、 この集積回路チップの電源回路ノイズを有効に吸収し、
    チップ保護用となるコンデンサを前記印刷配線積層基板
    に覆せ一体的に固着してなることを特徴とするコンデン
    サ付チップキャリア。
JP60087915A 1985-04-24 1985-04-24 コンデンサ付チツプキヤリア Pending JPS61247058A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60087915A JPS61247058A (ja) 1985-04-24 1985-04-24 コンデンサ付チツプキヤリア

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60087915A JPS61247058A (ja) 1985-04-24 1985-04-24 コンデンサ付チツプキヤリア

Publications (1)

Publication Number Publication Date
JPS61247058A true JPS61247058A (ja) 1986-11-04

Family

ID=13928214

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60087915A Pending JPS61247058A (ja) 1985-04-24 1985-04-24 コンデンサ付チツプキヤリア

Country Status (1)

Country Link
JP (1) JPS61247058A (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818106A (en) * 1994-11-29 1998-10-06 Kyocera Corporation Semiconductor device having a capacitor formed on a surface of a closure
US5831810A (en) * 1996-08-21 1998-11-03 International Business Machines Corporation Electronic component package with decoupling capacitors completely within die receiving cavity of substrate
JP2010238923A (ja) * 2009-03-31 2010-10-21 Tdk Corp 電子部品内蔵モジュール

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5818106A (en) * 1994-11-29 1998-10-06 Kyocera Corporation Semiconductor device having a capacitor formed on a surface of a closure
US5831810A (en) * 1996-08-21 1998-11-03 International Business Machines Corporation Electronic component package with decoupling capacitors completely within die receiving cavity of substrate
JP2010238923A (ja) * 2009-03-31 2010-10-21 Tdk Corp 電子部品内蔵モジュール

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