|
KR100568075B1
(ko)
*
|
1996-11-26 |
2006-10-24 |
가부시끼가이샤 히다치 세이사꾸쇼 |
반도체집적회로장치
|
|
JP3732914B2
(ja)
*
|
1997-02-28 |
2006-01-11 |
株式会社ルネサステクノロジ |
半導体装置
|
|
US6166584A
(en)
*
|
1997-06-20 |
2000-12-26 |
Intel Corporation |
Forward biased MOS circuits
|
|
US6411156B1
(en)
*
|
1997-06-20 |
2002-06-25 |
Intel Corporation |
Employing transistor body bias in controlling chip parameters
|
|
JP4109340B2
(ja)
*
|
1997-12-26 |
2008-07-02 |
株式会社ルネサステクノロジ |
半導体集積回路装置
|
|
US6191615B1
(en)
*
|
1998-03-30 |
2001-02-20 |
Nec Corporation |
Logic circuit having reduced power consumption
|
|
US6252452B1
(en)
*
|
1998-08-25 |
2001-06-26 |
Kabushiki Kaisha Toshiba |
Semiconductor device
|
|
JP4071378B2
(ja)
*
|
1998-11-17 |
2008-04-02 |
株式会社ルネサステクノロジ |
半導体回路装置
|
|
JP3187019B2
(ja)
|
1998-12-10 |
2001-07-11 |
沖電気工業株式会社 |
半導体集積回路及びその試験方法
|
|
US6272666B1
(en)
|
1998-12-30 |
2001-08-07 |
Intel Corporation |
Transistor group mismatch detection and reduction
|
|
US6484265B2
(en)
|
1998-12-30 |
2002-11-19 |
Intel Corporation |
Software control of transistor body bias in controlling chip parameters
|
|
CA2263061C
(en)
*
|
1999-02-26 |
2011-01-25 |
Ki-Jun Lee |
Dual control analog delay element
|
|
JP3892612B2
(ja)
*
|
1999-04-09 |
2007-03-14 |
株式会社東芝 |
半導体装置
|
|
JP3502328B2
(ja)
|
1999-05-06 |
2004-03-02 |
松下電器産業株式会社 |
半導体集積回路
|
|
CN1173405C
(zh)
*
|
1999-05-06 |
2004-10-27 |
松下电器产业株式会社 |
互补型金属氧化物半导体的半导体集成电路
|
|
JP3928837B2
(ja)
*
|
1999-09-13 |
2007-06-13 |
株式会社ルネサステクノロジ |
半導体集積回路装置
|
|
JP3439412B2
(ja)
|
1999-09-17 |
2003-08-25 |
Necエレクトロニクス株式会社 |
集積回路装置、電子回路機器、回路製造方法
|
|
DE19950543C1
(de)
*
|
1999-10-20 |
2000-11-23 |
Infineon Technologies Ag |
Integrierte Schaltung mit Regelung der Einsatzspannungen ihrer Transistoren
|
|
US6452858B1
(en)
|
1999-11-05 |
2002-09-17 |
Hitachi, Ltd. |
Semiconductor device
|
|
JP2001156619A
(ja)
*
|
1999-11-25 |
2001-06-08 |
Texas Instr Japan Ltd |
半導体回路
|
|
US6515534B2
(en)
*
|
1999-12-30 |
2003-02-04 |
Intel Corporation |
Enhanced conductivity body biased PMOS driver
|
|
DE10007176A1
(de)
|
2000-02-17 |
2001-08-30 |
Infineon Technologies Ag |
Dekodiervorrichtung
|
|
JP3874234B2
(ja)
*
|
2000-04-06 |
2007-01-31 |
株式会社ルネサステクノロジ |
半導体集積回路装置
|
|
JP2001339045A
(ja)
*
|
2000-05-25 |
2001-12-07 |
Hitachi Ltd |
半導体集積回路装置
|
|
TW501278B
(en)
*
|
2000-06-12 |
2002-09-01 |
Intel Corp |
Apparatus and circuit having reduced leakage current and method therefor
|
|
JP4420156B2
(ja)
*
|
2000-06-14 |
2010-02-24 |
日本電気株式会社 |
半導体装置
|
|
JP2002033451A
(ja)
*
|
2000-07-14 |
2002-01-31 |
Fujitsu Ltd |
半導体集積回路
|
|
US6433573B1
(en)
*
|
2000-08-07 |
2002-08-13 |
Koninklijke Philips Electronics N.V. |
Method and apparatus for measuring parameters of an electronic device
|
|
US6501676B1
(en)
*
|
2000-09-12 |
2002-12-31 |
The Board Of Regents Of The University Of Nebraska |
Accessing of two-terminal electronic quantum dot comprising static memory
|
|
JP2002093195A
(ja)
*
|
2000-09-18 |
2002-03-29 |
Mitsubishi Electric Corp |
半導体記憶装置および半導体記憶装置のテスト方法
|
|
JP4038351B2
(ja)
*
|
2001-05-29 |
2008-01-23 |
株式会社東芝 |
半導体記憶装置
|
|
JP2003059273A
(ja)
|
2001-08-09 |
2003-02-28 |
Hitachi Ltd |
半導体記憶装置
|
|
JP2003132683A
(ja)
*
|
2001-10-23 |
2003-05-09 |
Hitachi Ltd |
半導体装置
|
|
JP2003188351A
(ja)
*
|
2001-12-17 |
2003-07-04 |
Hitachi Ltd |
半導体集積回路
|
|
WO2003094235A1
(fr)
*
|
2002-04-30 |
2003-11-13 |
Renesas Technology Corp. |
Dispositif de circuit integre a semiconducteur
|
|
US7432136B2
(en)
*
|
2002-05-06 |
2008-10-07 |
Advanced Micro Devices, Inc. |
Transistors with controllable threshold voltages, and various methods of making and operating same
|
|
US7129142B2
(en)
*
|
2002-06-11 |
2006-10-31 |
Advanced Micro Devices, Inc. |
Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same
|
|
US6738305B1
(en)
|
2002-07-25 |
2004-05-18 |
Taiwan Semiconductor Manufacturing Company |
Standby mode circuit design for SRAM standby power reduction
|
|
JP2004165649A
(ja)
*
|
2002-10-21 |
2004-06-10 |
Matsushita Electric Ind Co Ltd |
半導体集積回路装置
|
|
JP4290457B2
(ja)
*
|
2003-03-31 |
2009-07-08 |
株式会社ルネサステクノロジ |
半導体記憶装置
|
|
JP4321678B2
(ja)
*
|
2003-08-20 |
2009-08-26 |
パナソニック株式会社 |
半導体集積回路
|
|
DE10342997A1
(de)
*
|
2003-09-17 |
2005-04-28 |
Infineon Technologies Ag |
Elektronischer Schaltkreis, Schaltkreis-Testanordnung und Verfahren zum Ermitteln der Funktionsfähigkeit eines elektronischen Schaltkreises
|
|
US7236044B2
(en)
*
|
2003-10-14 |
2007-06-26 |
The Board Of Trustees Of The Leland Stanford Junior University |
Apparatus and method for adjusting the substrate impedance of a MOS transistor
|
|
JP3944855B2
(ja)
*
|
2003-11-07 |
2007-07-18 |
株式会社リコー |
キャパシタ充電用半導体装置
|
|
JP4637512B2
(ja)
*
|
2003-11-13 |
2011-02-23 |
ルネサスエレクトロニクス株式会社 |
半導体集積回路装置
|
|
JP2005164357A
(ja)
*
|
2003-12-02 |
2005-06-23 |
Seiko Instruments Inc |
電圧検出回路
|
|
US7020041B2
(en)
*
|
2003-12-18 |
2006-03-28 |
Intel Corporation |
Method and apparatus to clamp SRAM supply voltage
|
|
US7227383B2
(en)
*
|
2004-02-19 |
2007-06-05 |
Mosaid Delaware, Inc. |
Low leakage and data retention circuitry
|
|
US7092309B2
(en)
*
|
2004-04-30 |
2006-08-15 |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Standby mode SRAM design for power reduction
|
|
US7382178B2
(en)
*
|
2004-07-09 |
2008-06-03 |
Mosaid Technologies Corporation |
Systems and methods for minimizing static leakage of an integrated circuit
|
|
JP2006040495A
(ja)
*
|
2004-07-30 |
2006-02-09 |
Renesas Technology Corp |
半導体集積回路装置
|
|
US7206249B2
(en)
*
|
2004-09-30 |
2007-04-17 |
Intel Corporation |
SRAM cell power reduction circuit
|
|
DE102004058612A1
(de)
*
|
2004-12-04 |
2006-06-08 |
Infineon Technologies Ag |
Spannungsversorgungsschaltung, insbesondere für eine DRAM-Speicherschaltung sowie ein Verfahren zum Steuern einer Versorgungsquelle
|
|
US7215147B1
(en)
*
|
2004-12-10 |
2007-05-08 |
National Semiconductor Corporation |
System and method for providing power managed CML transmitters for use with main and auxiliary power sources
|
|
US20060133135A1
(en)
*
|
2004-12-20 |
2006-06-22 |
Lachman Jonathan E |
Reducing power in SRAMs while maintaining cell stability
|
|
US7659746B2
(en)
*
|
2005-02-14 |
2010-02-09 |
Qualcomm, Incorporated |
Distributed supply current switch circuits for enabling individual power domains
|
|
JP2006270027A
(ja)
|
2005-02-24 |
2006-10-05 |
Matsushita Electric Ind Co Ltd |
半導体装置および相補形mis論理回路
|
|
JP4667928B2
(ja)
*
|
2005-03-31 |
2011-04-13 |
富士通セミコンダクター株式会社 |
レベルコンバート回路および半導体装置
|
|
US7615841B2
(en)
*
|
2005-05-02 |
2009-11-10 |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Design structure for coupling noise prevention
|
|
US7508256B2
(en)
*
|
2005-05-13 |
2009-03-24 |
Mosaid Technologies Corporation |
Integrated circuit with signal bus formed by cell abutment of logic cells
|
|
US7355905B2
(en)
|
2005-07-01 |
2008-04-08 |
P.A. Semi, Inc. |
Integrated circuit with separate supply voltage for memory that is different from logic circuit supply voltage
|
|
JP4967264B2
(ja)
*
|
2005-07-11 |
2012-07-04 |
株式会社日立製作所 |
半導体装置
|
|
US7418683B1
(en)
*
|
2005-09-21 |
2008-08-26 |
Cadence Design Systems, Inc |
Constraint assistant for circuit design
|
|
JP2007103863A
(ja)
*
|
2005-10-07 |
2007-04-19 |
Nec Electronics Corp |
半導体デバイス
|
|
US7355437B2
(en)
*
|
2006-03-06 |
2008-04-08 |
Altera Corporation |
Latch-up prevention circuitry for integrated circuits with transistor body biasing
|
|
US7567133B2
(en)
*
|
2006-04-06 |
2009-07-28 |
Mosaid Technologies Corporation |
Phase-locked loop filter capacitance with a drag current
|
|
WO2008014825A1
(en)
*
|
2006-08-03 |
2008-02-07 |
Agilent Technologies, Inc. |
Channelless fluidic sample transport medium
|
|
KR101258530B1
(ko)
|
2006-09-01 |
2013-04-30 |
삼성전자주식회사 |
딥스탑 모드를 구현하기 위한 시스템 온 칩 및 그 방법
|
|
WO2008047416A1
(fr)
*
|
2006-10-18 |
2008-04-24 |
Spansion Llc |
Circuit de détection de tension
|
|
JP2008263088A
(ja)
*
|
2007-04-12 |
2008-10-30 |
Rohm Co Ltd |
半導体装置
|
|
US7675317B2
(en)
*
|
2007-09-14 |
2010-03-09 |
Altera Corporation |
Integrated circuits with adjustable body bias and power supply circuitry
|
|
US20090160531A1
(en)
*
|
2007-12-20 |
2009-06-25 |
Ati Technologies Ulc |
Multi-threshold voltage-biased circuits
|
|
CN101682325B
(zh)
*
|
2008-02-27 |
2013-06-05 |
松下电器产业株式会社 |
半导体集成电路以及包括该半导体集成电路的各种装置
|
|
US8462960B2
(en)
*
|
2008-05-28 |
2013-06-11 |
Mediatek Inc. |
Signal processing system having a plurality of high-voltage functional blocks integrated into interface module and method thereof
|
|
US7812662B2
(en)
*
|
2008-10-07 |
2010-10-12 |
Via Technologies, Inc. |
System and method for adjusting supply voltage levels to reduce sub-threshold leakage
|
|
JP5304505B2
(ja)
*
|
2009-07-21 |
2013-10-02 |
富士通セミコンダクター株式会社 |
半導体集積回路
|
|
JP4791581B2
(ja)
*
|
2009-08-01 |
2011-10-12 |
株式会社半導体理工学研究センター |
サブスレッショルドディジタルcmos回路のための電源電圧制御回路及び制御方法
|
|
KR101699033B1
(ko)
*
|
2009-11-30 |
2017-01-24 |
에스케이하이닉스 주식회사 |
출력 드라이버
|
|
US20100321094A1
(en)
*
|
2010-08-29 |
2010-12-23 |
Hao Luo |
Method and circuit implementation for reducing the parameter fluctuations in integrated circuits
|
|
US9013228B2
(en)
|
2011-06-20 |
2015-04-21 |
Stmicroelectronics Sa |
Method for providing a system on chip with power and body bias voltages
|
|
FR2976723A1
(fr)
*
|
2011-06-20 |
2012-12-21 |
St Microelectronics Sa |
Procede d'alimentation et de polarisation de caissons d'un systeme integre sur puce
|
|
WO2013018217A1
(ja)
*
|
2011-08-03 |
2013-02-07 |
富士通株式会社 |
半導体集積回路及びラッチ回路の駆動方法
|
|
US9287253B2
(en)
|
2011-11-04 |
2016-03-15 |
Synopsys, Inc. |
Method and apparatus for floating or applying voltage to a well of an integrated circuit
|
|
US8773893B2
(en)
*
|
2012-04-15 |
2014-07-08 |
Nanya Technology Corp. |
System for powering up voltage domains after exiting powerdown event
|
|
US8856712B2
(en)
*
|
2012-08-13 |
2014-10-07 |
Sandisk Technologies Inc. |
Optimized flip-flop device with standard and high threshold voltage MOS devices
|
|
US9112495B1
(en)
*
|
2013-03-15 |
2015-08-18 |
Mie Fujitsu Semiconductor Limited |
Integrated circuit device body bias circuits and methods
|
|
KR102095856B1
(ko)
*
|
2013-04-15 |
2020-04-01 |
삼성전자주식회사 |
반도체 메모리 장치 및 그것의 바디 바이어스 방법
|
|
FR3009149A1
(fr)
*
|
2013-07-24 |
2015-01-30 |
St Microelectronics Sa |
Element a retard variable
|
|
EP2849218B1
(en)
*
|
2013-09-16 |
2016-02-03 |
ST-Ericsson SA |
Integrated circuit of CMOS type comprising first and second circuit parts
|
|
US9110484B2
(en)
*
|
2013-09-24 |
2015-08-18 |
Freescale Semiconductor, Inc. |
Temperature dependent biasing for leakage power reduction
|
|
JP2015122027A
(ja)
*
|
2013-12-25 |
2015-07-02 |
株式会社東芝 |
半導体システム、半導体部品、及び電源チップ
|
|
US9429610B2
(en)
|
2014-01-16 |
2016-08-30 |
Qualcomm Incorporated |
Voltage dependent die RC modeling for system level power distribution networks
|
|
US9710006B2
(en)
*
|
2014-07-25 |
2017-07-18 |
Mie Fujitsu Semiconductor Limited |
Power up body bias circuits and methods
|
|
US9762242B2
(en)
*
|
2014-12-24 |
2017-09-12 |
Texas Instuments Incorporated |
Multi-supply output circuit
|
|
US9768773B2
(en)
*
|
2016-01-27 |
2017-09-19 |
Peregrine Semiconductor Corporation |
Dual voltage supply
|
|
JP6719236B2
(ja)
*
|
2016-03-18 |
2020-07-08 |
エイブリック株式会社 |
発振回路、昇圧回路及び半導体装置
|
|
JP6946531B2
(ja)
*
|
2016-09-29 |
2021-10-06 |
ルネサスエレクトロニクス株式会社 |
半導体装置
|
|
JP6767225B2
(ja)
*
|
2016-09-29 |
2020-10-14 |
ルネサスエレクトロニクス株式会社 |
半導体装置
|
|
US10469076B2
(en)
*
|
2016-11-22 |
2019-11-05 |
The Curators Of The University Of Missouri |
Power gating circuit utilizing double-gate fully depleted silicon-on-insulator transistor
|
|
EP3343763B1
(en)
*
|
2016-12-29 |
2019-11-06 |
GN Hearing A/S |
Output driver comprising mos switches with adjustable back gate biasing
|
|
US10079597B1
(en)
*
|
2017-03-15 |
2018-09-18 |
Globalfoundries Inc. |
Circuit tuning scheme for FDSOI
|
|
US11262780B1
(en)
*
|
2020-11-12 |
2022-03-01 |
Micron Technology, Inc. |
Back-bias optimization
|
|
US12407350B2
(en)
*
|
2023-07-11 |
2025-09-02 |
Globalfoundries U.S. Inc. |
Voltage level shifter with programmable high supply voltage and high supply voltage-dependent variable low supply voltage
|
|
US12348133B2
(en)
|
2023-07-11 |
2025-07-01 |
Globalfoundries U.S. Inc. |
Multi-stage charge pump circuit including voltage level shifter for clock signal generation
|