KR100574301B1 - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR100574301B1
KR100574301B1 KR1019980005898A KR19980005898A KR100574301B1 KR 100574301 B1 KR100574301 B1 KR 100574301B1 KR 1019980005898 A KR1019980005898 A KR 1019980005898A KR 19980005898 A KR19980005898 A KR 19980005898A KR 100574301 B1 KR100574301 B1 KR 100574301B1
Authority
KR
South Korea
Prior art keywords
voltage
circuit
threshold
transistor
well
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
KR1019980005898A
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English (en)
Korean (ko)
Other versions
KR19980071678A (ko
Inventor
기요오 이토
히로유키 미즈노
Original Assignee
가부시끼가이샤 히다치 세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 가부시끼가이샤 히다치 세이사꾸쇼 filed Critical 가부시끼가이샤 히다치 세이사꾸쇼
Publication of KR19980071678A publication Critical patent/KR19980071678A/ko
Application granted granted Critical
Publication of KR100574301B1 publication Critical patent/KR100574301B1/ko
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G11C5/146—Substrate bias generators
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0013—Arrangements for reducing power consumption in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0008—Arrangements for reducing power consumption
    • H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00315—Modifications for increasing the reliability for protection in field-effect transistor circuits
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02—Regulating voltage or current
    • G05F3/08—Regulating voltage or current wherein the variable is DC
    • G05F3/10—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20—Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/205—Substrate bias-voltage generators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of DC power input into DC power output
    • H02M3/02—Conversion of DC power input into DC power output without intermediate conversion into AC
    • H02M3/04—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters
    • H02M3/06—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of DC power input into DC power output without intermediate conversion into AC by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Power Engineering (AREA)
  • Dram (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)
KR1019980005898A 1997-02-28 1998-02-25 반도체장치 Expired - Fee Related KR100574301B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP97-045235 1997-02-28
JP04523597A JP3732914B2 (ja) 1997-02-28 1997-02-28 半導体装置

Publications (2)

Publication Number Publication Date
KR19980071678A KR19980071678A (ko) 1998-10-26
KR100574301B1 true KR100574301B1 (ko) 2006-07-25

Family

ID=12713605

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019980005898A Expired - Fee Related KR100574301B1 (ko) 1997-02-28 1998-02-25 반도체장치

Country Status (4)

Country Link
US (6) US6046627A (enExample)
JP (1) JP3732914B2 (enExample)
KR (1) KR100574301B1 (enExample)
TW (1) TW388120B (enExample)

Cited By (3)

* Cited by examiner, † Cited by third party
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KR100714300B1 (ko) * 2000-04-06 2007-05-04 가부시키가이샤 히타치세이사쿠쇼 반도체장치
KR101258530B1 (ko) 2006-09-01 2013-04-30 삼성전자주식회사 딥스탑 모드를 구현하기 위한 시스템 온 칩 및 그 방법
KR20140123829A (ko) * 2013-04-15 2014-10-23 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법

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KR100714300B1 (ko) * 2000-04-06 2007-05-04 가부시키가이샤 히타치세이사쿠쇼 반도체장치
KR101258530B1 (ko) 2006-09-01 2013-04-30 삼성전자주식회사 딥스탑 모드를 구현하기 위한 시스템 온 칩 및 그 방법
KR20140123829A (ko) * 2013-04-15 2014-10-23 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법
KR102095856B1 (ko) * 2013-04-15 2020-04-01 삼성전자주식회사 반도체 메모리 장치 및 그것의 바디 바이어스 방법

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KR19980071678A (ko) 1998-10-26
US7772917B2 (en) 2010-08-10
US20030155962A1 (en) 2003-08-21
US20070109034A1 (en) 2007-05-17
US7560975B2 (en) 2009-07-14
US20030016075A1 (en) 2003-01-23
US6545525B2 (en) 2003-04-08
TW388120B (en) 2000-04-21
US7176745B2 (en) 2007-02-13
JP3732914B2 (ja) 2006-01-11
JPH10242839A (ja) 1998-09-11
US20040217802A1 (en) 2004-11-04
US20090179693A1 (en) 2009-07-16
US6046627A (en) 2000-04-04

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