JP4967264B2 - 半導体装置 - Google Patents
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- JP4967264B2 JP4967264B2 JP2005201054A JP2005201054A JP4967264B2 JP 4967264 B2 JP4967264 B2 JP 4967264B2 JP 2005201054 A JP2005201054 A JP 2005201054A JP 2005201054 A JP2005201054 A JP 2005201054A JP 4967264 B2 JP4967264 B2 JP 4967264B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/66772—Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
- H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0021—Modifications of threshold
- H03K19/0027—Modifications of threshold in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00369—Modifications for compensating variations of temperature, supply voltage or other physical parameters
- H03K19/00384—Modifications for compensating variations of temperature, supply voltage or other physical parameters in field effect transistor circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B20/00—Energy efficient lighting technologies, e.g. halogen lamps or gas discharge lamps
- Y02B20/30—Semiconductor lamps, e.g. solid state lamps [SSL] light emitting diodes [LED] or organic LED [OLED]
Description
(2)従来回路でも、これまでの提案はSRAMセルへの応用に限られていた。ゲートとウエルを直接接続した該回路の動作条件や低電圧化の限界などを、FD−SOI MOSTのデバイス特性と関連付けて明確にされていなかったためである。
入力(IN)波形が0からVDDに変化していく過程では、MOSTのVTはコンバータを介してダイナミックに変わる。今、NMOST(MN1)を例にとろう。入力電圧(VIN)のウエル電圧(Vwell)への変換率をk1、ウエル電圧の変化に対するVTの変化率をk2、また入力電圧が0VでのVT、すなわちVT(0)は、サブスレッショルド電流を許容できる大きな値0.2V(図2ではa点)と仮定する。入力電圧が0VからVINになると、MOSTのVTはVT(0)−k2Vwellとなるが、その時点でMOSTがオンしたとすると、
Vwell = k1VIN
VIN = VT(0)−k2Vwell
∴ VIN = VT(0)/(1+k1k2)―――――――――――――(1)
となる。したがって、オンとなり始める入力電圧は係数(1+k1k2)だけ小さくなる。実は、この入力電圧こそダイナミックに変化した結果のNMOSTのVTであり、それが小さくなったことを示す。
VT(0)−k2Vwell = VT(0)−k1k2VIN < 0 ―――――(2)
に設定すればよい。したがって、まずk1を大きくする回路方式が重要である。それには、ウエル電圧振幅をできるだけ大きくすればよい。図1の実施例がまさにそれである。あるいは図13(b)の回路なら大きな入力電圧、すなわち大きなVDDを使えば効果的である。k2を大きくするMOST構造も重要である。このためにはBOX層の厚さを薄くして下部MOSTの働きを高めることである。しかし薄くしすぎるとトンネル電流が発生するので、二酸化シリコン膜厚で2nm程度がその限界である。ただし膜厚2nm程度の二酸化シリコン膜以外に、BOX層形成後に必要な高温処理温度でもゲート膜界面が安定性を維持するのでオキシナイトライド(SiON)膜なども好適である。この場合には、二酸化シリコン膜換算で1.5nm程度にまで薄膜化できる。以上の動作と効果はPMOSTについても同様である。
Claims (6)
- 第1のゲートと埋め込み酸化膜の下に存在するウエル層を第2のゲートとする二重ゲートを持ちSOI層が完全に空乏化したSOI構造を有する第1のMOSトランジスタを含む第1の回路と、前記第1のMOSトランジスタの前記第1のゲートとその入力が接続され前記第1のMOSトランジスタの前記第2のゲートとその出力が接続される第2の回路とを有し、
前記第2の回路は、前記第1のMOSトランジスタの前記第2のゲートの電圧を制御する回路であって、前記第2の回路の出力パルスの電圧振幅は前記第1の回路の入力パルスの電圧振幅よりも大きく、
前記第2の回路は、前記第1の回路の入力電圧を検出し、その検出電圧から前記第1の回路の入力電圧よりも大きな電圧に変換する回路であることを特徴とする半導体装置。 - 請求項1において、
前記第1のMOSトランジスタの前記第2のゲートの電圧を、前記第1のMOSトランジスタの閾値電圧が導通時には小さくなるように、また非導通時には大きくなるように制御することを特徴とする半導体装置。 - 請求項1において、
前記第1の回路の入力電圧の高レベルと低レベルは、前記第1のMOSトランジスタの前記第1のゲートあるいは前記第2のゲートの高レベルと低レベルの間に設定されることを特徴とする半導体装置。 - 請求項1において、
前記第2の回路は、その第1のゲートとその第2のゲートとを直接接続した第2のMOSトランジスタを含むことを特徴とする半導体装置。 - 請求項1において、
前記第2の回路は、前記第1の回路の入力電圧よりも大きな電圧で動作する第1のゲートと第2のゲートが接続された第3のMOSトランジスタを含むことを特徴とする半導体装置。 - 請求項1において、
前記第1のMOSトランジスタの非導通時の閾値電圧は、サブスレッショルド電流を許容する最小閾値電圧よりも大きな値に設定されることを特徴とする半導体装置。
Priority Applications (11)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005201054A JP4967264B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体装置 |
US11/362,172 US7511558B2 (en) | 2005-07-11 | 2006-02-27 | Semiconductor devices utilizing double gated fully depleted silicon on insulator MOS transistors |
TW095106628A TW200723499A (en) | 2005-07-11 | 2006-02-27 | Semiconductor devices |
EP06003938A EP1744364A3 (en) | 2005-07-11 | 2006-02-27 | Semiconductor devices |
KR1020060018925A KR101106916B1 (ko) | 2005-07-11 | 2006-02-27 | 반도체 장치 |
EP10002248A EP2207202A1 (en) | 2005-07-11 | 2006-02-27 | Semiconductor devices |
EP10002249A EP2207203A1 (en) | 2005-07-11 | 2006-02-27 | Semiconductor devices |
EP09001297A EP2053657B1 (en) | 2005-07-11 | 2006-02-27 | Method for operating a semiconductor device |
CN2008100868803A CN101281929B (zh) | 2005-07-11 | 2006-02-28 | 半导体器件 |
CNB2006100093694A CN100511688C (zh) | 2005-07-11 | 2006-02-28 | 半导体器件 |
US11/714,844 US7385436B2 (en) | 2005-07-11 | 2007-03-07 | Fully depleted silicon on insulator semiconductor devices |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005201054A JP4967264B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体装置 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2007019357A JP2007019357A (ja) | 2007-01-25 |
JP2007019357A5 JP2007019357A5 (ja) | 2008-02-21 |
JP4967264B2 true JP4967264B2 (ja) | 2012-07-04 |
Family
ID=36972724
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2005201054A Expired - Fee Related JP4967264B2 (ja) | 2005-07-11 | 2005-07-11 | 半導体装置 |
Country Status (6)
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---|---|
US (2) | US7511558B2 (ja) |
EP (4) | EP2053657B1 (ja) |
JP (1) | JP4967264B2 (ja) |
KR (1) | KR101106916B1 (ja) |
CN (2) | CN101281929B (ja) |
TW (1) | TW200723499A (ja) |
Families Citing this family (47)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4800700B2 (ja) * | 2005-08-01 | 2011-10-26 | ルネサスエレクトロニクス株式会社 | 半導体装置およびそれを用いた半導体集積回路 |
JP2007179602A (ja) * | 2005-12-27 | 2007-07-12 | Hitachi Ltd | 半導体装置 |
TWI355664B (en) * | 2006-09-29 | 2012-01-01 | Macronix Int Co Ltd | Method of reading a dual bit memory cell |
CN101680018B (zh) * | 2007-01-10 | 2017-03-15 | 海莫希尔有限责任公司 | 体外血液动力学的内皮/平滑肌细胞共培养模型在鉴定血管疾病的新型治疗靶标中的应用 |
TW200834525A (en) * | 2007-02-14 | 2008-08-16 | Advanced Analog Technology Inc | Image sticking erasing circuit, the method for performing the same and monitor control circuit thereof |
JP2009088387A (ja) * | 2007-10-02 | 2009-04-23 | Renesas Technology Corp | 半導体装置 |
JP5234333B2 (ja) * | 2008-05-28 | 2013-07-10 | Nltテクノロジー株式会社 | ゲート線駆動回路、アクティブマトリクス基板及び液晶表示装置 |
KR101623958B1 (ko) * | 2008-10-01 | 2016-05-25 | 삼성전자주식회사 | 인버터 및 그의 동작방법과 인버터를 포함하는 논리회로 |
US20100102872A1 (en) * | 2008-10-29 | 2010-04-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Dynamic Substrate Bias for PMOS Transistors to Alleviate NBTI Degradation |
KR101034615B1 (ko) * | 2009-08-11 | 2011-05-12 | 주식회사 하이닉스반도체 | 센스앰프 및 이를 포함하는 반도체 메모리장치 |
EP2320454A1 (en) * | 2009-11-05 | 2011-05-11 | S.O.I.Tec Silicon on Insulator Technologies | Substrate holder and clipping device |
FR2953636B1 (fr) * | 2009-12-08 | 2012-02-10 | Soitec Silicon On Insulator | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
FR2957193B1 (fr) | 2010-03-03 | 2012-04-20 | Soitec Silicon On Insulator | Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante |
US8508289B2 (en) | 2009-12-08 | 2013-08-13 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
FR2953643B1 (fr) | 2009-12-08 | 2012-07-27 | Soitec Silicon On Insulator | Cellule memoire flash sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
FR2953641B1 (fr) | 2009-12-08 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Circuit de transistors homogenes sur seoi avec grille de controle arriere enterree sous la couche isolante |
KR102480794B1 (ko) | 2009-12-28 | 2022-12-22 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | 기억 장치와 반도체 장치 |
FR2955195B1 (fr) | 2010-01-14 | 2012-03-09 | Soitec Silicon On Insulator | Dispositif de comparaison de donnees dans une memoire adressable par contenu sur seoi |
FR2955200B1 (fr) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree |
FR2955203B1 (fr) | 2010-01-14 | 2012-03-23 | Soitec Silicon On Insulator | Cellule memoire dont le canal traverse une couche dielectrique enterree |
FR2955204B1 (fr) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Cellule memoire dram disposant d'un injecteur bipolaire vertical |
FR2957186B1 (fr) | 2010-03-08 | 2012-09-28 | Soitec Silicon On Insulator | Cellule memoire de type sram |
FR2957449B1 (fr) | 2010-03-11 | 2022-07-15 | S O I Tec Silicon On Insulator Tech | Micro-amplificateur de lecture pour memoire |
FR2958441B1 (fr) | 2010-04-02 | 2012-07-13 | Soitec Silicon On Insulator | Circuit pseudo-inverseur sur seoi |
EP2372716A1 (en) * | 2010-04-02 | 2011-10-05 | S.O.I.Tec Silicon on Insulator Technologies | Pseudo-inverter circuit on SeOI |
EP2378549A1 (en) | 2010-04-06 | 2011-10-19 | S.O.I.Tec Silicon on Insulator Technologies | Method for manufacturing a semiconductor substrate |
EP2381470B1 (en) | 2010-04-22 | 2012-08-22 | Soitec | Semiconductor device comprising a field-effect transistor in a silicon-on-insulator structure |
US8988152B2 (en) * | 2012-02-29 | 2015-03-24 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US8624632B2 (en) | 2012-03-29 | 2014-01-07 | International Business Machines Corporation | Sense amplifier-type latch circuits with static bias current for enhanced operating frequency |
US9628075B2 (en) | 2012-07-07 | 2017-04-18 | Skyworks Solutions, Inc. | Radio-frequency switch having dynamic body coupling |
US9276570B2 (en) | 2012-07-07 | 2016-03-01 | Skyworks Solutions, Inc. | Radio-frequency switch having gate node voltage compensation network |
US9160328B2 (en) | 2012-07-07 | 2015-10-13 | Skyworks Solutions, Inc. | Circuits, devices, methods and applications related to silicon-on-insulator based radio-frequency switches |
US8975950B2 (en) * | 2012-07-07 | 2015-03-10 | Skyworks Solutions, Inc. | Switching device having a discharge circuit for improved intermodulation distortion performance |
US9148194B2 (en) | 2012-07-07 | 2015-09-29 | Skyworks Solutions, Inc. | Radio-frequency switch system having improved intermodulation distortion performance |
US9059702B2 (en) | 2012-07-07 | 2015-06-16 | Skyworks Solutions, Inc. | Switch linearization by non-linear compensation of a field-effect transistor |
US10147724B2 (en) | 2012-07-07 | 2018-12-04 | Skyworks Solutions, Inc. | Feed-forward circuit to improve intermodulation distortion performance of radio-frequency switch |
FR2999802A1 (fr) | 2012-12-14 | 2014-06-20 | St Microelectronics Sa | Cellule cmos realisee dans une technologie fd soi |
US9013225B2 (en) | 2013-02-04 | 2015-04-21 | Skyworks Solutions, Inc. | RF switches having increased voltage swing uniformity |
US8803591B1 (en) * | 2013-11-06 | 2014-08-12 | Freescale Semiconductor, Inc. | MOS transistor with forward bulk-biasing circuit |
US9178517B2 (en) * | 2013-11-12 | 2015-11-03 | Stmicroelectronics International N.V. | Wide range core supply compatible level shifter circuit |
US20150129967A1 (en) * | 2013-11-12 | 2015-05-14 | Stmicroelectronics International N.V. | Dual gate fd-soi transistor |
US9800204B2 (en) | 2014-03-19 | 2017-10-24 | Stmicroelectronics International N.V. | Integrated circuit capacitor including dual gate silicon-on-insulator transistor |
FR3034930B1 (fr) * | 2015-04-10 | 2019-06-14 | Universite De Nice | Procede et dispositif d'auto-calibration de circuits multi-grilles |
US9972395B2 (en) * | 2015-10-05 | 2018-05-15 | Silicon Storage Technology, Inc. | Row and column decoders comprising fully depleted silicon-on-insulator transistors for use in flash memory systems |
WO2018075988A1 (en) * | 2016-10-21 | 2018-04-26 | Hoey Thomas Joseph | Article retaining device and method of attachment |
US10469076B2 (en) * | 2016-11-22 | 2019-11-05 | The Curators Of The University Of Missouri | Power gating circuit utilizing double-gate fully depleted silicon-on-insulator transistor |
US11062745B2 (en) * | 2018-09-27 | 2021-07-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | FDSOI sense amplifier configuration in a memory device |
Family Cites Families (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5604368A (en) * | 1994-07-15 | 1997-02-18 | International Business Machines Corporation | Self-aligned double-gate MOSFET by selective lateral epitaxy |
TW295745B (ja) * | 1995-04-26 | 1997-01-11 | Matsushita Electric Ind Co Ltd | |
US5736435A (en) * | 1995-07-03 | 1998-04-07 | Motorola, Inc. | Process for fabricating a fully self-aligned soi mosfet |
JP3082671B2 (ja) * | 1996-06-26 | 2000-08-28 | 日本電気株式会社 | トランジスタ素子及びその製造方法 |
TW324862B (en) * | 1996-07-03 | 1998-01-11 | Hitachi Ltd | Liquid display apparatus |
US5831451A (en) * | 1996-07-19 | 1998-11-03 | Texas Instruments Incorporated | Dynamic logic circuits using transistors having differing threshold voltages |
JP3195256B2 (ja) * | 1996-10-24 | 2001-08-06 | 株式会社東芝 | 半導体集積回路 |
JPH10284729A (ja) * | 1997-02-07 | 1998-10-23 | Sony Corp | 絶縁ゲートトランジスタ素子及びその駆動方法 |
JP3732914B2 (ja) * | 1997-02-28 | 2006-01-11 | 株式会社ルネサステクノロジ | 半導体装置 |
US6037808A (en) * | 1997-12-24 | 2000-03-14 | Texas Instruments Incorporated | Differential SOI amplifiers having tied floating body connections |
US6121659A (en) * | 1998-03-27 | 2000-09-19 | International Business Machines Corporation | Buried patterned conductor planes for semiconductor-on-insulator integrated circuit |
JP3699823B2 (ja) * | 1998-05-19 | 2005-09-28 | 株式会社東芝 | 半導体装置 |
US6365465B1 (en) * | 1999-03-19 | 2002-04-02 | International Business Machines Corporation | Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques |
JP4439031B2 (ja) * | 1999-04-15 | 2010-03-24 | 株式会社ルネサステクノロジ | 半導体装置 |
US6239649B1 (en) * | 1999-04-20 | 2001-05-29 | International Business Machines Corporation | Switched body SOI (silicon on insulator) circuits and fabrication method therefor |
CN1139317C (zh) * | 1999-07-09 | 2004-02-25 | 北京锦绣大地农业股份有限公司 | 猪笼草工厂化快繁方法 |
JP2001044441A (ja) * | 1999-07-29 | 2001-02-16 | Sony Corp | 完全空乏soi型半導体装置及び集積回路 |
JP2002164544A (ja) * | 2000-11-28 | 2002-06-07 | Sony Corp | 半導体装置 |
US6404243B1 (en) * | 2001-01-12 | 2002-06-11 | Hewlett-Packard Company | System and method for controlling delay times in floating-body CMOSFET inverters |
US6686630B2 (en) | 2001-02-07 | 2004-02-03 | International Business Machines Corporation | Damascene double-gate MOSFET structure and its fabrication method |
JP3729082B2 (ja) * | 2001-04-25 | 2005-12-21 | 日本電信電話株式会社 | 半導体保護回路 |
US6433609B1 (en) * | 2001-11-19 | 2002-08-13 | International Business Machines Corporation | Double-gate low power SOI active clamp network for single power supply and multiple power supply applications |
JP2003152192A (ja) * | 2001-11-19 | 2003-05-23 | Sony Corp | 電界効果半導体装置及びその駆動方法 |
JP2004297048A (ja) * | 2003-03-11 | 2004-10-21 | Semiconductor Energy Lab Co Ltd | 集積回路、該集積回路を有する半導体表示装置及び集積回路の駆動方法 |
US7019342B2 (en) * | 2003-07-03 | 2006-03-28 | American Semiconductor, Inc. | Double-gated transistor circuit |
US6919647B2 (en) * | 2003-07-03 | 2005-07-19 | American Semiconductor, Inc. | SRAM cell |
JP2005116981A (ja) * | 2003-10-10 | 2005-04-28 | Hitachi Ltd | 半導体装置 |
JP3718512B2 (ja) * | 2003-10-24 | 2005-11-24 | 株式会社ルネサステクノロジ | 半導体装置 |
JP2005201054A (ja) | 2004-01-13 | 2005-07-28 | Koyo Seiko Co Ltd | ポンプ |
JP4795653B2 (ja) * | 2004-06-15 | 2011-10-19 | ルネサスエレクトロニクス株式会社 | 半導体記憶装置 |
US7091069B2 (en) * | 2004-06-30 | 2006-08-15 | International Business Machines Corporation | Ultra thin body fully-depleted SOI MOSFETs |
JP2006165808A (ja) * | 2004-12-03 | 2006-06-22 | Seiko Epson Corp | 差動増幅回路 |
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US7511558B2 (en) | 2009-03-31 |
CN101281929A (zh) | 2008-10-08 |
US20070152736A1 (en) | 2007-07-05 |
CN1897284A (zh) | 2007-01-17 |
US7385436B2 (en) | 2008-06-10 |
EP1744364A2 (en) | 2007-01-17 |
JP2007019357A (ja) | 2007-01-25 |
CN101281929B (zh) | 2010-10-13 |
EP1744364A3 (en) | 2008-06-04 |
CN100511688C (zh) | 2009-07-08 |
EP2053657B1 (en) | 2012-11-07 |
US20070008027A1 (en) | 2007-01-11 |
EP2053657A3 (en) | 2009-07-22 |
KR101106916B1 (ko) | 2012-01-25 |
KR20070007703A (ko) | 2007-01-16 |
EP2207203A1 (en) | 2010-07-14 |
EP2053657A2 (en) | 2009-04-29 |
TW200723499A (en) | 2007-06-16 |
EP2207202A1 (en) | 2010-07-14 |
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