FR2953636B1 - Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante - Google Patents
Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolanteInfo
- Publication number
- FR2953636B1 FR2953636B1 FR0958749A FR0958749A FR2953636B1 FR 2953636 B1 FR2953636 B1 FR 2953636B1 FR 0958749 A FR0958749 A FR 0958749A FR 0958749 A FR0958749 A FR 0958749A FR 2953636 B1 FR2953636 B1 FR 2953636B1
- Authority
- FR
- France
- Prior art keywords
- seoi
- controlling
- insulating layer
- memory cell
- control grid
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
- G11C11/404—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7841—Field effect transistors with field effect produced by an insulated gate with floating body, e.g. programmable transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/20—DRAM devices comprising floating-body transistors, e.g. floating-body cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/401—Indexing scheme relating to cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C2211/4016—Memory devices with silicon-on-insulator cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0958749A FR2953636B1 (fr) | 2009-12-08 | 2009-12-08 | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
US12/898,230 US20110134690A1 (en) | 2009-12-08 | 2010-10-05 | METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER |
EP10187012A EP2333779A1 (fr) | 2009-12-08 | 2010-10-08 | Procédé de commande d'une cellule mémoire dram sur SeOI disposant d'une seconde grille de contrôle enterrée sous la couche isolante |
TW099134576A TW201123453A (en) | 2009-12-08 | 2010-10-11 | Method of controlling a SeOI dram memory cell having a second control gate buried under the insulating layer |
SG2010076537A SG172527A1 (en) | 2009-12-08 | 2010-10-18 | Method of controlling a seoi dram memory cell having a second control gate buried under the insulating layer |
CN2010105284181A CN102087873A (zh) | 2009-12-08 | 2010-10-28 | 控制具有第二控制栅极的dram存储器单元的方法 |
KR1020100106797A KR20110065316A (ko) | 2009-12-08 | 2010-10-29 | 절연층 아래에 매설된 제2 제어 게이트를 갖는 SeOI DRAM 메모리 셀을 제어하는 방법 |
JP2010244690A JP2011123985A (ja) | 2009-12-08 | 2010-10-29 | 第2のコントロールゲートを絶縁層の下に埋め込んだSeOIDRAMメモリセルをコントロールする方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FR0958749A FR2953636B1 (fr) | 2009-12-08 | 2009-12-08 | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2953636A1 FR2953636A1 (fr) | 2011-06-10 |
FR2953636B1 true FR2953636B1 (fr) | 2012-02-10 |
Family
ID=42173895
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0958749A Expired - Fee Related FR2953636B1 (fr) | 2009-12-08 | 2009-12-08 | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
Country Status (8)
Country | Link |
---|---|
US (1) | US20110134690A1 (fr) |
EP (1) | EP2333779A1 (fr) |
JP (1) | JP2011123985A (fr) |
KR (1) | KR20110065316A (fr) |
CN (1) | CN102087873A (fr) |
FR (1) | FR2953636B1 (fr) |
SG (1) | SG172527A1 (fr) |
TW (1) | TW201123453A (fr) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9214400B2 (en) * | 2011-08-31 | 2015-12-15 | Institute of Microelectronics, Chinese Academy of Sciences | Semiconductor device with back gate isolation regions and method for manufacturing the same |
FR3001333B1 (fr) * | 2013-01-22 | 2016-05-06 | Soitec Silicon On Insulator | Grille arriere dans transistor de selection pour dram embarquee |
CN103824861A (zh) * | 2014-01-15 | 2014-05-28 | 上海新储集成电路有限公司 | 一种鳍状背栅的存储结构及其浮体单元的自动刷新方法 |
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-
2009
- 2009-12-08 FR FR0958749A patent/FR2953636B1/fr not_active Expired - Fee Related
-
2010
- 2010-10-05 US US12/898,230 patent/US20110134690A1/en not_active Abandoned
- 2010-10-08 EP EP10187012A patent/EP2333779A1/fr not_active Withdrawn
- 2010-10-11 TW TW099134576A patent/TW201123453A/zh unknown
- 2010-10-18 SG SG2010076537A patent/SG172527A1/en unknown
- 2010-10-28 CN CN2010105284181A patent/CN102087873A/zh active Pending
- 2010-10-29 KR KR1020100106797A patent/KR20110065316A/ko active Search and Examination
- 2010-10-29 JP JP2010244690A patent/JP2011123985A/ja active Pending
Also Published As
Publication number | Publication date |
---|---|
SG172527A1 (en) | 2011-07-28 |
EP2333779A1 (fr) | 2011-06-15 |
KR20110065316A (ko) | 2011-06-15 |
TW201123453A (en) | 2011-07-01 |
JP2011123985A (ja) | 2011-06-23 |
US20110134690A1 (en) | 2011-06-09 |
CN102087873A (zh) | 2011-06-08 |
FR2953636A1 (fr) | 2011-06-10 |
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