JP4762036B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP4762036B2 JP4762036B2 JP2006112190A JP2006112190A JP4762036B2 JP 4762036 B2 JP4762036 B2 JP 4762036B2 JP 2006112190 A JP2006112190 A JP 2006112190A JP 2006112190 A JP2006112190 A JP 2006112190A JP 4762036 B2 JP4762036 B2 JP 4762036B2
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- 239000004065 semiconductor Substances 0.000 title claims description 35
- 230000015654 memory Effects 0.000 claims description 36
- 239000000758 substrate Substances 0.000 claims description 28
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 21
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 21
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 20
- 238000002955 isolation Methods 0.000 claims description 20
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 20
- 239000012528 membrane Substances 0.000 claims description 5
- 239000010408 film Substances 0.000 description 244
- 150000004767 nitrides Chemical class 0.000 description 43
- 229910004298 SiO 2 Inorganic materials 0.000 description 32
- 208000024875 Infantile dystonia-parkinsonism Diseases 0.000 description 28
- 208000001543 infantile parkinsonism-dystonia Diseases 0.000 description 28
- 230000000694 effects Effects 0.000 description 14
- 238000000034 method Methods 0.000 description 12
- 238000005121 nitriding Methods 0.000 description 12
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 9
- 229910052710 silicon Inorganic materials 0.000 description 9
- 239000010703 silicon Substances 0.000 description 9
- 238000009826 distribution Methods 0.000 description 7
- 239000011800 void material Substances 0.000 description 7
- 238000005530 etching Methods 0.000 description 6
- 238000004519 manufacturing process Methods 0.000 description 6
- 229910052757 nitrogen Inorganic materials 0.000 description 6
- 239000002019 doping agent Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 241000894007 species Species 0.000 description 4
- 230000007423 decrease Effects 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 2
- 230000014759 maintenance of location Effects 0.000 description 2
- -1 nitrogen ions Chemical class 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910020286 SiOxNy Inorganic materials 0.000 description 1
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 1
- 241001122767 Theaceae Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Description
NAND型フラッシュメモリを微細化していくためには、トンネルゲート絶縁膜やゲート電極間絶縁膜(以下、IPD膜という)の薄膜化を行ったほうが都合がよい。しかし、データ保持特性を確保するために薄膜化を進めることは困難であった。
まず、図3を用いて本発明者らが検討した問題点について説明する。図3では、IPD膜として、SiO2 膜15a、Si3 N4 膜15b、SiO2 膜15cを順次積層してなるONO膜を使用している。
図11および図12を用いて第2の実施形態を説明する。以下の図において、既出の図と対応する部分には既出の図と同一符号を付してあり、詳細な説明は省略する。
Claims (5)
- 半導体基板と、
前記半導体基板に設けられた素子分離絶縁膜と、
前記半導体基板上に設けられた複数の不揮発性メモリセルと
を具備してなる半導体装置であって、
前記不揮発性メモリセルは、
前記半導体基板上に設けられたトンネル絶縁膜と、
前記トンネル絶縁膜上に設けられたフローティングゲート電極と、
前記フローティングゲート電極の上方に設けられたコントロールゲート電極と、
前記コントロールゲート電極と前記フローティングゲート電極との間に設けられ、シリコン酸化膜と、前記シリコン酸化膜上に接して設けられ、前記シリコン酸化膜よりも誘電率が高いシリコン窒化膜もしくはオキシナイトライド膜とを含む電極間絶縁膜とを備え、
前記電極間絶縁膜は、前記不揮発性メモリセルのチャネル幅方向の断面において、前記フローティングゲート電極の側壁上に設けられており、かつ、前記側壁の上部から下部に向かって厚さが増加し、
前記シリコン窒化膜もしくはオキシナイトライド膜は、前記チャネル幅方向の断面において、前記フローティングゲート電極の上部角部での厚さが前記フローティングゲート電極の側壁上における他の部分よりも厚いことを特徴とする半導体装置。 - 前記素子分離絶縁膜は、前記チャネル幅方向の断面において、隣接するフローティングゲート電極間に存在しており、前記シリコン窒化膜もしくはオキシナイトライド膜は、前記隣接するフローティングゲート電極間の前記素子分離絶縁膜の上面上での厚さが他の部分よりも薄いことを特徴とする請求項1に記載の半導体装置。
- 半導体基板と、
前記半導体基板に設けられた素子分離絶縁膜と、
前記半導体基板上に設けられた複数の不揮発性メモリセルと
を具備してなる半導体装置であって、
前記不揮発性メモリセルは、
前記半導体基板上に設けられたトンネル絶縁膜と、
前記トンネル絶縁膜上に設けられたフローティングゲート電極と、
前記フローティングゲート電極の上方に設けられたコントロールゲート電極と、
前記コントロールゲート電極と前記フローティングゲート電極との間に設けられ、シリコン酸化膜と、前記シリコン酸化膜上に接して設けられ、前記シリコン酸化膜よりも誘電率が高いシリコン窒化膜もしくはオキシナイトライド膜とを含む電極間絶縁膜とを備え、
前記電極間絶縁膜は、前記不揮発性メモリセルのチャネル幅方向の断面において、前記フローティングゲート電極の側壁上に設けられており、かつ、前記側壁の上部から下部に向かって厚さが増加し、
前記素子分離絶縁膜は、前記チャネル幅方向の断面において、隣接するフローティングゲート電極間に存在しており、
前記シリコン窒化膜もしくはオキシナイトライド膜は、前記隣接するフローティングゲート電極間の前記素子分離絶縁膜の上面上での厚さが他の部分よりも薄いことを特徴とする半導体装置。 - 前記フローティングゲート電極は、前記チャネル幅方向の断面において、前記半導体基板の表面に対して垂直な側壁を有することを特徴とする請求項1ないし3のいずれか1項に記載の半導体装置。
- 前記シリコン窒化膜もしくはオキシナイトライド膜は、前記電極間絶縁膜の最上層のシリコン窒化膜もしくはオキシナイトライド膜であることを特徴とする請求項1ないし4のいずれか1項に記載の半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006112190A JP4762036B2 (ja) | 2006-04-14 | 2006-04-14 | 半導体装置 |
US11/783,933 US7612404B2 (en) | 2006-04-14 | 2007-04-13 | Semiconductor device |
KR1020070036348A KR20070102422A (ko) | 2006-04-14 | 2007-04-13 | 반도체 장치 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006112190A JP4762036B2 (ja) | 2006-04-14 | 2006-04-14 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
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JP2007287857A JP2007287857A (ja) | 2007-11-01 |
JP4762036B2 true JP4762036B2 (ja) | 2011-08-31 |
Family
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Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2006112190A Expired - Fee Related JP4762036B2 (ja) | 2006-04-14 | 2006-04-14 | 半導体装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7612404B2 (ja) |
JP (1) | JP4762036B2 (ja) |
KR (1) | KR20070102422A (ja) |
Families Citing this family (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4921848B2 (ja) * | 2006-05-09 | 2012-04-25 | 株式会社東芝 | 半導体装置およびその製造方法 |
CN101680018B (zh) * | 2007-01-10 | 2017-03-15 | 海莫希尔有限责任公司 | 体外血液动力学的内皮/平滑肌细胞共培养模型在鉴定血管疾病的新型治疗靶标中的应用 |
JP2009152498A (ja) * | 2007-12-21 | 2009-07-09 | Toshiba Corp | 不揮発性半導体メモリ |
JP5361328B2 (ja) | 2008-10-27 | 2013-12-04 | 株式会社東芝 | 不揮発性半導体記憶装置の製造方法 |
JP2010283127A (ja) * | 2009-06-04 | 2010-12-16 | Toshiba Corp | 半導体装置およびその製造方法 |
EP2320454A1 (en) * | 2009-11-05 | 2011-05-11 | S.O.I.Tec Silicon on Insulator Technologies | Substrate holder and clipping device |
FR2953641B1 (fr) * | 2009-12-08 | 2012-02-10 | S O I Tec Silicon On Insulator Tech | Circuit de transistors homogenes sur seoi avec grille de controle arriere enterree sous la couche isolante |
FR2953636B1 (fr) * | 2009-12-08 | 2012-02-10 | Soitec Silicon On Insulator | Procede de commande d'une cellule memoire dram sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
US8508289B2 (en) * | 2009-12-08 | 2013-08-13 | Soitec | Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer |
FR2953643B1 (fr) * | 2009-12-08 | 2012-07-27 | Soitec Silicon On Insulator | Cellule memoire flash sur seoi disposant d'une seconde grille de controle enterree sous la couche isolante |
FR2957193B1 (fr) | 2010-03-03 | 2012-04-20 | Soitec Silicon On Insulator | Cellule a chemin de donnees sur substrat seoi avec grille de controle arriere enterree sous la couche isolante |
FR2955204B1 (fr) * | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Cellule memoire dram disposant d'un injecteur bipolaire vertical |
FR2955203B1 (fr) | 2010-01-14 | 2012-03-23 | Soitec Silicon On Insulator | Cellule memoire dont le canal traverse une couche dielectrique enterree |
FR2955200B1 (fr) | 2010-01-14 | 2012-07-20 | Soitec Silicon On Insulator | Dispositif, et son procede de fabrication, disposant d'un contact entre regions semi-conductrices a travers une couche isolante enterree |
FR2955195B1 (fr) * | 2010-01-14 | 2012-03-09 | Soitec Silicon On Insulator | Dispositif de comparaison de donnees dans une memoire adressable par contenu sur seoi |
FR2957186B1 (fr) * | 2010-03-08 | 2012-09-28 | Soitec Silicon On Insulator | Cellule memoire de type sram |
FR2957449B1 (fr) | 2010-03-11 | 2022-07-15 | S O I Tec Silicon On Insulator Tech | Micro-amplificateur de lecture pour memoire |
FR2958441B1 (fr) | 2010-04-02 | 2012-07-13 | Soitec Silicon On Insulator | Circuit pseudo-inverseur sur seoi |
EP2378549A1 (en) | 2010-04-06 | 2011-10-19 | S.O.I.Tec Silicon on Insulator Technologies | Method for manufacturing a semiconductor substrate |
EP2381470B1 (en) | 2010-04-22 | 2012-08-22 | Soitec | Semiconductor device comprising a field-effect transistor in a silicon-on-insulator structure |
JP2012114199A (ja) * | 2010-11-24 | 2012-06-14 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
KR20120085360A (ko) * | 2011-01-24 | 2012-08-01 | 삼성전자주식회사 | 게이트 구조물, 게이트 구조물 형성 방법 및 이를 이용한 반도체 소자 제조 방법 |
JP2013065776A (ja) | 2011-09-20 | 2013-04-11 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
KR101906167B1 (ko) * | 2011-10-27 | 2018-10-12 | 삼성전자주식회사 | 비휘발성 메모리 장치 및 그 제조 방법 |
US8994089B2 (en) * | 2011-11-11 | 2015-03-31 | Applied Materials, Inc. | Interlayer polysilicon dielectric cap and method of forming thereof |
JP2013131606A (ja) | 2011-12-21 | 2013-07-04 | Toshiba Corp | 半導体装置 |
US8704289B2 (en) * | 2011-12-27 | 2014-04-22 | Kabushiki Kaisha Toshiba | Nonvolatile semiconductor memory device |
US11588031B2 (en) * | 2019-12-30 | 2023-02-21 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor structure for memory device and method for forming the same |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
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JP2670330B2 (ja) * | 1989-01-17 | 1997-10-29 | 株式会社東芝 | 不揮発性半導体記憶装置 |
JPH08316348A (ja) * | 1995-03-14 | 1996-11-29 | Toshiba Corp | 半導体装置およびその製造方法 |
JPH10189579A (ja) * | 1996-12-27 | 1998-07-21 | Toshiba Corp | 半導体装置の製造方法 |
JPH11204788A (ja) * | 1998-01-19 | 1999-07-30 | Toshiba Corp | 半導体装置およびその製造方法 |
JP2001326287A (ja) * | 2000-05-17 | 2001-11-22 | Nec Corp | 半導体装置の製造方法 |
JP4068286B2 (ja) * | 2000-06-30 | 2008-03-26 | 株式会社東芝 | 半導体装置の製造方法 |
JP5068402B2 (ja) * | 2000-12-28 | 2012-11-07 | 公益財団法人国際科学振興財団 | 誘電体膜およびその形成方法、半導体装置、不揮発性半導体メモリ装置、および半導体装置の製造方法 |
US6844604B2 (en) | 2001-02-02 | 2005-01-18 | Samsung Electronics Co., Ltd. | Dielectric layer for semiconductor device and method of manufacturing the same |
JP3845073B2 (ja) | 2003-05-27 | 2006-11-15 | 株式会社東芝 | 半導体装置 |
JP4237561B2 (ja) | 2003-07-04 | 2009-03-11 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
KR100546694B1 (ko) | 2004-05-06 | 2006-01-26 | 동부아남반도체 주식회사 | 비휘발성 메모리 장치 및 그 제조방법 |
JP2006019579A (ja) * | 2004-07-02 | 2006-01-19 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4734019B2 (ja) * | 2005-04-26 | 2011-07-27 | 株式会社東芝 | 半導体記憶装置及びその製造方法 |
-
2006
- 2006-04-14 JP JP2006112190A patent/JP4762036B2/ja not_active Expired - Fee Related
-
2007
- 2007-04-13 US US11/783,933 patent/US7612404B2/en not_active Expired - Fee Related
- 2007-04-13 KR KR1020070036348A patent/KR20070102422A/ko not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
US20070241388A1 (en) | 2007-10-18 |
JP2007287857A (ja) | 2007-11-01 |
US7612404B2 (en) | 2009-11-03 |
KR20070102422A (ko) | 2007-10-18 |
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