WO2003094235A1 - Dispositif de circuit integre a semiconducteur - Google Patents

Dispositif de circuit integre a semiconducteur Download PDF

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Publication number
WO2003094235A1
WO2003094235A1 PCT/JP2002/004323 JP0204323W WO03094235A1 WO 2003094235 A1 WO2003094235 A1 WO 2003094235A1 JP 0204323 W JP0204323 W JP 0204323W WO 03094235 A1 WO03094235 A1 WO 03094235A1
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WIPO (PCT)
Prior art keywords
circuit
substrate bias
voltage
substrate
bias voltage
Prior art date
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PCT/JP2002/004323
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English (en)
Japanese (ja)
Inventor
Toshio Sasaki
Yoshio Takazawa
Toshio Yamada
Shinya Aizawa
Shigeru Shimada
Toshikazu Matsui
Akihisa Uchida
Original Assignee
Renesas Technology Corp.
Hitachi Ulsi Systems Co., Ltd.
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Application filed by Renesas Technology Corp., Hitachi Ulsi Systems Co., Ltd. filed Critical Renesas Technology Corp.
Priority to JP2004502355A priority Critical patent/JPWO2003094235A1/ja
Priority to PCT/JP2002/004323 priority patent/WO2003094235A1/fr
Priority to TW091116172A priority patent/TW595007B/zh
Publication of WO2003094235A1 publication Critical patent/WO2003094235A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0921—Means for preventing a bipolar, e.g. thyristor, action between the different transistor regions, e.g. Latchup prevention
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Definitions

  • the present invention relates to a semiconductor integrated circuit device, and more particularly to a technology that is effective when used for a low power consumption technology in a standby mode in a MS integrated circuit.
  • Akita
  • a so-called standby mode in which the operation is stopped while the power supply voltage is applied is set as necessary.
  • the standby mode may include a state in which the memory data is kept retained. In standby mode, it is desirable that the power supply current flowing through the integrated circuit be small.
  • Japanese Patent Application Laid-Open No. H10-242839 discloses an example of a technique for reducing the leakage current in the standby mode.
  • This publication discloses a high-threshold MOS circuit composed of a high-threshold M ⁇ SF ET and a low-threshold MOS circuit composed of a low-threshold MOSFET. It is disclosed that bias control, that is, reduction of MOSFET leakage current by increasing the substrate bias voltage is disclosed.
  • the present inventors evaluated the characteristics of the current in the off state or the gate off (standby) of the MOSFET in the evaluation of the LSI (Large Scale Integrated Circuit). As shown in the figure, even if the substrate bias voltage is increased, It was found that the leakage current did not decrease in the MOSFET and could not be within the target current range.
  • the current flowing through the MOSFET that should be in the off state depends on the channel leakage current flowing between its drain and source and the junction current flowing through a junction such as the drain junction.
  • the junction leakage current may increase to exceed the above-described reduction in channel leakage. I came out.
  • a metal silicide layer is provided on the surface of such a source / drain semiconductor layer, the junction leakage tends to increase.
  • the channel leakage current I 1 of the MOSFET having a low threshold (hereinafter referred to as a low Vth region MOS) is reduced.
  • the channel leakage current I 2 of the MOSFET having a high threshold (hereinafter referred to as high Vth region MOS) is significantly small, and the application of the substrate noise voltage is shown in FIG. When turned on, it increases the junction leakage and increases the current component consumed by the substrate bias generation circuit to form the substrate bias voltage, making it difficult to reduce the target standby current. I found
  • An object of the present invention is to provide a semiconductor integrated circuit device which solves the above-described problems and reduces current consumption (leakage current) during standby. Another object of the present invention is to provide a stabilizing device in response to miniaturization of elements and manufacturing variations. An object of the present invention is to provide a semiconductor integrated circuit device in which current consumption during standby is reduced.
  • FIG. 1 is a characteristic diagram for explaining a relationship between a substrate bias voltage V BB and a standby current I s b for explaining the present invention.
  • FIG. 2 is a schematic sectional view of an element structure showing one embodiment of an N-channel M ⁇ S FET used in the present invention.
  • FIG. 3 is a schematic diagram for explaining a metal silicide film leak in the MOS FET used in the present invention.
  • FIG. 4 is a configuration diagram showing one embodiment of a semiconductor integrated circuit device to which the present invention is applied.
  • FIG. 5 is a schematic sectional view of the element structure corresponding to the enlarged element pattern of FIG.
  • FIG. 6 shows the threshold voltage and the threshold voltage of the M ⁇ SFET for explaining the present invention.
  • 'I a characteristic diagram showing the relationship with the current
  • FIG. 7 is a flowchart showing one embodiment of a data writing method for setting a substrate bias.
  • FIG. 8 is a block diagram showing one embodiment of a substrate bias generation circuit according to the present invention.
  • FIG. 9 is a block diagram showing another embodiment of the substrate bias generation circuit according to the present invention.
  • FIG. 10 is a circuit diagram showing an embodiment of a charge pump circuit for generating a negative voltage used in the present invention.
  • FIG. 11 is a circuit diagram showing an embodiment of an oscillation circuit for forming an oscillation pulse supplied to the charge pump circuit of FIG. 10,
  • FIG. 12 is a circuit diagram showing one embodiment of the level sensor for the negative voltage VBB (VBN) of FIG.
  • FIG. 13 is a block diagram showing still another embodiment of the substrate bias generating circuit according to the present invention.
  • FIG. 14 is a block diagram showing one embodiment of a monitor circuit for the Vdd leakage current of FIG. 13;
  • FIG. 15 is a characteristic diagram for explaining a relationship between a threshold voltage and a channel leak current for explaining the present invention.
  • FIG. 16 is a characteristic diagram for explaining the relationship between the substrate bias voltage and the total power for explaining the present invention.
  • FIG. 1 shows a substrate bias voltage VBB and a switch for explaining the present invention.
  • a characteristic diagram for explaining the relationship between the evening current I sb is shown.
  • channel leakage (sub-threshold current) 1 is reduced by applying a substrate bias to the M ⁇ SFET and shifting the threshold voltage Vth to a positive value (higher Vth).
  • Figure 1 shows that the reduction extends over one or two orders of magnitude.
  • the junction leakage tends to increase as the substrate bias is applied deeply.
  • This junction leakage together with the well-known drain-source pn junction leakage, and the purpose of reducing the resistance at the source / drain contact area due to miniaturization, have been developed to reduce the source and drain semiconductor layers.
  • a metal silicide film is provided on the surface of the substrate, there is a leakage current 3 flowing from the film portion to the substrate. Contrary to the empirical prediction that channel leakage has been regarded as dominant, it has been found that the junction leakage observed in recent miniaturized MOSFETs becomes large enough to be ignored. did.
  • a step-down internal voltage V dd is set for the power supply of the core circuit (internal circuit), and the high voltage system of the input / output interface circuit is set.
  • the power supply voltage VCC supplied from the external pin is set, and the substrate node voltage may be generated from the substrate bias generation circuit operated by the latter high-voltage power supply voltage VCC.
  • the amount of current flowing through the high-voltage VCC must also take into account the amount of current flowing through the substrate noise generating circuit. This current component increases in proportion to increasing the substrate bias.
  • the standby current of the LSI is plotted with the substrate bias VBB on the horizontal axis. Then, the channel leakage decreases in proportion to the increase of the node voltage VBB, and the junction leakages (2) and (3) are inversely proportional.
  • the leakage currents (1) and (2) + (3) of the above both have the intersection points A and B where the standby current is the minimum with respect to the substrate bias voltage VB B. During standby, the substrate bias is applied at those points. Make it work.
  • a MOS circuit is composed of two types of MOS FETs having a threshold voltage and a threshold voltage Vth
  • channel leakage is large in an off state where no substrate bias is applied in a MOS device with a low threshold voltage Vth (low Vth).
  • Vth low threshold voltage
  • the junction voltage becomes large when the substrate bias is turned on, and as a result, the junction leakage increases and the current consumed by the substrate bias generation circuit increases, but the standby current is reduced by about one digit or more compared to when the substrate bias is not applied. I do.
  • the high-Vth MS device Since the high-Vth MS device has a small channel leak in the off state where no substrate noise is applied, if the same substrate bias voltage is supplied as the low-Vth MFET device, junction leakage will occur as shown at point A. The sum of the currents consumed by the substrate bias generation circuit is greater than the reduction in channel leakage. Therefore, in addition to the substrate bias voltage generation circuit for the low Vth MOSFET, a substrate bias voltage generation circuit for the high Vth M ⁇ SFET is provided, and the substrate bias voltage value is made shallow as shown at point B. The optimum bias is applied so that the channel leakage of such a high Vth MOSFET is reduced and the junction voltage is reduced so that the substrate noise generation circuit and the junction leakage component are also at low levels.
  • the high-Vth LSI in the standby mode, is a p-type substrate in which a power supply voltage near Vdd and an N-channel MOSFET are formed on an n-type substrate on which a P-channel MOSFET is formed. A value close to the ground voltage Vs s is applied to.
  • a low Vth LSI applies a voltage higher than Vdd to the n-type substrate where the P-channel MOSFET is formed, and a negative voltage lower than Vss to the p-type substrate where the N-channel M-SFET is formed. Apply.
  • M ⁇ S is originally referred to simply as a metal “oxide” semiconductor configuration.
  • M ⁇ S which is a general name in recent years, is used to replace metal in the essential parts of semiconductor devices with non-metallic electrical conductors such as polysilicon, and oxides with other insulators. It includes things that change.
  • CMOS has also come to be understood as having a wide range of technical implications in response to changes in the perception of MS as described above.
  • M ⁇ SF ET is also not understood in the same narrow sense, but in its broad sense, including in its broadest sense virtually as an insulated gate field effect transistor .
  • the CMOS, MOSFET, etc. of the present invention follow the common names.
  • FIG. 2 is a schematic sectional view of the element structure of an embodiment of the N-channel MSFET used in the present invention.
  • FIG. 2 also shows the structure of the element and a place where a leak current is generated.
  • a gate electrode is formed via a gate insulating film so as to straddle a source and drain region formed of an n + type diffusion layer formed in a p-type well and the source and drain regions.
  • the p-type cell has a substrate bias voltage (-Vbb) through a contact portion made of a p + -type diffusion layer.
  • a metal silicide film is provided on the surface of each of the diffusion layers and on the polysilicon gate electrode.
  • the standby (leak) current is composed of channel leak (sub-threshold) 1 and junction leak (pn junction leak 2 + metal silicide film leak 3).
  • FIG. 3 is a schematic diagram for explaining a metal silicide film leak in the MOS FET used in the present invention.
  • FIG. 3 at the boundary between the separation layer SGI and the diffusion layer L, that is, the part where the gate electrode and the source / drain diffusion layers are in contact with each other, It was observed that it reached deeper than the part.
  • the metal silicide film short-circuits the pn junction with a relatively high resistance, and the current generated in such a portion generates the above-mentioned metal silicide film REET 3, which causes leakage between the substrate and the substrate. Considered as current.
  • metal silicide film leakage is also treated as junction leakage.
  • the channel leakage is dominant in the low Vth M ⁇ S FET standby current when the substrate is biased off, and in the substrate no-son state, Vth increases as the substrate noise increases and channel leakage decreases.
  • increasing the substrate bias also increases the junction leakage.
  • the substrate bias is applied deeper than a predetermined value (point A in Fig. 1), the current relationship when the substrate bias is on and the substrate bias is off is reversed. Therefore, in the stand-alone mode, it is set near a predetermined value (point A in the figure) where the sum of the channel leak and the junction leak is minimum.
  • the standby current of the high Vth-MOSFET has a considerably low channel leakage 1, and when the substrate noise is applied, the standby current increases. Junction leakage 1 + 3 increases and becomes dominant. Therefore, it is set near a predetermined value (point B in the figure) different from point A where the sum of channel leak 1 and junction leak 2 + 3 is minimum.
  • FIG. 4 shows a configuration diagram of an embodiment of a semiconductor integrated circuit device to which the present invention is applied. The figure also shows an element pattern in which a part of the pattern is enlarged.
  • FIG. 5 is a schematic cross-sectional view of the element structure corresponding to the enlarged element pattern.
  • CMOS devices are required to have high speed and low power consumption. Even a CPU etc. can be divided into a critical path section that operates at high speed and a data setting section or I / O interface I • section that operates relatively slowly. Accordingly, in the semiconductor integrated circuit device (LSI) of this embodiment, a low-Vth MOS FET is used for the high-speed circuit as described above, and the other circuits, that is, the input / output interface are used. ⁇ ⁇ ⁇ ⁇ Configured using high Vth MS FET for low-speed circuits. In the figure, the low Vth region is a circuit region where a low Vth is formed, and the high Vth region is a circuit region where a high Vth is formed.
  • the low Vth region is a low-Vth P-channel MOSFET.
  • the high Vth region is composed of a high Vth P-channel MOSFET and an N-channel MOSFET.
  • the LSI of this embodiment is a multi-device having two or more Vths such as high Vth and low Vth. Vth specification.
  • the element of the CMOS inverter circuit is used as an example of the CMOS circuit formed in each of the low Vth region and the high Vth region.
  • the turn is shown as an enlarged portion as a representative, and FIG. 5 shows a cross-sectional view of the element structure.
  • the P-channel MOS FET (pMOS) constituting the inverter circuit is formed n-pole, and the N-channel MOSFE T (nMO S) is formed in p-well.
  • the substrate bias voltage VBP1 is supplied to the n-pole where the P-channel MOSFET (pMOS) in the low Vth region is formed, and the N-channel MOS FET ( The substrate bias voltage VB N1 is supplied to the p-well where the nMOS is formed.
  • the substrate bias circuits VBP 1 -G and VBN 1 -G are activated when the semiconductor integrated circuit device LSI is in the standby mode, and generate the substrate bias voltages VBP 1 and VBN 1.
  • each of the substrate bias voltages V BP 1 and VBN 1 includes an oscillation circuit, a charge pump circuit, and a level determination circuit, and the voltages VBP 1 and VBN 1 correspond to the point A. It operates to become voltage.
  • the leakage current in the P-channel MOSFET and the N-channel MOSFET in the high V th region is small even when the substrate bias voltage is zero, that is, even when the potential of the capacitor and the source is the same. Since the amount of decrease when a shallow bias voltage like a point is supplied is extremely smaller than the amount of decrease when the bias voltages V BP1 and VB1 are applied in the low Vth region, the P-channel MOSFET (pMOS) is formed The n-pole is short-circuited to its source and is given a fixed operating voltage Vdd, forming an N-channel MOSFET (nMOS) . The p-well is short-circuited to its source and has a fixed ground potential V ss Given to. In the case of such a configuration, in the LSI having the characteristic diagram of FIG. 16, it is possible to set the total power consumption of the high Vth region to the minimum point while setting the total power consumption of the low Vth region to the minimum point. It becomes possible.
  • the voltage of the P-channel MFETSFET n-type substrate in the high Vth region is set near Vdd
  • the voltage of the p-type N-type MOSFET substrate is set near Vss.
  • the reason for this is that, as described above, since the high-Vth MOSFET has a small channel leakage (1) during standby, the total leakage current of the junction leakage (1) and (3) and the current component consumed by the substrate bias generation circuit must be considered. No substrate bias is applied. As a result, the standby current can be reduced by reducing the junction leakage or by stopping the substrate bias generation circuit.
  • the n-type substrate voltage of the P-channel MOSFET is higher than Vdd
  • the p-type substrate voltage of the N-channel M NSFET is lower than Vss
  • the leakage current is minimized.
  • the low Vth MOSFET has a large channel leak during the stand-by mode, so the amount of channel leak reduction due to the substrate noise effect is due to the increase in junction leakage and the occurrence of substrate bias. This is because the sum of the currents consumed in the circuit is more than the amount considered. At this time, the substrate noise should be considered in consideration of the junction leakage that increases in proportion to the junction voltage.
  • the present invention can also be applied to an LSI of a single Vth specification in which Vth is formed in one type.
  • MOSFETs have relatively large manufacturing variations, and can be divided into those having relatively large threshold voltages Vth as a result of manufacture and those having relatively small threshold voltages. As described above, based on the above-mentioned characteristics due to the manufacturing variation, the judgment is made based on the Vth production amount at the time of manufacturing.
  • LSI at low Vth activates the substrate bias circuit and applies the optimum bias value.
  • LSIs with high Vth stop the activation of the substrate bias circuit or apply a shallow substrate bias.
  • FIG. 6 is a characteristic diagram illustrating the relationship between the threshold voltage of M ⁇ S FET and the standby current for explaining the present invention.
  • the relationship between the standby current and the threshold voltage is the same when the ambient temperature is high RTH and room temperature RTL.
  • the current is controlled by the temperature as follows.
  • the mode switching points for substrate bias off and substrate bias on which have the effect of reducing standby current, are A region for substrate bias on and B region for substrate bias off at high temperature RTH.
  • the substrate bias is in the C region and the substrate bias is in the D region.
  • the current worst is the high temperature RTH side.
  • Set the mode switching point to Vth 0.15 V.
  • the standby current can be minimized by controlling the standby current with or without the application of the substrate bias and by appropriately controlling the depth of the substrate bias. Further, by monitoring the above temperature and switching between the substrate bias off and the substrate bias on, the standby current can be further optimized.
  • the substrate bias on current becomes smaller than the substrate noise off current, and the substrate bias off is maintained even in the current setting of the substrate bias off in the room temperature region where the minimum stun current occurs.
  • the substrate bias off current is smaller than the substrate noison current, and a minimum standby current state is obtained.
  • set values are as follows.
  • write information "1" of a flash memory used as a program element ⁇
  • the substrate bias voltage is turned off during standby.
  • the write information of the program element “0” similar to the above is turned on ⁇ the substrate bias voltage is turned on during standby.
  • the substrate bias generating circuit forms an output voltage for fixing the n-type p-type substrate to Vdd and the p-type p-type substrate to Vss at high Vth based on the information stored in the program element.
  • the circuit configuration is switched so that a voltage higher than Vd is applied to the n-type cell substrate and a voltage lower than Vss is applied to the p-type cell substrate.
  • a voltage higher than Vd is applied to the n-type cell substrate and a voltage lower than Vss is applied to the p-type cell substrate.
  • the ON / OFF control of the board VBB may be supplied digitally as a predetermined fixed value so that the sun current becomes low level, or based on the monitoring of the actual Vth value and the temperature monitor.
  • the depth of the substrate bias may be variably controlled.
  • the function of the substrate bias generation circuit is stopped and the current consumed by the substrate bias is cut. This is useful for reducing the standby current of LSI of single Vth or multi Vth specification.
  • the variation in the standby current value due to the process yield can be suppressed by controlling the depth level of the substrate ground.
  • setting whether or not to use the LSI substrate bias voltage imprinting 0 function (active or not) can reduce the standby current.
  • FIG. 7 shows a flowchart of one embodiment of a data writing method for setting a substrate bias.
  • a data writing method for setting a substrate bias based on the W (wafer) detection and measurement results (Vth value) of a device such as a MOS device, there is an example in which a substrate bias VBB is applied or not, and a high level or a low level of the VBB depth is set. It is shown.
  • This embodiment is a part of the W (wafer) inspection or the P (lobe) inspection.
  • the Vth value is determined by W detection or F detection, etc.
  • the data programming element corresponding to each bit be a device that can be implemented in the inspection process.
  • the program element has a single-layer gate structure using only one-layer polysilicon, which is a normal gate for the purpose of matching the logic LSI process.
  • two memory cells two memory cells are connected in parallel to store one bit, and even if one of them has a storage failure, the stored information from the other is made valid to improve reliability.
  • step (2) the same or the same write data is written to the above two cells in step (3) by using the ones that have been tested and passed the program element.
  • step (4) in order to further maintain the reliability of the write data, the write data is used with an ECC (Error Correct Code) function. That is, a parity bit for performing error detection and correction is generated in the write data, and the parity bit is written in correspondence with the write data.
  • ECC Error Correct Code
  • data writing is performed as follows.
  • Vth 0.000 V-0.25 V
  • V FLAG 1
  • Substrate bias on 0.1 1 1 -0.25 V FLAG 0
  • Vth range D region ⁇ region C region ⁇ region From the above, a low level standby current can always be ensured by controlling the operation of the substrate bias circuit based on the measured Vth value and by monitoring the temperature.
  • the tendency of the standby current is defined by the room temperature RTL. However, the tendency is the same even at lower temperatures. Therefore, when controlling the temperature over a wide range from low to high, consider this extension.
  • the temperature worst is defined as RTH (for example, 85 ° C)
  • activation and activation of the substrate bias circuit is performed by an electrically writable program element such as a flash memory or EPR ⁇ M, but the bonding option method, laser haze, etc., which are conventionally known techniques, have been described. Configurable.
  • FIG. 8 is a block diagram of one embodiment of the substrate bias generating circuit according to the present invention.
  • the figure is directed to a fixed mode type with the substrate bias fixed on / off.
  • the control data such as the presence / absence of the substrate bias application and the setting of the bias level are written in advance in the seventh flow, for example, and activated by the activation of the external signal ST or the internal power-on signal PON.
  • Select whether or not to apply the substrate bias voltage substrate bias VBP for p-type well and substrate bias VBN for n-type well
  • the switch for setting the substrate bias voltage to ON or the substrate bias voltage to OFF is switched by W (wafer) inspection by a program such as a flash memory.
  • Result Based on the evening (measurement result of Vth), the setting is instructed by a tester or the like.
  • Vth When the actual measurement result of Vth is low Vth, it is set to "0", VBP is higher than Vdd on the n-type plug substrate, and VB N is lower than Vss (0 v) on the p-type plug substrate (negative voltage ) Is applied.
  • the bias voltage is set to the optimal VBN and VBP values. That is, the bias voltage VBP and VBN are optimally set by the output level trimming circuit so as to compensate for the process variation.
  • a bias voltage corresponding to the above point A is supplied to the P-channel MOSFET. In other words, a bias voltage that minimizes the standby current is output.
  • FIG. 9 is a block diagram showing another embodiment of the substrate bias generation circuit according to the present invention.
  • a function for automatically controlling the operation of the substrate bias generation circuit is added.
  • a monitor such as a temperature sensor and a threshold sensor is provided, and a circuit for adjusting a substrate bias level is also provided.
  • the operation mode setting of the substrate bias on or the substrate bias off is performed, and the activation ON / OFF of the oscillation circuit SC or the activation ON / OFF of the boost / negative voltage circuit is changed depending on the environment (temperature, Vth, etc.).
  • the output level of VBN and VBP values can also be switched automatically.
  • the standby current of an LSI with multi-Vth specifications has a single MOS characteristic.
  • Control based on the following procedure.
  • the mode setting for standby operation is set in the following modes 1-3 based on the wafer characteristics (Vth of MOSFET, etc.) of the lot obtained from the scribe TEG.
  • the setting conditions are monitored (Vth or temperature Ta is sensed), and the presence / absence of substrate bias VBB (VBP, VBN) and the high side or low side of VBB (VBP, VBN) depth are trimmed by a trimming circuit. Make settings. According to these settings, self-control is performed automatically to maintain the minimum standby current I s b value.
  • the substrate noise when the substrate noise is set to a mode in which the substrate noise voltage is increased to increase Vth, and when the substrate bias is set to the When the potential (for example, Vth) or current (for example, leakage) level is detected, the mode shifts to the substrate zone-on or substrate-off operation mode. Alternatively, when a level lower than the predetermined value is detected, the transition is made in reverse.
  • FIG. 10 is a circuit diagram showing one embodiment of a negative voltage generating charge pump circuit used in the present invention.
  • this embodiment although not particularly limited, it is configured using P-channel MOSFETs Q59 to Q66. These P-channel MOSFETs are formed in the n-type well region
  • Capacitor C13 and MOSFETQ formed using MOS capacitance 6 1 and Q63 constitute the basic circuit of the bombing circuit that generates the negative voltage VBB.
  • the capacitor C14 and the MOSFETs Q62 and Q64 are the same basic circuit, but the input pulses 0SC and 0SCB are in an anti-phase relationship so that their active levels do not overlap each other. Corresponding alternate operations are performed to perform an efficient charge pump operation.
  • the MOSFETs Q61 and Q63 may be basically in the form of a diode, but this causes a level loss corresponding to the threshold voltage.
  • the high level of the pulse signal ⁇ SC is a low voltage such as 3.3 V, it does not substantially operate. Therefore, focusing on the fact that the MOSFET Q61 is only required to be turned on when the input pulse ⁇ ⁇ SC is at the low level, the inverter circuit N10 and the capacitor C11, which form a pulse similar to the input pulse, are formed.
  • a switch MOSFETQ59 is provided to form a negative control voltage.
  • the MOSFE TQ 59 is turned on when a negative voltage is formed by the other input pulse 0 S CB, and charges up the capacitor C 11.
  • the capacity C 11 is small enough to form the control voltage of the MOSFET Q61.
  • the MOSFET Q63 is turned off at an early timing by receiving a high-level output signal of the driving circuit N13, which receives the other input pulse ⁇ SCB at the back gate (channel portion). Efficient extraction of potential. Similarly, the output signal of the driving inverter circuit N12 is supplied to the back gate of the MOSFET Q61, so that when the capacitor C13 is charged up, the MOSFET Q61 is charged.
  • the other input pulse The control voltage supplied to the gate of M0SFET Q62 corresponding to OSCB, the back gate voltage of MOSFETs Q64 and Q62, and the pulse formed by inverter circuit N13 and capacitor C14 that perform the same operation A pulse signal formed based on the signal and the input pulse ⁇ SC is used.
  • the MOSFETQ59 and Q63 are provided with MOSFETQ65 (Q66) that pull out the gate voltage at an early timing.
  • the MOSFET Q65 (Q66) has a gate and a drain connected in common to form a diode, and has its back gate receiving its own input pulse OSC (OSCB). Is supplied, the switch is controlled in a complementary manner to the MOSFET Q63 (Q64). This allows the MOSFET Q63 (Q64) to switch from the on state to the off state when the output signal of the drive inverter circuit N12 (N13) changes to the gate level according to the input pulse OSC (OSCB). Since the switching can be performed quickly, the substrate potential can be efficiently extracted to the negative potential.
  • OSCB input pulse OSC
  • FIG. 11 is a circuit diagram of an embodiment of an oscillation circuit for forming an oscillation pulse supplied to the charge pump circuit.
  • an oscillation circuit for forming an oscillation pulse supplied to the charge pump circuit.
  • a P-channel MOSFET Q67 and an N-channel MOSFET Q69 acting as resistive elements are connected in series to the P-channel MOSFET Q67 and N-channel MOSFET Q70 that make up the CMOS inverter circuit, respectively, and together with the input capacitance of the next stage CM ⁇ S inverter circuit. Configure a time constant circuit to delay the signal.
  • An odd number (5 in this figure) of these CMOS inverter circuits are connected in cascade to form a ring oscillator. In order to operate these ring oscillators intermittently, in other words, the substrate voltage VBB (VBN) is set to the desired negative voltage (about 1.0 V).
  • the signal DETA is a signal formed by a level sensor described below, and is set to a low level when it is determined that the substrate voltage VBB has reached a desired potential. Due to the low level of this signal DET A, the output signal passing through the inverter circuit N15 and N16 becomes low level, and is provided in the final stage CM ⁇ S inverter circuit constituting the ring oscillator, and has a resistance element. Turn off the N-channel MOSFET acting as a transistor, and turn on the P-channel M ⁇ SFET provided at its output terminal, forcing the final-stage output to a high level.
  • the outputs of the gate circuits G 1 and G 2 are set to the high level, the output signal of the gate circuit G 3 is set to the low level, the oscillation pulse 0 SC is fixed to the low level, and the oscillation pulse OSCB is fixed to the high level.
  • the signal V BOSCS W is a signal that is set to a high level when, for example, the dynamic memory is in the standby state.
  • the gate circuit G 1 closes the gate and the gate circuit G 1 according to the high level of the signal VBOSC SW. Open G2 and replace the relatively high frequency formed by the ring oscillator with the oscillation pulse SL ⁇ SC for the built-in self-refresh timer provided in the dynamic memory to the charge pump circuit. Oscillation pulse ⁇ SC, OSCB. Even in the operation of the charge pump circuit at such a low frequency, the gate pulse of the signal DETA causes the gate G2 to close the gate and the oscillation pulse OSC to the low level, and the oscillation pulse ⁇ SCB to the low level. It is fixed at a high level. .
  • FIG. 12 is a circuit diagram showing one embodiment of the level sensor circuit for the negative voltage VBB (VBN).
  • Constant voltage VR EF 0 is gate and source
  • a constant current is formed by the N-channel MOSFET Q72 applied therebetween, and a reference current i1 is formed by a current mirror circuit based on the constant current.
  • a substrate voltage VBB is supplied by connecting a plurality of N-channel M ⁇ SFETs in series in the current path.
  • the above-mentioned plurality of series MOSFETs are provided with terminals for adjustment, and are used for adjusting device process variations. That is, when the substrate voltage VBB is 1.1 V as described above, the trimming adjustment is performed so that the current i 2 flowing through the series MOSFET is balanced with the current i 1.
  • the balance between the current i1 flowing through the MOSFETQ76 and the above current i1 is adjusted so that the source potential of the MOSFETQ76 matches the ground potential VSS.
  • Two M ⁇ SFE TQ73 and Q74 are also connected in series to the N-channel type current mirror circuit to enable the adjustment of the reference current i1 as described above, and a selective short circuit between source and drain, that is, The mirror current ratio is also adjusted by the trimming as described above.
  • the source potential of the MOSFET Q76 becomes higher than the ground potential so that the current i2 ⁇ i1.
  • no current flows through the P-channel type M ⁇ SF ET Q77 provided in parallel with the P-channel MOSFET Q76 through which the reference current i 1 flows, and an N-channel type through which a current corresponding to the current i 1 flows Voltage vs is set to low level in accordance with the current difference from MOSFET Q78.
  • This low-level signal Vs is amplified by a CMOS inverter circuit composed of M ⁇ SFETs Q68 to Q71, and further output as a sense output DETA through an inverter circuit and a gate circuit G4.
  • the level judgment by the CM 0 S inverter circuit has a hysteresis characteristic.
  • the intermittent operation of the oscillation circuit can be stably controlled, and the substrate voltage VBB can be set stably with respect to the set value.
  • the signal S ETB is a signal which is temporarily set to a high level immediately after the power is turned on.
  • the high level of the signal SETB forcibly sets the sense output DETA to the high level to start the oscillation circuit.
  • the voltage VSN or VSP is used as a bias voltage for operating with low current consumption, such as a CM ⁇ S circuit circuit for determining the high level / input level of the voltage Vs.
  • FIG. 13 is a block diagram of still another embodiment of the substrate bias generating circuit according to the present invention.
  • This figure shows an example in which the setting of the substrate bias-on and the substrate bias-off mode is switched based on the result of monitoring the gate-off (standby) current of the MOSFET.
  • the leak current monitor circuit shifts to the substrate no-off mode even in the substrate bias-on mode, stops the oscillation circuit 0 SC, etc., and stops the It works to suppress or stop the generation level.
  • the output level trimming circuit gives the optimum bias value to minimize the standby current value. I can.
  • the Vdd leakage current corresponding to the noise voltages VBP and VBN is monitored, and the oscillation circuit, the booster circuit, and the negative voltage circuit are operated based on the result, and the minimum voltage is changed by changing the bias voltages VBP and VBN. It is controlled to be a value.
  • FIG. 14 is a block diagram showing an embodiment of a Vdd leak current monitor circuit used in the embodiment of FIG.
  • the circuit is configured.
  • the potential VC of the capacitor C is lower than the logic threshold voltage of the inverter circuit N1
  • the output signal S1 becomes high level
  • the signal S2 becomes high level through the delay circuit DLY
  • the switch SW is turned on.
  • the capacitor C is charged up by the power supply voltage VDD (or VCC).
  • VDD power supply voltage
  • the charge-up causes the voltage VC to rise and exceeds the logic threshold voltage of the inverter circuit N1
  • the output signal S1 changes from high level to low level
  • the signal S2 is delayed by the delay circuit DLY.
  • To a low level and the switch SW is turned off.
  • the M ⁇ SFET QM for monitoring is shown as one element, but is constituted by a plurality of M ⁇ SFETs connected in parallel to represent a large number of MO SFETs formed in the semiconductor integrated circuit device. Is done. This makes it possible to monitor an average leakage current that is not affected by process variations.
  • the comparison circuit CMP compares the count value A of the count CNT with the count result B of the previous cycle held in the register REG '. Until A> B, the substrate bias generation circuit VBN-G is operated to control the substrate bias voltage VBN to be deep. When the result of the determination becomes A> B, it is determined that the substrate bias has become deeper than the minimum point of the characteristic shown in FIG. 1, and the operation of the substrate bias voltage VBN-G is stopped. And this is flip-flop. Etc., and invert the judgment result of the comparator.
  • the characteristic where the determination result is A> B is the characteristic on the right side of point A (point B) in FIG. 1, so the operation of the substrate bias voltage VBN-G is continuously stopped by B> A. It is necessary.
  • the operation of the substrate bias voltage VBNG is performed to increase the substrate bias voltage VBN.
  • the substrate bias voltage V BN-G is stopped and the substrate bias voltage VBN is controlled to be shallow.
  • the advantage of presetting whether to use the substrate bias as the on mode or the off mode for the chip, wafer, or product is when there is a product that does not want to apply the substrate bias in the AS IC, and the tolerance of Vth is wide It is effective in the case.
  • the advantage of providing a temperature / process (Vth) sensor is that it is not necessary to reflect an actual measurement value such as Vth at the time of inspection / probe inspection, so that the test time involved in the setting can be reduced.
  • the present invention can extend the battery life by reducing the standby current when it is operated by the battery voltage. Therefore, it is useful for various semiconductor integrated circuit devices that constitute PDA, mobile phone, digital camera, and AS IC in notebook PC. Industrial applicability
  • the present invention provides a semiconductor integrated circuit device capable of reducing a leakage current (DC current) during standby, such as a PDA operated by a battery voltage, a mobile phone, a digital camera, an AS IC in a notebook PC, and the like. It can be widely used for various semiconductor integrated circuit devices that need to reduce leakage current.
  • DC current leakage current

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  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

La présente invention concerne un circuit MOS dans lequel se produisent un courant de fuite de canal décroissant en proportion inverse à une tension de polarisation de substrat et un courant de fuite de jonction augmentant proportionnellement à la tension de polarisation du substrat, lequel circuit possède un mode actif dans lequel le circuit MOS effectue une opération de circuit désirée et un mode d'attente dans lequel le circuit MOS arrête l'opération du circuit. Un circuit de polarisation de substrat produit une tension de polarisation de substrat qu'il transmet au circuit MOS de façon que la région peut être celle où le courant de fuite total représentant la somme du courant de fuite de canal et du courant de fuite de jonction se trouve réduit à un minimum en mode d'attente.
PCT/JP2002/004323 2002-04-30 2002-04-30 Dispositif de circuit integre a semiconducteur WO2003094235A1 (fr)

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JP2004502355A JPWO2003094235A1 (ja) 2002-04-30 2002-04-30 半導体集積回路装置
PCT/JP2002/004323 WO2003094235A1 (fr) 2002-04-30 2002-04-30 Dispositif de circuit integre a semiconducteur
TW091116172A TW595007B (en) 2002-04-30 2002-07-19 Semiconductor integrated circuit device

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Cited By (12)

* Cited by examiner, † Cited by third party
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JP2005197411A (ja) * 2004-01-06 2005-07-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JP2007281934A (ja) * 2006-04-07 2007-10-25 Nec Electronics Corp 半導体リレー
JP2008085571A (ja) * 2006-09-27 2008-04-10 Nec Electronics Corp 半導体集積回路
WO2008047416A1 (fr) * 2006-10-18 2008-04-24 Spansion Llc Circuit de détection de tension
JP2009231360A (ja) * 2008-03-19 2009-10-08 Fujitsu Ltd 半導体装置
JP2009537103A (ja) * 2006-06-30 2009-10-22 インテル・コーポレーション 漏れ電力推定
JP2009295225A (ja) * 2008-06-04 2009-12-17 Toppan Printing Co Ltd ディレイパルス発生回路、および半導体記憶装置
WO2010146640A1 (fr) * 2009-06-15 2010-12-23 パナソニック株式会社 Dispositif de circuit intégré à semi-conducteurs et équipement électrique
US8008659B2 (en) 2004-11-01 2011-08-30 Nec Corporation Semiconductor integrated circuit device
CN102280653A (zh) * 2010-06-14 2011-12-14 Sb锂摩托有限公司 可再充电电池
WO2015177982A1 (fr) * 2014-05-19 2015-11-26 ソニー株式会社 Dispositif à semi-conducteur et procédé de commande de transistor mos
US9246155B2 (en) 2009-12-07 2016-01-26 Samsung Sdi Co., Ltd. Rechargeable secondary battery having improved safety against puncture and collapse

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JPH02199863A (ja) * 1989-01-30 1990-08-08 Nec Corp 半導体装置
US6046627A (en) * 1997-02-28 2000-04-04 Hitachi, Ltd. Semiconductor device capable of operating stably with reduced power consumption
JP2000223586A (ja) * 1999-02-02 2000-08-11 Oki Micro Design Co Ltd 半導体集積回路
JP2001332625A (ja) * 2000-05-19 2001-11-30 Hitachi Ltd 半導体集積回路

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Publication number Priority date Publication date Assignee Title
JPS5989031A (ja) * 1982-11-12 1984-05-23 Toshiba Corp 基板バイアス発生回路
JPH02199863A (ja) * 1989-01-30 1990-08-08 Nec Corp 半導体装置
US6046627A (en) * 1997-02-28 2000-04-04 Hitachi, Ltd. Semiconductor device capable of operating stably with reduced power consumption
JP2000223586A (ja) * 1999-02-02 2000-08-11 Oki Micro Design Co Ltd 半導体集積回路
JP2001332625A (ja) * 2000-05-19 2001-11-30 Hitachi Ltd 半導体集積回路

Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005197411A (ja) * 2004-01-06 2005-07-21 Matsushita Electric Ind Co Ltd 半導体集積回路装置
JP4744807B2 (ja) * 2004-01-06 2011-08-10 パナソニック株式会社 半導体集積回路装置
US8008659B2 (en) 2004-11-01 2011-08-30 Nec Corporation Semiconductor integrated circuit device
JP2007281934A (ja) * 2006-04-07 2007-10-25 Nec Electronics Corp 半導体リレー
JP2009537103A (ja) * 2006-06-30 2009-10-22 インテル・コーポレーション 漏れ電力推定
JP2008085571A (ja) * 2006-09-27 2008-04-10 Nec Electronics Corp 半導体集積回路
WO2008047416A1 (fr) * 2006-10-18 2008-04-24 Spansion Llc Circuit de détection de tension
US7605616B2 (en) 2006-10-18 2009-10-20 Spansion Llc Voltage detector circuit
JP2009231360A (ja) * 2008-03-19 2009-10-08 Fujitsu Ltd 半導体装置
JP2009295225A (ja) * 2008-06-04 2009-12-17 Toppan Printing Co Ltd ディレイパルス発生回路、および半導体記憶装置
WO2010146640A1 (fr) * 2009-06-15 2010-12-23 パナソニック株式会社 Dispositif de circuit intégré à semi-conducteurs et équipement électrique
JP5195915B2 (ja) * 2009-06-15 2013-05-15 パナソニック株式会社 半導体集積回路装置及び電子機器
US9246155B2 (en) 2009-12-07 2016-01-26 Samsung Sdi Co., Ltd. Rechargeable secondary battery having improved safety against puncture and collapse
CN102280653A (zh) * 2010-06-14 2011-12-14 Sb锂摩托有限公司 可再充电电池
CN102280653B (zh) * 2010-06-14 2014-03-12 三星Sdi株式会社 可再充电电池
WO2015177982A1 (fr) * 2014-05-19 2015-11-26 ソニー株式会社 Dispositif à semi-conducteur et procédé de commande de transistor mos
US10263622B2 (en) 2014-05-19 2019-04-16 Sony Semiconductor Solutions Corporation Semiconductor apparatus and method of controlling MOS transistor

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