JP6081171B2 - 記憶装置 - Google Patents

記憶装置 Download PDF

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Publication number
JP6081171B2
JP6081171B2 JP2012265958A JP2012265958A JP6081171B2 JP 6081171 B2 JP6081171 B2 JP 6081171B2 JP 2012265958 A JP2012265958 A JP 2012265958A JP 2012265958 A JP2012265958 A JP 2012265958A JP 6081171 B2 JP6081171 B2 JP 6081171B2
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JP
Japan
Prior art keywords
memory cell
cell array
bit line
film
word line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2012265958A
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English (en)
Japanese (ja)
Other versions
JP2013168631A5 (enExample
JP2013168631A (ja
Inventor
熱海 知昭
知昭 熱海
高 奥田
高 奥田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
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Semiconductor Energy Laboratory Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP2012265958A priority Critical patent/JP6081171B2/ja
Publication of JP2013168631A publication Critical patent/JP2013168631A/ja
Publication of JP2013168631A5 publication Critical patent/JP2013168631A5/ja
Application granted granted Critical
Publication of JP6081171B2 publication Critical patent/JP6081171B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/08Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/24Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using capacitors
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/404Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with one charge-transfer gate, e.g. MOS transistor, per cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409Read-write [R-W] circuits 
    • G11C11/4097Bit-line organisation, e.g. bit-line layout, folded bit lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/50Peripheral circuit region structures
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/421Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer
    • H10D86/423Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs having a particular composition, shape or crystalline structure of the active layer comprising semiconductor materials not belonging to the Group IV, e.g. InGaZnO
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/40Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
    • H10D86/60Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/10Integrated device layouts

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Dram (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • General Engineering & Computer Science (AREA)
JP2012265958A 2011-12-09 2012-12-05 記憶装置 Expired - Fee Related JP6081171B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012265958A JP6081171B2 (ja) 2011-12-09 2012-12-05 記憶装置

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP2011269712 2011-12-09
JP2011269712 2011-12-09
JP2012009731 2012-01-20
JP2012009731 2012-01-20
JP2012265958A JP6081171B2 (ja) 2011-12-09 2012-12-05 記憶装置

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2017006307A Division JP2017118118A (ja) 2011-12-09 2017-01-18 半導体装置及びその作製方法

Publications (3)

Publication Number Publication Date
JP2013168631A JP2013168631A (ja) 2013-08-29
JP2013168631A5 JP2013168631A5 (enExample) 2016-01-14
JP6081171B2 true JP6081171B2 (ja) 2017-02-15

Family

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Family Applications (4)

Application Number Title Priority Date Filing Date
JP2012265958A Expired - Fee Related JP6081171B2 (ja) 2011-12-09 2012-12-05 記憶装置
JP2017006307A Withdrawn JP2017118118A (ja) 2011-12-09 2017-01-18 半導体装置及びその作製方法
JP2018132334A Active JP6611870B2 (ja) 2011-12-09 2018-07-12 半導体装置
JP2019196265A Withdrawn JP2020036033A (ja) 2011-12-09 2019-10-29 半導体装置

Family Applications After (3)

Application Number Title Priority Date Filing Date
JP2017006307A Withdrawn JP2017118118A (ja) 2011-12-09 2017-01-18 半導体装置及びその作製方法
JP2018132334A Active JP6611870B2 (ja) 2011-12-09 2018-07-12 半導体装置
JP2019196265A Withdrawn JP2020036033A (ja) 2011-12-09 2019-10-29 半導体装置

Country Status (2)

Country Link
US (1) US9076505B2 (enExample)
JP (4) JP6081171B2 (enExample)

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US9887212B2 (en) * 2014-03-14 2018-02-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and electronic device
TWI767772B (zh) 2014-04-10 2022-06-11 日商半導體能源研究所股份有限公司 記憶體裝置及半導體裝置
JP6635670B2 (ja) 2014-04-11 2020-01-29 株式会社半導体エネルギー研究所 半導体装置
WO2015170220A1 (en) 2014-05-09 2015-11-12 Semiconductor Energy Laboratory Co., Ltd. Memory device and electronic device
JP6580863B2 (ja) 2014-05-22 2019-09-25 株式会社半導体エネルギー研究所 半導体装置、健康管理システム
JP6616102B2 (ja) 2014-05-23 2019-12-04 株式会社半導体エネルギー研究所 記憶装置及び電子機器
US9312280B2 (en) 2014-07-25 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
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JP6734263B2 (ja) * 2015-04-27 2020-08-05 ソニーセミコンダクタソリューションズ株式会社 メモリシステム
WO2016181256A1 (ja) * 2015-05-12 2016-11-17 株式会社半導体エネルギー研究所 半導体装置、電子部品および電子機器
US9847406B2 (en) 2015-08-27 2017-12-19 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, storage device, resistor circuit, display device, and electronic device
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JP6811084B2 (ja) 2015-12-18 2021-01-13 株式会社半導体エネルギー研究所 半導体装置
KR102613318B1 (ko) 2015-12-28 2023-12-14 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
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JPWO2017158465A1 (ja) * 2016-03-18 2019-02-14 株式会社半導体エネルギー研究所 記憶装置
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US10347333B2 (en) 2017-02-16 2019-07-09 Micron Technology, Inc. Efficient utilization of memory die area
US9792958B1 (en) * 2017-02-16 2017-10-17 Micron Technology, Inc. Active boundary quilt architecture memory
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