JP2014515955A - 内視鏡用の改良型画像センサ - Google Patents
内視鏡用の改良型画像センサ Download PDFInfo
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- JP2014515955A JP2014515955A JP2014510550A JP2014510550A JP2014515955A JP 2014515955 A JP2014515955 A JP 2014515955A JP 2014510550 A JP2014510550 A JP 2014510550A JP 2014510550 A JP2014510550 A JP 2014510550A JP 2014515955 A JP2014515955 A JP 2014515955A
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Abstract
Description
・交互の相互接続、すなわち、相互接続の冗長性を与える能力が増大されることにより製造信頼性を改善すること。
・応用または使用分野ごとに費用効率性が高いやり方でバンプピッチサイズを最大化すること。
・より大きい画素ピッチを使用する能力により、より経済的なCMOSプロセスを可能にすること。
・より効率的なバンプ技術のアクセス、すなわち複数のバスからのデータ読み出しまたは画素配列から直接のデータ読み出しを可能にすること。
・CMOSプロセスの冗長性が歩留まりを改善することを可能にすること。
・所定または一定の画素領域における局所的なADCを使用すること。
・複数の画素配列の幾何学的形状、複数のバスおよび列バンプ構成が利用されることを可能にすること。
反対に、本明細書中で言及されるとき、回路列356は、画素配列350を含む第1の基板310ではない基板上に割り当てられた空間であり、これは対応する画素列352に専用であり、対応する画素列352に電気的に接続されるまたは電気通信する少なくとも1つの支援回路370を含む。画素列352によって占められる空間は、画素列352と対応する回路列356によって占められる空間と同じまたはほぼ同じにできることが理解されよう。このようにして、第2の基板または支持用基板311は、複数の回路列356を備えることができ、各回路列356は、対応する画素列352が第1の基板310上に領域を有するのと実質的に同一または類似の占有面積の領域を第2の基板311上に備える。
そのような構成では、画素列352のアスペクト比は、回路列356のアスペクト比にほぼ等しくなるが、さらに以下に述べられるように、そのようなアスペクト比の等しさは必要とされないことにも留意されたい。図3mに見られるように、画素列は、1つの画素列の幅および6画素の長さであり、したがってアスペクト比は1/6である。回路列も、同じ1/6のアスペクト比を有する。対照的に、図3nは、回路列のアスペクト比が画素列のアスペクト比の2倍の幅であるが、たった半分の長さであり、それによって支援用回路を配置するために使用可能な実装面積をできる限りより多く与える設計を示す。図3mおよび図3nでは共に、画素列352と回路列356の両方の実装面積の領域は、アスペクト比が異なっているとしても、互いにほぼ等しい。
図3yは、間に電気的接続を示す図3uの最右列356の左側への最右列356に隣接した列からとった画素の単一の列352および回路の単一の列356の斜視図を示す。図3zは、間に電気的接続を示す図3yからとった画素の単一の列352および回路の単一の列356の正面図を示す。図3vおよび図3yは、図3uの画素配列350からとった画素列352を示す。図3vおよび図3yは、回路列356の実装面積内の相互接続321の配置についての2つのオプションを示す。図3aaに示されるように、回路列のアスペクト比はより広いが、対応する画素列352のアスペクト比より短いので、相互接続位置のオプションは、画素列352の長さの一部に利用できるだけであることに留意されたい。図3zは、複雑なバス形状の場合、それが支持する画素列352の4倍の幅および4分の1の長さを有する回路列356内のバス340に沿って4つの相互接続位置経路のオプションが存在できることを示す。したがって、回路列356のアスペクト比は画素列352のアスペクト比とは異なるが、それぞれの実装面積の領域が、ほぼ同じであり、すなわち等しいことが見られる。製造技法が改善されるまたは設計パラメータが変更されると、多かれ少なかれ領域が、回路列356の支援用回路のために必要とされ得る。
一実施形態では、画素配列を含む基板510は、画素配列を含む基板に対して遠隔に設置される支持基板520に隣接しているまたはその近くにあることができる。支持基板520は、その上に増幅器回路を備えることができ、一方、他の支援用回路は、支持基板520が画素配列基板510から離れて設置される距離よりも画素配列基板510から離れている距離で別の基板530a上により遠隔に設置することができる。一実施形態では、より遠隔に設置された基板530は、配線ビア522によって画像センサ500内の他の基板に接続することができ、または他の基板および回路と無線で通信することができる。隣接した基板同士は、バンプまたははんだボール521によって互いに接続することができる。画素配列および他の回路が徐々により効率的になるにつれて、画素配列を含む基板が全ての他の支援回路からより遠隔である画像センサを提供することが、本開示の範囲内である。そのような回路は、図10に示されており、画素配列を含む基板1010は、信号処理回路および電力回路などの支援回路をそれぞれが備える支持基板1020、1030、1040からビア1022によってより遠隔に設置される。
主に図16を参照すると、内部にリードバス構成を有する多重基板の画像センサ1600が示される。図に見られるように、基板1652は、画素配列1610を含むことができ、複数の画素列リードバスを通じて支持基板1654および1656に電気的に接続することができ、画像センサの構造は、1つまたは複数の続く基板1654および1656上に支援回路を設置することによって大いに単純化することができる。続く基板1654および1656は、第1の基板1652に近接するが、第1の基板1652の背後にあることができる。支援回路1622および1663は、例示されるように、垂直構成で基板を積み重ねることを可能にするために、続く基板1654および1656上に配置することができる。貫通基板ビアが使用されて、複数の基板のいずれかを通じて前から後ろへの通信を可能にすることができる。積層時の第2の基板1654は、第1の基板1652上に位置する画素列1650に対して専用にされる二次回路であって、それらと電気的に接続される二次回路を備えることができる。第3の基板1654は、第2の基板上の支援回路1622に対して専用にされ得る追加のデータ処理回路1663を備えることができ、第2の基板から複数の支援回路からのデータを処理することになっていてもよい。第3の基板1656上の回路1663は、第1の基板1652上の特定の画素列1650に対して専用にすることができ、または複数の画素列1650からのデータの処理に対して専用にすることができることに留意されたい。言い換えれば、第3の基板1656上に位置する回路1663は、第2の基板1654上の特定の回路1622、または第1の基板1652上の特定の画素列1650に直接対応することができる。各基板が、全基板上の回路を電気的に接続する少なくとも1つのバスを備えることができることに留意されたい。したがって、基板の各々のバス1623a〜1623cは、基板同士の間に配設された相互接続1621によって、バス1623a〜1623c間の電気的接続を引き起こすように重ね合わせることができる。
したがって、画素列リードバス2430は、対応する画素サブ列リードバス2430aおよび2430bに製造することができる。各画素サブ列2487、2488は、まず画素列バス2430aまたは2430bに接続され、次いで支援用回路2470および回路列2456に接続することができ、または各サブ列2487、2488はそれぞれ、関連した回路バス2440aおよび2440bへのそれら自体の相互接続2424aおよび2424bを介して、回路2470および回路列2456に直接接続することができる。
したがって、画素列リードバス2630は、対応する画素サブ列リードバス2630aおよび2630bに製造することができる。各画素サブ列2687、2688は、まず画素列バス2630aまたは2630bに接続され、次いで支援用回路2670および回路列2656に接続することができ、または各サブ列2687、2688はそれぞれ、関連した回路バス2640aおよび2640bへのそれら自体の相互接続2624aおよび2624bを介して、回路2670および回路列2656に直接接続することができる。
したがって、2つの支援用回路および回路列のリードバス(画素サブ列リードバス当たり1つの支援回路および回路列バス)もあり、この構成では、回路列のアスペクト比は3/2、画素サブ列のアスペクト比はやはり6/1、および画素列全体のアスペクト比が12/1である。
Claims (37)
- 管腔(lumen)と、
前記管腔の遠位端(distal tip)の近くに配設される撮像センサと
を備える内視鏡装置であって、
前記撮像センサが、
少なくとも第1の基板および第2の基板を備える複数の基板と、
前記第1の基板上に位置すると共に複数の画素列(pixel columns)を備える画素配列であって、前記複数の画素列の各々が、幅(in width)1画素および長さ(in length)複数画素として定められる、画素配列(pixel array)と、
前記第2の基板上に位置すると共に複数の回路列(circuit columns)を備える複数の支援用回路であって、1つの回路列が1つの画素列に対応し、前記複数の回路列の各々が、対応する画素列の領域と対応する領域(area)を有するものとして定められる、支援用回路(supporting circuits)と、
前記第1の基板上に存在する少なくとも1つの画素列当たり1つの画素列バス(pixel column bus)、および前記第2の基板上に存在する回路列当たり1つの回路列バス(circuit column bus)が存在する複数のバスと
を備え、
前記画素列バスの各々の少なくとも一部が、対応する回路列バスの各々の少なくとも一部と重ね合わされ(superimposed)、少なくとも1つの相互接続(interconnect)が1つの画素列バスと対応する1つの回路列バスの間の電気通信(electrical communication)を与え、
前記少なくとも1つの相互接続が、1つの画素列バスと対応する1つの回路列バスの間のどこか(anywhere)に設置され、互いに対して(with respect to each other)重ね合わされる、内視鏡(endoscopic)装置。 - 前記基板同士の間に配設される複数の相互接続をさらに備え、前記複数の相互接続が前記画素配列の画素ピッチより大きい距離で互いに対して間隔をおいて(spaced)配置される、請求項1に記載の内視鏡。
- 前記第1の基板および前記第2の基板が、揃った状態(in alignment)である、請求項1に記載の内視鏡。
- 前記第1の基板上の前記画素列のうちの1つの領域(area)が、前記第2の基板上の前記対応する回路列のうちの1つの領域とほぼ等しい、請求項1に記載の内視鏡。
- 前記第2の基板が、前記第1の基板とほぼ同じサイズである、請求項1に記載の内視鏡。
- 前記第1の基板上の前記画素列のうちの1つの領域が、前記第2の基板上の前記対応する回路列のうちの1つの領域より大きい、請求項1に記載の内視鏡。
- 前記第1の基板上の前記画素列のうちの1つの領域が、前記第2の基板上の前記対応する回路列のうちの1つの領域より小さい、請求項1に記載の内視鏡。
- 前記画素列のうちの1つのアスペクト比が、前記回路列のうちの1つのアスペクト比とほぼ同様である、請求項1に記載の内視鏡。
- 複数の相互接続が、画素列バスを対応する回路列バスに接続する、請求項1に記載の内視鏡。
- 前記画素列のうちの1つのアスペクト比が、前記回路列のうちの1つのアスペクト比とは異なる、請求項1に記載の内視鏡。
- 前記回路列のうちの1つのアスペクト比が、前記画素列のうちの1つのアスペクト比の4倍の幅および4分の1の長さである、請求項1に記載の内視鏡。
- 前記回路列のうちの1つのアスペクト比が、前記画素列のうちの1つのアスペクト比の2倍の幅および半分の長さである、請求項8に記載の内視鏡。
- 管腔と、
前記内視鏡内に配設される撮像センサと
を備える内視鏡であって、
前記撮像センサが、
第1の基板および少なくとも1つの第2の次の支持用基板を含む複数の基板と、
画素配列と、
複数の相互接続と、
複数の支援回路と
を備え、
前記複数の基板のうちの前記第1の基板が、前記画素配列を備え、
前記複数の支援用回路が、前記第1の基板に対して遠隔に配置される前記少なくとも1つの第2の次の(subsequent)支持用基板上に配設され、
前記複数の支援用回路が、前記第1の基板と前記少なくとも1つの第2の次の支持用基板との間に配設された前記複数の相互接続を介して、前記画素配列に電気的に接続されると共に前記画素配列と電気通信し、
前記第2の次の支持用基板が、撮像される対象に対して前記画素配列の背後に配設され、
前記複数の相互接続が、前記画素配列の画素ピッチより大きい距離で互いに対して間隔をおいて配置される、内視鏡。 - 前記第1の基板上に位置する前記画素配列が、複数の画素列を備え、前記複数の画素列の各々が、幅1画素および長さ複数画素として定められる、請求項13に記載の内視鏡。
- 前記第2の基板上に位置する複数の支援用回路をさらに備えると共に、複数の回路列を備え、1つの回路列が1つの画素列に対応し、前記複数の回路列の各々が、対応する画素列の領域と対応する領域を有するものとして定められる、請求項14に記載の内視鏡。
- 複数のバスをさらに備え、前記第1の基板上に存在する少なくとも1つの画素列当たり1つの画素列バス、および前記第2の基板上に存在する回路列当たり1つの画素列バスが存在する、請求項14に記載の内視鏡。
- 前記画素列バスの各々の少なくとも一部が、前記対応する回路列バスの各々の少なくとも一部と重ね合わされ、少なくとも1つの相互接続が、1つの画素列バスと対応する1つの回路列バスの間の電気通信を与え、
前記少なくとも1つの相互接続が、1つの画素列バスと対応する1つの回路列バスの間のどこかに設置され、互いに対して重ね合わされる、
請求項16に記載の内視鏡。 - 前記撮像センサが裏面照射される、請求項13に記載の内視鏡。
- 前記画素配列が、前記第1の基板の表面の実質的大部分を覆う、請求項13に記載の撮像センサ。
- 前記画素配列が、前記第1の基板の表面の25パーセントより多くを覆う、請求項13に記載の撮像センサ。
- 前記第1の基板が、主にシリコン材料で作製される、請求項13に記載の撮像センサ。
- 前記第1の基板が、主に「高Z」半導体材料(テルル化カドミウム)で作製される、請求項13に記載の撮像センサ。
- 前記第1の基板が、主にIII−V半導体材料(ガリウムヒ素)で作製される、請求項13に記載の撮像センサ。
- 前記画素配列が、複数の画素列から構成され、各画素列が複数の画素を含み、
前記画素配列内の前記複数の画素列の各々が、共通の源から読み出される第1の列から順にバスに読み出され、第2の列が、前記第2の列に対して以前に読み出された画素列とは異なると共に、前記第2の列に対して続いて読み出される画素列とは異なる第1の行から読み出される、
請求項23に記載の撮像センサ。 - 前記第1の行が、前記以前に読み出された画素列および前記続いて読みだされる画素列の行の位置から少なくとも2つの行の位置だけ離れて間隔をおいて配置される、請求項24に記載の撮像センサ。
- 管腔と、
前記管腔の前記遠位端の近くに配設される撮像センサと
を備える内視鏡装置であって、
前記撮像センサが、
少なくとも第1の基板および第2の基板を備える複数の基板と、
前記第1の基板上に位置すると共に複数の画素列を備える画素配列であって、前記複数の画素列の各々が、前記配列の寸法(dimension)を覆うのに十分な幅1画素および長さ複数画素として定められ、
前記画素列が、画素サブ列(sub-columns)に分割され、各画素サブ列が、他の画素サブ列から電気的に絶縁されるようになっている、
画素配列と、
前記第2の基板上に位置する複数の支援用回路であって、複数の回路列を含んでおり、1つの回路列が1つの画素サブ列に対応し、前記複数の回路列の各々が、対応する画素サブ列の領域と対応する領域を有するものとして定められる、支援用回路と、
前記第1の基板上に存在する少なくとも1つの画素サブ列当たりの1つの画素サブ列バス、および前記第2の基板上に存在する回路列当たり1つの画素列バスが存在する複数のバスと
を備え、
前記画素サブ列バスの各々の少なくとも一部が、対応する回路列バスの各々の少なくとも一部と重ね合わされ、少なくとも1つの相互接続が1つの画素サブ列バスと対応する1つの回路列バスの間の電気通信を与え、
前記少なくとも1つの相互接続が、1つの画素サブ列バスと対応する1つの回路列バスの間のどこかに設置され、互いに対して重ね合わされる、内視鏡装置。 - 前記基板同士の間に配設される複数の相互接続をさらに備え、前記複数の相互接続が、前記画素配列の画素ピッチより大きい距離で互いに対して間隔をおいて配置される、請求項26に記載の内視鏡。
- 前記第1の基板および前記第2の基板が、揃った状態である、請求項26に記載の内視鏡。
- 前記第1の基板上の前記画素サブ列のうちの1つの領域が、前記第2の基板上の前記対応する回路列のうちの1つの領域とほぼ等しい、請求項26に記載の内視鏡。
- 前記第2の基板が、前記第1の基板とほぼ同じサイズである、請求項26に記載の内視鏡。
- 前記第1の基板上の前記画素サブ列のうちの1つの領域が、前記第2の基板上の前記対応する回路列のうちの1つの領域より大きい、請求項26に記載の内視鏡。
- 前記第1の基板上の前記画素サブ列のうちの1つの領域が、前記第2の基板上の前記対応する回路列のうちの1つの領域より小さい、請求項26に記載の内視鏡。
- 前記画素サブ列のうちの1つのアスペクト比が、前記回路列のうちの1つのアスペクト比とほぼ同様である、請求項26に記載の内視鏡。
- 複数の相互接続が、画素サブ列バスを対応する回路列バスに接続する、請求項26に記載の内視鏡。
- 前記画素サブ列のうちの1つのアスペクト比が、前記回路列のうちの1つのアスペクト比とは異なる、請求項26に記載の内視鏡。
- 前記回路列のうちの1つのアスペクト比が、前記画素サブ列のうちの1つのアスペクト比の4倍の幅および4分の1の長さである、請求項26に記載の内視鏡。
- 前記回路列のうちの1つのアスペクト比が、前記画素サブ列のうちの1つのアスペクト比の2倍の幅および半分の長さである、請求項26に記載の内視鏡。
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JP2022031325A (ja) * | 2017-09-29 | 2022-02-18 | キヤノン株式会社 | 半導体装置および機器 |
JP7293323B2 (ja) | 2017-09-29 | 2023-06-19 | キヤノン株式会社 | 半導体装置および機器 |
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