JP5861868B2 - 電子回路および電子回路の製造方法 - Google Patents
電子回路および電子回路の製造方法 Download PDFInfo
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Description
シングルエンド信号がやりとりされるパッドを有するシングルエンドI/Fが設けられた半導体チップと、
差動信号を伝送する差動伝送路が形成されており、前記差動伝送路を構成する導体に、前記シングルエンドI/Fのパッドが、電気的に直接接続されるように、前記半導体チップが実装された実装部と
を備える電子回路。
[2]
前記シングルエンドI/Fは、信号がやりとりされる信号パッドと、グランドに接続されるグランドパットとを有し、
前記差動伝送路は、平行に配置された2本の導体を有し、
前記信号パッドと、前記2本の導体のうちの一方の導体とが接続され、かつ、前記グランドパットと、前記2本の導体のうちの他方の導体とが接続されるように、前記半導体チップが、前記実装部に実装されている
[1]に記載の電子回路。
[3]
誘電体が、前記差動伝送路上に配置されている
[2]に記載の電子回路。
[4]
前記誘電体は、前記シングルエンドI/Fのインピーダンスと、前記差動伝送路のインピーダンスとを整合させる誘電率の誘電体である
[3]に記載の電子回路。
[5]
前記誘電体は、前記実装部の誘電率より大きい誘電率の誘電体である
[3]又は[4]に記載の電子回路。
[6]
前記誘電体は、前記差動伝送路の前記2本の導体に沿って配置されており、前記2本の導体の一方の導体から他方の導体までの全体を覆うことができる幅の誘電体である
[3]ないし[5]のいずれかに記載の電子回路。
[7]
前記誘電体は、前記差動伝送路の前記2本の導体に沿って配置されており、前記2本の導体の間の、前記2本の導体を含む距離と同一の幅を有する誘電体である
[3]ないし[5]のいずれかに記載の電子回路。
[8]
前記誘電体は、前記差動伝送路の前記2本の導体に沿って、前記2本の導体の間に配置されており、前記2本の導体の間の、前記2本の導体を含まない距離と同一の幅を有する誘電体である
[3]ないし[5]のいずれかに記載の電子回路。
[9]
前記差動伝送路の2本の導体は、前記シングルエンドI/Fのインピーダンスと、前記差動伝送路のインピーダンスとを整合させるように、厚みが調整されている
[2]に記載の電子回路。
[10]
前記2本の導体が、層状に形成されている
[2]に記載の電子回路。
[11]
前記差動伝送路は、コプレーナストリップ線路である
[1]ないし[10]のいずれかに記載の電子回路。
[12]
前記シングルエンド信号は、ミリ波帯の信号である
[1]ないし[11]のいずれかに記載の電子回路。
[13]
シングルエンド信号がやりとりされるパッドを有するシングルエンドI/Fが設けられた半導体チップを、差動信号を伝送する差動伝送路が形成された、前記半導体チップが実装される実装部に実装するときに、前記差動伝送路を構成する導体に、前記シングルエンドI/Fのパッドを、電気的に直接接続させる
電子回路の製造方法。
[14]
差動信号を伝送する差動伝送路が形成され、
前記差動伝送路上に誘電体が配置され、
シングルエンド信号がやりとりされるパッドを有するシングルエンドI/Fが設けられた半導体チップが実装される
実装部材。
[15]
前記シングルエンドI/Fは、信号がやりとりされる信号パッドと、グランドに接続されるグランドパットとを有し、
前記差動伝送路は、平行に配置された2本の導体を有し、
前記信号パッドと、前記2本の導体のうちの一方の導体とが接続され、かつ、前記グランドパットと、前記2本の導体のうちの他方の導体とが接続されるように、前記半導体チップが実装される
[14]に実装部材。
[16]
前記誘電体は、前記シングルエンドI/Fのインピーダンスと、前記差動伝送路のインピーダンスとを整合させる誘電率の誘電体である
[14]又は[15]に記載の実装部材。
[17]
前記誘電体は、前記実装部の誘電率より大きい誘電率の誘電体である
[14]又は[15]に記載の実装部材。
[18]
前記差動伝送路は、コプレーナストリップ線路である
[14]ないし[17]のいずれかに記載の実装部材。
[19]
前記シングルエンド信号は、ミリ波帯の信号である
[14]ないし[18]のいずれかに記載の実装部材。
Claims (15)
- ミリ波帯の信号であるシングルエンド信号がやりとりされる信号パッドと、グランドに接続されるグランドパッドを有するシングルエンドI/Fが設けられた半導体チップと、
差動信号を伝送する差動伝送路が形成されており、前記差動伝送路を構成する平行に配置された2本の導体の一方に前記信号パッドが電気的に直接接続され、他方に前記グランドパッドが電気的に直接接続されるように、前記半導体チップが実装された実装部と
を備え、
前記2本の導体の一方には、グランドに接続されるグランド配線が接続される
電子回路。 - 前記グランド配線の長さは、前記ミリ波帯の信号の波長の4分の1である
請求項1に記載の電子回路。 - 前記グランド配線の一部は、前記2本の導体と平行に配置され、
前記グランド配線の一部の長さは、前記ミリ波帯の信号の波長の4分の1である
請求項1に記載の電子回路。 - 前記半導体チップは、前記グランドパッドとは異なる、前記グランド配線に接続されるグランドパッドを有する
請求項1ないし3のいずれかに記載の電子回路。 - 前記グランド配線に接続されるグランドパッドは、前記シングルエンドI/Fに設けられる
請求項4に記載の電子回路。 - 誘電体が、前記差動伝送路上に配置されている
請求項1ないし5のいずれかに記載の電子回路。 - 前記誘電体は、前記シングルエンドI/Fのインピーダンスと、前記差動伝送路のインピーダンスとを整合させる誘電率の誘電体である
請求項6に記載の電子回路。 - 前記誘電体は、前記実装部の誘電率より大きい誘電率の誘電体である
請求項6又は7に記載の電子回路。 - 前記誘電体は、前記差動伝送路の前記2本の導体に沿って配置されており、前記2本の導体の一方の導体から他方の導体までの全体を覆うことができる幅の誘電体である
請求項6ないし8のいずれかに記載の電子回路。 - 前記誘電体は、前記差動伝送路の前記2本の導体に沿って配置されており、前記2本の導体の間の、前記2本の導体を含む距離と同一の幅を有する誘電体である
請求項6ないし8のいずれかに記載の電子回路。 - 前記誘電体は、前記差動伝送路の前記2本の導体に沿って、前記2本の導体の間に配置されており、前記2本の導体の間の、前記2本の導体を含まない距離と同一の幅を有する誘電体である
請求項6ないし8のいずれかに記載の電子回路。 - 前記差動伝送路の2本の導体は、前記シングルエンドI/Fのインピーダンスと、前記差動伝送路のインピーダンスとを整合させるように、厚みが調整されている
請求項1ないし5のいずれかに記載の電子回路。 - 前記2本の導体が、層状に形成されている
請求項1ないし5のいずれかに記載の電子回路。 - 前記差動伝送路は、コプレーナストリップ線路である
請求項1ないし13のいずれかに記載の電子回路。 - ミリ波帯の信号であるシングルエンド信号がやりとりされる信号パッドと、グランドに接続されるグランドパッドを有するシングルエンドI/Fが設けられた半導体チップを、差動信号を伝送する差動伝送路が形成された、前記半導体チップが実装される実装部に実装するときに、前記差動伝送路を構成する平行に配置された2本の導体の一方であって、グランドに接続されるグランド配線が接続される導体に前記信号パッドを電気的に直接接続させ、他方に前記グランドパッドを電気的に直接接続させる
電子回路の製造方法。
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JP2011241943A JP5861868B2 (ja) | 2011-11-04 | 2011-11-04 | 電子回路および電子回路の製造方法 |
US13/660,111 US9596750B2 (en) | 2011-11-04 | 2012-10-25 | Electronic circuit, method of manufacturing electronic circuit, and mounting member |
CN201210413331.9A CN103094653B (zh) | 2011-11-04 | 2012-10-25 | 电子电路、电子电路的制造方法和安装部件 |
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US9596750B2 (en) | 2017-03-14 |
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