JP2006277870A - 半導体記憶装置 - Google Patents
半導体記憶装置 Download PDFInfo
- Publication number
- JP2006277870A JP2006277870A JP2005098027A JP2005098027A JP2006277870A JP 2006277870 A JP2006277870 A JP 2006277870A JP 2005098027 A JP2005098027 A JP 2005098027A JP 2005098027 A JP2005098027 A JP 2005098027A JP 2006277870 A JP2006277870 A JP 2006277870A
- Authority
- JP
- Japan
- Prior art keywords
- command
- chip
- address
- memory chips
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 77
- 230000015654 memory Effects 0.000 claims abstract description 168
- 230000003213 activating effect Effects 0.000 claims abstract description 4
- 239000000872 buffer Substances 0.000 claims description 55
- 239000000758 substrate Substances 0.000 claims description 34
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 claims description 22
- 230000006870 function Effects 0.000 claims description 18
- 238000012360 testing method Methods 0.000 claims description 15
- 238000011084 recovery Methods 0.000 claims description 13
- 230000004913 activation Effects 0.000 claims description 7
- 230000005540 biological transmission Effects 0.000 claims description 7
- 230000003071 parasitic effect Effects 0.000 abstract description 15
- 238000010586 diagram Methods 0.000 description 32
- 238000000034 method Methods 0.000 description 20
- 230000002457 bidirectional effect Effects 0.000 description 10
- 230000002093 peripheral effect Effects 0.000 description 8
- 208000035795 Hypocalcemic vitamin D-dependent rickets Diseases 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 5
- 208000033584 type 1 vitamin D-dependent rickets Diseases 0.000 description 5
- 101000597193 Homo sapiens Telethonin Proteins 0.000 description 4
- 102100035155 Telethonin Human genes 0.000 description 4
- 230000000295 complement effect Effects 0.000 description 4
- 101100018377 Saccharomyces cerevisiae (strain ATCC 204508 / S288c) ICS3 gene Proteins 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000000630 rising effect Effects 0.000 description 2
- 238000007599 discharging Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000014759 maintenance of location Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4096—Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/50—Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Databases & Information Systems (AREA)
- Power Engineering (AREA)
- Dram (AREA)
- Static Random-Access Memory (AREA)
Abstract
【解決手段】 コマンド・アドレス外部端子群CA、データ入出力外部端子群DQ、並びに、単一のチップ選択外部端子CSを有するベース基板101と、ベース基板101上に積層され、それぞれ単独で読み出し動作及び書き込み動作が可能な複数のメモリチップ110〜113とを備える。端子CA,DQ,CSは、いずれもインターフェースチップ120に接続されている。インターフェースチップ120は、端子CAを介して供給されるアドレス信号及び端子CSを介して供給されるチップ選択信号に基づいて、複数のメモリチップ110〜113を個別に活性化可能なチップ選択信号発生回路を有している。
【選択図】 図4
Description
101 ベース基板
101a ベース基板上のパッド
110〜113 メモリチップ
110a メモリチップ上のパッド
120,220 インターフェースチップ
130〜133 テープ
320 インターフェース機能を持ったメモリチップ
ABR 活性バンクレジスタ
CA コマンド・アドレス外部端子群
CAB コマンド・アドレスバス
CAP,ECAP,ICAP コマンド・アドレスパッド
CDC コマンドデコーダ
CS チップ選択信号外部端子
CSG チップ選択信号発生回路
CSP,ECSP,ICSP チップ選択信号パッド
DEC デコーダ
DLL クロック再生回路
DQ データ入出力外部端子群
DQB データバス
DQP,EDQP,IDQP データ入出力パッド
DSG ストローブ信号発生回路
ESD 静電保護素子
EXB ボール電極
INB 入力バッファ
INW 内部配線
L ラッチ回路
MA メモリアレイ
MR モードレジスタ
MUX 双方向マルチプレクサ
OB 出力バッファ
OBV インピーダンス可変出力バッファ
PERI 周辺回路領域
REP 双方向リピータ
RT 終端抵抗
SEL セレクタ
TCAP テスト用コマンド・アドレスパッド
TDQP テスト用データ入出力パッド
VRG 降圧回路
VS 電源外部端子群
VSP 電源パッド
Claims (14)
- コマンド信号及びアドレス信号が供給されるコマンド・アドレス外部端子群、データ信号の授受を行うデータ入出力外部端子群、並びに、単一のチップ選択外部端子を有するベース基板と、
前記ベース基板上に積層され、それぞれ単独で読み出し動作及び書き込み動作が可能な複数のメモリチップとを備え、
前記コマンド・アドレス外部端子群を構成する複数の端子、前記データ外部端子群を構成する複数の端子、並びに、前記単一のチップ選択外部端子は、いずれも、インターフェース機能を有する単一のチップに接続されており、
前記インターフェース機能を有する単一のチップは、少なくとも、前記コマンド・アドレス外部端子群を介して供給される前記アドレス信号及び前記チップ選択外部端子を介して供給される前記チップ選択信号に基づいて、前記複数のメモリチップを個別に活性化可能なチップ選択信号発生回路を有していることを特徴とする半導体記憶装置。 - 前記インターフェース機能を有する単一のチップは、前記複数のメモリチップとは異なるインターフェースチップであることを特徴とする請求項1に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップは、前記複数のメモリチップのいずれか一つのチップであることを特徴とする請求項1に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップと前記複数のメモリチップとの間における前記コマンド信号、前記アドレス信号及び前記データ信号の少なくとも一部の信号の送信を、前記複数のメモリチップに対して共通接続された配線を介して行うことを特徴とする請求項1乃至3のいずれか1項に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップと前記複数のメモリチップとの間における前記コマンド信号、前記アドレス信号及び前記データ信号の少なくとも一部の信号の送信を、前記複数のメモリチップに対してそれぞれ個別に接続された配線を介して行うことを特徴とする請求項1乃至4のいずれか1項に記載の半導体記憶装置。
- 前記チップ選択信号発生回路は、活性化コマンドが入力された場合、前記コマンド・アドレス外部端子群を介して供給される前記アドレス信号のうち、バンクアドレスとは異なる部分に基づいて、前記複数のメモリチップのいずれか一つを活性化することを特徴とする請求項1乃至5のいずれか1項に記載の半導体記憶装置。
- 前記チップ選択信号発生回路には、選択されたバンクと活性化させるべきメモリチップとの関係を記憶する活性バンクレジスタを有しており、前記コマンド・アドレス外部端子群を介して、前記バンクアドレスとともにリードコマンド又はライトコマンドが入力された場合、前記活性バンクレジスタを参照することによって、前記複数のメモリチップのいずれか一つを活性化させることを特徴とする請求項6に記載の半導体記憶装置。
- 前記チップ選択信号発生回路は、リフレッシュコマンドが入力された場合、前記複数のメモリチップを順次活性化することを特徴とする請求項1乃至7のいずれか1項に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップにはクロック再生回路が含まれており、前記複数のメモリチップには、前記クロック再生回路により再生されたクロックが供給されることを特徴とする請求項1乃至8のいずれか1項に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップにはストローブ信号発生回路が含まれており、前記インターフェース機能を有する単一のチップは、前記ストローブ信号発生回路の出力に同期して、前記メモリチップから読み出したデータ信号を前記データ入出力外部端子群を介して出力することを特徴とする請求項1乃至9のいずれか1項に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップには、前記データ入出力外部端子群に接続された終端抵抗が含まれていることを特徴とする請求項1乃至10のいずれか1項に記載の半導体記憶装置。
- 前記複数のメモリチップはいずれもボンディングパッド領域を有しており、前記複数のメモリチップは、配線が形成されたテープを介して前記ベース基板に接続されていることを特徴とする請求項1乃至11のいずれか1項に記載の半導体記憶装置。
- 前記インターフェース機能を有する単一のチップに含まれる出力バッファのうち、前記複数のメモリチップに対して出力するための出力バッファには、高レベル側電源電圧として、外部から供給される高レベル側電源電圧よりも低い内部電源電圧が与えられ、低レベル側電源電圧として、外部から供給される低レベル側電源電圧よりも高い内部電源電圧が与えられることを特徴とする請求項1乃至12のいずれか1項に記載の半導体記憶装置。
- 前記複数のメモリチップはいずれも、実使用時に使用する通常パッドの他にテスト用パッドを有しており、前記テスト用パッドは、少なくともバッファ回路を介してメモリアレイに接続されており、前記通常パッドは、前記バッファ回路をバイパスして前記メモリアレイに接続されていることを特徴とする請求項1乃至13のいずれか1項に記載の半導体記憶装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005098027A JP4309368B2 (ja) | 2005-03-30 | 2005-03-30 | 半導体記憶装置 |
CN200610071011.4A CN100570738C (zh) | 2005-03-30 | 2006-03-30 | 具有多个层叠的存储芯片的半导体存储器件 |
US11/392,805 US7466577B2 (en) | 2005-03-30 | 2006-03-30 | Semiconductor storage device having a plurality of stacked memory chips |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2005098027A JP4309368B2 (ja) | 2005-03-30 | 2005-03-30 | 半導体記憶装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006277870A true JP2006277870A (ja) | 2006-10-12 |
JP4309368B2 JP4309368B2 (ja) | 2009-08-05 |
Family
ID=37030522
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2005098027A Expired - Fee Related JP4309368B2 (ja) | 2005-03-30 | 2005-03-30 | 半導体記憶装置 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7466577B2 (ja) |
JP (1) | JP4309368B2 (ja) |
CN (1) | CN100570738C (ja) |
Cited By (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009301415A (ja) * | 2008-06-16 | 2009-12-24 | Nec Corp | メモリモジュール制御方法及びメモリモジュール並びにデータ転送装置 |
JP2010045762A (ja) * | 2008-08-08 | 2010-02-25 | Hynix Semiconductor Inc | 半導体集積回路及びその制御方法 |
JP2010514080A (ja) * | 2006-12-14 | 2010-04-30 | ラムバス・インコーポレーテッド | マルチダイメモリ素子 |
US7830692B2 (en) | 2007-10-04 | 2010-11-09 | Samsung Electronics Co., Ltd. | Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory |
JP2010277620A (ja) * | 2009-05-26 | 2010-12-09 | Elpida Memory Inc | 半導体記憶装置及びこれを備える情報処理システム並びにコントローラ |
JP2011081881A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体記憶装置及びデータ処理システム |
JP2012059348A (ja) * | 2010-09-03 | 2012-03-22 | Samsung Electronics Co Ltd | 半導体メモリ装置 |
JP2012099189A (ja) * | 2010-11-04 | 2012-05-24 | Elpida Memory Inc | 半導体装置 |
JP2012150565A (ja) * | 2011-01-17 | 2012-08-09 | Elpida Memory Inc | 半導体装置 |
JP2012155641A (ja) * | 2011-01-28 | 2012-08-16 | Elpida Memory Inc | 半導体装置 |
JP2012209497A (ja) * | 2011-03-30 | 2012-10-25 | Elpida Memory Inc | 半導体装置 |
JP2012221540A (ja) * | 2011-04-13 | 2012-11-12 | Elpida Memory Inc | 半導体装置及びシステム |
JP2012238376A (ja) * | 2005-09-02 | 2012-12-06 | Metallum Inc | Dramをスタックする方法及び装置 |
JP2013516020A (ja) * | 2009-12-31 | 2013-05-09 | インテル コーポレイション | ハイブリッドメモリのためのシステム、方法及び装置 |
JP2013097843A (ja) * | 2011-11-02 | 2013-05-20 | Toshiba Corp | 半導体記憶装置 |
US8473653B2 (en) | 2009-10-09 | 2013-06-25 | Elpida Memory, Inc. | Semiconductor device, control method for the semiconductor device and information processing system including the same |
KR20140003234A (ko) * | 2012-06-29 | 2014-01-09 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
US8693230B2 (en) | 2011-03-31 | 2014-04-08 | Elpida Memory, Inc. | Semiconductor device including plural chips stacked to each other |
KR101416315B1 (ko) | 2007-11-09 | 2014-07-08 | 삼성전자주식회사 | 내부 전압 제어 방법 및 그 방법을 이용하는 멀티 칩패키지 메모리 |
JP2015521337A (ja) * | 2012-06-28 | 2015-07-27 | インテル・コーポレーション | Dramにおける電力低減のための構成 |
US9209160B2 (en) | 2011-07-20 | 2015-12-08 | Samsung Electronics Co., Ltd. | Semiconductor devices compatible with mono-rank and multi-ranks |
US9230610B2 (en) | 2013-12-09 | 2016-01-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device for use in multi-chip package |
JP2016526724A (ja) * | 2013-07-01 | 2016-09-05 | インテル・コーポレーション | 不整合信号受信器に対するタイミング制御 |
JPWO2016038748A1 (ja) * | 2014-09-12 | 2017-06-29 | 株式会社東芝 | 記憶装置 |
CN114115440A (zh) * | 2020-08-26 | 2022-03-01 | 长鑫存储技术有限公司 | 存储器 |
US11302379B2 (en) | 2019-10-04 | 2022-04-12 | Honda Motor Co., Ltd. | Semiconductor apparatus |
US11309290B2 (en) | 2019-10-04 | 2022-04-19 | Honda Motor Co., Ltd. | Semiconductor apparatus including penetration electrodes connecting laminated semiconductor chips |
US11456028B2 (en) | 2020-03-06 | 2022-09-27 | Honda Motor Co., Ltd. | Semiconductor device and control method thereof |
Families Citing this family (160)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7289386B2 (en) | 2004-03-05 | 2007-10-30 | Netlist, Inc. | Memory module decoder |
US7916574B1 (en) | 2004-03-05 | 2011-03-29 | Netlist, Inc. | Circuit providing load isolation and memory domain translation for memory module |
US7341887B2 (en) * | 2004-10-29 | 2008-03-11 | Intel Corporation | Integrated circuit die configuration for packaging |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US9542352B2 (en) | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US8060774B2 (en) | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US7327592B2 (en) * | 2005-08-30 | 2008-02-05 | Micron Technology, Inc. | Self-identifying stacked die semiconductor components |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
JP4885623B2 (ja) * | 2006-06-13 | 2012-02-29 | エルピーダメモリ株式会社 | 積層半導体装置 |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
JP4353330B2 (ja) * | 2006-11-22 | 2009-10-28 | エルピーダメモリ株式会社 | 半導体装置および半導体チップ |
US8504788B2 (en) | 2006-12-20 | 2013-08-06 | Rambus Inc. | Memory controller, system and method for read signal timing calibration |
US8228704B2 (en) * | 2007-02-28 | 2012-07-24 | Samsung Electronics Co., Ltd. | Stacked semiconductor chip package with shared DLL signal and method for fabricating stacked semiconductor chip package with shared DLL signal |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US7623365B2 (en) * | 2007-08-29 | 2009-11-24 | Micron Technology, Inc. | Memory device interface methods, apparatus, and systems |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
JP2009094152A (ja) * | 2007-10-04 | 2009-04-30 | Hitachi Ltd | 半導体装置、その製造方法及び半導体搭載用フレキシブル基板 |
JP5557419B2 (ja) | 2007-10-17 | 2014-07-23 | スパンション エルエルシー | 半導体装置 |
KR101393311B1 (ko) | 2008-03-19 | 2014-05-12 | 삼성전자주식회사 | 프로세스 변화량을 보상하는 멀티 칩 패키지 메모리 |
US8516185B2 (en) * | 2009-07-16 | 2013-08-20 | Netlist, Inc. | System and method utilizing distributed byte-wise buffers on a memory module |
US8154901B1 (en) | 2008-04-14 | 2012-04-10 | Netlist, Inc. | Circuit providing load isolation and noise reduction |
US8787060B2 (en) | 2010-11-03 | 2014-07-22 | Netlist, Inc. | Method and apparatus for optimizing driver load in a memory package |
US8521979B2 (en) | 2008-05-29 | 2013-08-27 | Micron Technology, Inc. | Memory systems and methods for controlling the timing of receiving read data |
US7979757B2 (en) | 2008-06-03 | 2011-07-12 | Micron Technology, Inc. | Method and apparatus for testing high capacity/high bandwidth memory devices |
US8289806B2 (en) | 2008-06-27 | 2012-10-16 | Micron Technology, Inc. | Multiple device apparatus, systems, and methods |
US8756486B2 (en) | 2008-07-02 | 2014-06-17 | Micron Technology, Inc. | Method and apparatus for repairing high capacity/high bandwidth memory devices |
US7855931B2 (en) | 2008-07-21 | 2010-12-21 | Micron Technology, Inc. | Memory system and method using stacked memory device dice, and system using the memory system |
US8289760B2 (en) * | 2008-07-02 | 2012-10-16 | Micron Technology, Inc. | Multi-mode memory device and method having stacked memory dice, a logic die and a command processing circuit and operating in direct and indirect modes |
JP2010021449A (ja) * | 2008-07-11 | 2010-01-28 | Toshiba Corp | 半導体装置 |
US8127204B2 (en) | 2008-08-15 | 2012-02-28 | Micron Technology, Inc. | Memory system and method using a memory device die stacked with a logic die using data encoding, and system using the memory system |
US8106520B2 (en) | 2008-09-11 | 2012-01-31 | Micron Technology, Inc. | Signal delivery in stacked device |
US7925949B2 (en) | 2008-10-15 | 2011-04-12 | Micron Technology, Inc. | Embedded processor |
JP5632584B2 (ja) * | 2009-02-05 | 2014-11-26 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
US7894230B2 (en) | 2009-02-24 | 2011-02-22 | Mosaid Technologies Incorporated | Stacked semiconductor devices including a master device |
US8264903B1 (en) | 2009-05-05 | 2012-09-11 | Netlist, Inc. | Systems and methods for refreshing a memory module |
WO2010144624A1 (en) | 2009-06-09 | 2010-12-16 | Google Inc. | Programming of dimm termination resistance values |
KR101605747B1 (ko) | 2009-06-11 | 2016-03-23 | 삼성전자주식회사 | 물리적으로 공유된 데이터 패스를 구비하는 반도체 메모리 장치 및 이에 대한 테스트 장치 |
TWI474331B (zh) * | 2009-06-30 | 2015-02-21 | Hitachi Ltd | Semiconductor device |
US9128632B2 (en) | 2009-07-16 | 2015-09-08 | Netlist, Inc. | Memory module with distributed data buffers and method of operation |
KR20110078189A (ko) * | 2009-12-30 | 2011-07-07 | 삼성전자주식회사 | 적층 구조의 반도체 칩들을 구비하는 메모리 카드 및 메모리 시스템 |
KR101046272B1 (ko) * | 2010-01-29 | 2011-07-04 | 주식회사 하이닉스반도체 | 반도체 장치 |
KR101046273B1 (ko) * | 2010-01-29 | 2011-07-04 | 주식회사 하이닉스반도체 | 반도체 장치 |
US8796863B2 (en) | 2010-02-09 | 2014-08-05 | Samsung Electronics Co., Ltd. | Semiconductor memory devices and semiconductor packages |
JP2011180848A (ja) * | 2010-03-01 | 2011-09-15 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム、並びに、半導体装置を制御するコントローラ |
MY166609A (en) * | 2010-09-15 | 2018-07-17 | Semiconductor Components Ind Llc | Connector assembly and method of manufacture |
MY163661A (en) * | 2010-09-15 | 2017-10-13 | Semiconductor Components Ind Llc | Semiconductor component and method of manufacture |
KR101212854B1 (ko) * | 2010-12-03 | 2012-12-14 | 에스케이하이닉스 주식회사 | 멀티 칩 패키지 장치 및 그의 동작 방법 |
US8400808B2 (en) | 2010-12-16 | 2013-03-19 | Micron Technology, Inc. | Phase interpolators and push-pull buffers |
KR101198141B1 (ko) * | 2010-12-21 | 2012-11-12 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
US8400870B2 (en) * | 2011-01-04 | 2013-03-19 | Winbond Electronics Corp. | Memory devices and accessing methods thereof |
JP2012146377A (ja) * | 2011-01-14 | 2012-08-02 | Elpida Memory Inc | 半導体装置 |
JP2012155814A (ja) * | 2011-01-28 | 2012-08-16 | Elpida Memory Inc | 半導体装置及びこれを備える情報処理システム |
KR101263663B1 (ko) * | 2011-02-09 | 2013-05-22 | 에스케이하이닉스 주식회사 | 반도체 장치 |
TWI489477B (zh) * | 2011-03-07 | 2015-06-21 | Winbond Electronics Corp | 記憶體裝置以及其存取方法 |
CN102681943B (zh) * | 2011-03-16 | 2015-07-08 | 华邦电子股份有限公司 | 内存装置以及其存取方法 |
US9432298B1 (en) | 2011-12-09 | 2016-08-30 | P4tents1, LLC | System, method, and computer program product for improving memory systems |
US8913447B2 (en) * | 2011-06-24 | 2014-12-16 | Micron Technology, Inc. | Method and apparatus for memory command input and control |
JP2013077358A (ja) | 2011-09-30 | 2013-04-25 | Elpida Memory Inc | 半導体装置 |
JP5846664B2 (ja) * | 2011-12-28 | 2016-01-20 | インテル・コーポレーション | メモリ回路試験エンジン用の汎用アドレススクランブラ |
CN104246891B (zh) * | 2012-03-20 | 2018-01-26 | 英特尔公司 | 响应用于操作控制的装置命令的存储器装置 |
DE112012006172B4 (de) | 2012-03-30 | 2020-12-03 | Intel Corporation | Generischer Adressen-Scrambler für Speicherschaltungs-Testengine |
KR101980162B1 (ko) * | 2012-06-28 | 2019-08-28 | 에스케이하이닉스 주식회사 | 메모리 |
KR101919415B1 (ko) * | 2012-08-08 | 2018-11-16 | 에스케이하이닉스 주식회사 | 반도체 장치 |
KR20150046245A (ko) * | 2012-08-22 | 2015-04-29 | 피에스5 뤽스코 에스.에이.알.엘. | 멀티워드 상태를 방지하는 반도체 장치 |
CN102982647B (zh) * | 2012-12-06 | 2016-03-30 | 无锡华润矽科微电子有限公司 | 一种感烟报警装置的控制芯片设计的布线方法 |
US8817547B2 (en) * | 2012-12-10 | 2014-08-26 | Micron Technology, Inc. | Apparatuses and methods for unit identification in a master/slave memory stack |
US9190133B2 (en) | 2013-03-11 | 2015-11-17 | Micron Technology, Inc. | Apparatuses and methods for a memory die architecture including an interface memory |
US10324841B2 (en) | 2013-07-27 | 2019-06-18 | Netlist, Inc. | Memory module with local synchronization |
US9047953B2 (en) * | 2013-08-22 | 2015-06-02 | Macronix International Co., Ltd. | Memory device structure with page buffers in a page-buffer level separate from the array level |
US9171597B2 (en) | 2013-08-30 | 2015-10-27 | Micron Technology, Inc. | Apparatuses and methods for providing strobe signals to memories |
JP2015076110A (ja) * | 2013-10-08 | 2015-04-20 | マイクロン テクノロジー, インク. | 半導体装置及びこれを備えるデータ処理システム |
CN105531766A (zh) * | 2013-10-15 | 2016-04-27 | 拉姆伯斯公司 | 负载减小的存储模块 |
JP6067541B2 (ja) | 2013-11-08 | 2017-01-25 | 株式会社東芝 | メモリシステムおよびメモリシステムのアセンブリ方法 |
TWI539565B (zh) * | 2014-01-29 | 2016-06-21 | 森富科技股份有限公司 | 記憶體與記憶體球位焊墊之佈局方法 |
KR20150101762A (ko) * | 2014-02-27 | 2015-09-04 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US8908450B1 (en) | 2014-07-21 | 2014-12-09 | I'M Intelligent Memory Limited | Double capacity computer memory device |
KR20160029386A (ko) * | 2014-09-05 | 2016-03-15 | 에스케이하이닉스 주식회사 | 적층형 반도체 장치 |
KR20160068546A (ko) | 2014-12-05 | 2016-06-15 | 에스케이하이닉스 주식회사 | 반도체 장치의 입력 회로 및 이를 이용한 반도체 시스템 |
US9570142B2 (en) | 2015-05-18 | 2017-02-14 | Micron Technology, Inc. | Apparatus having dice to perorm refresh operations |
KR102401109B1 (ko) * | 2015-06-03 | 2022-05-23 | 삼성전자주식회사 | 반도체 패키지 |
US9825002B2 (en) | 2015-07-17 | 2017-11-21 | Invensas Corporation | Flipped die stack |
US9871019B2 (en) | 2015-07-17 | 2018-01-16 | Invensas Corporation | Flipped die stack assemblies with leadframe interconnects |
JP6509711B2 (ja) * | 2015-10-29 | 2019-05-08 | 東芝メモリ株式会社 | 不揮発性半導体記憶装置及びメモリシステム |
US9508691B1 (en) | 2015-12-16 | 2016-11-29 | Invensas Corporation | Flipped die stacks with multiple rows of leadframe interconnects |
KR20170082798A (ko) * | 2016-01-07 | 2017-07-17 | 에스케이하이닉스 주식회사 | 메모리 모듈 |
US10566310B2 (en) | 2016-04-11 | 2020-02-18 | Invensas Corporation | Microelectronic packages having stacked die and wire bond interconnects |
KR102509048B1 (ko) | 2016-04-26 | 2023-03-10 | 에스케이하이닉스 주식회사 | 반도체 패키지 |
US10083722B2 (en) * | 2016-06-08 | 2018-09-25 | Samsung Electronics Co., Ltd. | Memory device for performing internal process and operating method thereof |
US9728524B1 (en) | 2016-06-30 | 2017-08-08 | Invensas Corporation | Enhanced density assembly having microelectronic packages mounted at substantial angle to board |
US11068161B1 (en) * | 2016-07-18 | 2021-07-20 | Rambus Inc. | Memory module with emulated memory device population |
US20180040589A1 (en) * | 2016-08-03 | 2018-02-08 | Invensas Corporation | Microelectronic packages and assemblies with repeaters |
JP6736441B2 (ja) * | 2016-09-28 | 2020-08-05 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
US10490251B2 (en) | 2017-01-30 | 2019-11-26 | Micron Technology, Inc. | Apparatuses and methods for distributing row hammer refresh events across a memory device |
US10020046B1 (en) | 2017-03-03 | 2018-07-10 | Micron Technology, Inc. | Stack refresh control for memory device |
JP2018152147A (ja) * | 2017-03-10 | 2018-09-27 | 東芝メモリ株式会社 | 半導体記憶装置及び方法 |
JP6679528B2 (ja) * | 2017-03-22 | 2020-04-15 | キオクシア株式会社 | 半導体装置 |
KR102395463B1 (ko) * | 2017-09-27 | 2022-05-09 | 삼성전자주식회사 | 적층형 메모리 장치, 이를 포함하는 시스템 및 그 동작 방법 |
TWI658363B (zh) * | 2017-10-20 | 2019-05-01 | 慧榮科技股份有限公司 | 儲存裝置以及其介面晶片 |
KR102454368B1 (ko) * | 2018-01-22 | 2022-10-14 | 삼성전자주식회사 | 메모리 패키지 및 반도체 패키지 |
EP3776638A1 (en) * | 2018-04-11 | 2021-02-17 | ABB Power Grids Switzerland AG | Material reduced metallic plate on power semiconductor chip |
WO2019222960A1 (en) | 2018-05-24 | 2019-11-28 | Micron Technology, Inc. | Apparatuses and methods for pure-time, self adopt sampling for row hammer refresh sampling |
US10573370B2 (en) | 2018-07-02 | 2020-02-25 | Micron Technology, Inc. | Apparatus and methods for triggering row hammer address sampling |
CN112567352A (zh) | 2018-08-14 | 2021-03-26 | 拉姆伯斯公司 | 经封装的集成设备 |
WO2020063720A1 (en) * | 2018-09-27 | 2020-04-02 | Changxin Memory Technologies, Inc. | Power supply system and semiconductor package assembly |
US10685696B2 (en) | 2018-10-31 | 2020-06-16 | Micron Technology, Inc. | Apparatuses and methods for access based refresh timing |
WO2020117686A1 (en) | 2018-12-03 | 2020-06-11 | Micron Technology, Inc. | Semiconductor device performing row hammer refresh operation |
CN111354393B (zh) * | 2018-12-21 | 2023-10-20 | 美光科技公司 | 用于目标刷新操作的时序交错的设备和方法 |
KR102579174B1 (ko) * | 2018-12-24 | 2023-09-18 | 에스케이하이닉스 주식회사 | 적층형 메모리 장치 및 이를 포함하는 메모리 시스템 |
US10957377B2 (en) | 2018-12-26 | 2021-03-23 | Micron Technology, Inc. | Apparatuses and methods for distributed targeted refresh operations |
CN113767435A (zh) | 2019-02-22 | 2021-12-07 | 美光科技公司 | 存储器装置接口及方法 |
US11615831B2 (en) | 2019-02-26 | 2023-03-28 | Micron Technology, Inc. | Apparatuses and methods for memory mat refresh sequencing |
US11227649B2 (en) | 2019-04-04 | 2022-01-18 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of targeted refresh operations |
US11335383B2 (en) * | 2019-05-31 | 2022-05-17 | Micron Technology, Inc. | Memory component for a system-on-chip device |
US11069393B2 (en) | 2019-06-04 | 2021-07-20 | Micron Technology, Inc. | Apparatuses and methods for controlling steal rates |
US10978132B2 (en) | 2019-06-05 | 2021-04-13 | Micron Technology, Inc. | Apparatuses and methods for staggered timing of skipped refresh operations |
US11302374B2 (en) | 2019-08-23 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic refresh allocation |
US11302377B2 (en) | 2019-10-16 | 2022-04-12 | Micron Technology, Inc. | Apparatuses and methods for dynamic targeted refresh steals |
EP4081954A4 (en) | 2019-12-27 | 2023-04-05 | Micron Technology, Inc. | NEUROMORPHIC STORAGE DEVICE AND METHOD |
KR20220116258A (ko) | 2019-12-30 | 2022-08-22 | 마이크론 테크놀로지, 인크. | 메모리 디바이스 인터페이스 및 방법 |
EP4085459A4 (en) | 2019-12-31 | 2024-02-21 | Micron Technology, Inc. | MEMORY MODULE MULTI-PORT BUFFER TECHNIQUES |
WO2021143069A1 (zh) * | 2020-01-14 | 2021-07-22 | 长鑫存储技术有限公司 | 集成电路结构和存储器 |
CN113129942A (zh) * | 2020-01-14 | 2021-07-16 | 长鑫存储技术有限公司 | 集成电路结构和存储器 |
JP2021140837A (ja) * | 2020-03-02 | 2021-09-16 | キオクシア株式会社 | 半導体記憶装置 |
CN113838514B (zh) | 2020-04-28 | 2024-02-27 | 长江存储科技有限责任公司 | 存储器件及其擦除和验证方法 |
CN112102874B (zh) * | 2020-08-13 | 2024-02-06 | 深圳市宏旺微电子有限公司 | Dram测试系统、测试方法和装置 |
US11309010B2 (en) | 2020-08-14 | 2022-04-19 | Micron Technology, Inc. | Apparatuses, systems, and methods for memory directed access pause |
US11380382B2 (en) | 2020-08-19 | 2022-07-05 | Micron Technology, Inc. | Refresh logic circuit layout having aggressor detector circuit sampling circuit and row hammer refresh control circuit |
US11348631B2 (en) | 2020-08-19 | 2022-05-31 | Micron Technology, Inc. | Apparatuses, systems, and methods for identifying victim rows in a memory device which cannot be simultaneously refreshed |
CN114115437B (zh) | 2020-08-26 | 2023-09-26 | 长鑫存储技术有限公司 | 存储器 |
CN114115441B (zh) * | 2020-08-26 | 2024-05-17 | 长鑫存储技术有限公司 | 存储器 |
CN114115439A (zh) | 2020-08-26 | 2022-03-01 | 长鑫存储技术有限公司 | 存储器 |
KR20220028888A (ko) * | 2020-08-31 | 2022-03-08 | 에스케이하이닉스 주식회사 | 저장 장치 및 그 동작 방법 |
US11557331B2 (en) | 2020-09-23 | 2023-01-17 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh operations |
US11222686B1 (en) | 2020-11-12 | 2022-01-11 | Micron Technology, Inc. | Apparatuses and methods for controlling refresh timing |
US11264079B1 (en) | 2020-12-18 | 2022-03-01 | Micron Technology, Inc. | Apparatuses and methods for row hammer based cache lockdown |
US11532353B2 (en) * | 2021-01-29 | 2022-12-20 | Arm Limited | Circuitry apportioning of an integrated circuit |
US11710514B2 (en) * | 2021-10-04 | 2023-07-25 | Micron Technology, Inc. | Delay of self-refreshing at memory die |
CN114664336B (zh) * | 2022-03-21 | 2023-01-10 | 珠海博雅科技股份有限公司 | 堆叠存储器件、存储芯片及其控制方法 |
CN115360159B (zh) * | 2022-10-19 | 2023-01-31 | 北京登临科技有限公司 | 集成电路封装体、协处理器芯片、印制电路板、板卡和电子设备 |
Family Cites Families (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5138438A (en) * | 1987-06-24 | 1992-08-11 | Akita Electronics Co. Ltd. | Lead connections means for stacked tab packaged IC chips |
US5198888A (en) * | 1987-12-28 | 1993-03-30 | Hitachi, Ltd. | Semiconductor stacked device |
JPH02290048A (ja) | 1989-02-15 | 1990-11-29 | Matsushita Electric Ind Co Ltd | 積層型半導体の実装方法 |
EP0713609B1 (en) * | 1993-08-13 | 2003-05-07 | Irvine Sensors Corporation | Stack of ic chips as substitute for single ic chip |
US5561622A (en) * | 1993-09-13 | 1996-10-01 | International Business Machines Corporation | Integrated memory cube structure |
JP2001110978A (ja) | 1999-10-04 | 2001-04-20 | Seiko Epson Corp | 半導体装置の実装構造 |
US6683372B1 (en) * | 1999-11-18 | 2004-01-27 | Sun Microsystems, Inc. | Memory expansion module with stacked memory packages and a serial storage unit |
JP3822768B2 (ja) * | 1999-12-03 | 2006-09-20 | 株式会社ルネサステクノロジ | Icカードの製造方法 |
JP3768761B2 (ja) * | 2000-01-31 | 2006-04-19 | 株式会社日立製作所 | 半導体装置およびその製造方法 |
JP3980807B2 (ja) | 2000-03-27 | 2007-09-26 | 株式会社東芝 | 半導体装置及び半導体モジュール |
KR100468761B1 (ko) * | 2002-08-23 | 2005-01-29 | 삼성전자주식회사 | 분할된 시스템 데이터 버스에 연결되는 메모리 모듈을구비하는 반도체 메모리 시스템 |
JP4419049B2 (ja) | 2003-04-21 | 2010-02-24 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
JP4205553B2 (ja) * | 2003-11-06 | 2009-01-07 | エルピーダメモリ株式会社 | メモリモジュール及びメモリシステム |
US7200021B2 (en) * | 2004-12-10 | 2007-04-03 | Infineon Technologies Ag | Stacked DRAM memory chip for a dual inline memory module (DIMM) |
-
2005
- 2005-03-30 JP JP2005098027A patent/JP4309368B2/ja not_active Expired - Fee Related
-
2006
- 2006-03-30 US US11/392,805 patent/US7466577B2/en active Active
- 2006-03-30 CN CN200610071011.4A patent/CN100570738C/zh not_active Expired - Fee Related
Cited By (60)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012238376A (ja) * | 2005-09-02 | 2012-12-06 | Metallum Inc | Dramをスタックする方法及び装置 |
US10885971B2 (en) | 2006-12-14 | 2021-01-05 | Rambus Inc. | Multi-die memory device |
US11195572B2 (en) | 2006-12-14 | 2021-12-07 | Rambus Inc. | Multi-die memory device |
KR101533120B1 (ko) * | 2006-12-14 | 2015-07-01 | 램버스 인코포레이티드 | 멀티 다이 메모리 디바이스 |
US9082463B2 (en) | 2006-12-14 | 2015-07-14 | Rambus Inc. | Multi-die memory device |
US10607691B2 (en) | 2006-12-14 | 2020-03-31 | Rambus Inc. | Multi-die memory device |
US11657868B2 (en) | 2006-12-14 | 2023-05-23 | Rambus Inc. | Multi-die memory device |
JP2010514080A (ja) * | 2006-12-14 | 2010-04-30 | ラムバス・インコーポレーテッド | マルチダイメモリ素子 |
US9324411B2 (en) | 2006-12-14 | 2016-04-26 | Rambus Inc. | Multi-die memory device |
US11990177B2 (en) | 2006-12-14 | 2024-05-21 | Rambus Inc. | Multi-die memory device |
US9818470B2 (en) | 2006-12-14 | 2017-11-14 | Rambus Inc. | Multi-die memory device |
US7830692B2 (en) | 2007-10-04 | 2010-11-09 | Samsung Electronics Co., Ltd. | Multi-chip memory device with stacked memory chips, method of stacking memory chips, and method of controlling operation of multi-chip package memory |
KR101416315B1 (ko) | 2007-11-09 | 2014-07-08 | 삼성전자주식회사 | 내부 전압 제어 방법 및 그 방법을 이용하는 멀티 칩패키지 메모리 |
JP2009301415A (ja) * | 2008-06-16 | 2009-12-24 | Nec Corp | メモリモジュール制御方法及びメモリモジュール並びにデータ転送装置 |
JP2010045762A (ja) * | 2008-08-08 | 2010-02-25 | Hynix Semiconductor Inc | 半導体集積回路及びその制御方法 |
US9218871B2 (en) | 2009-05-26 | 2015-12-22 | Ps4 Luxco S.A.R.L. | Semiconductor memory device, information processing system including the same, and controller |
JP2010277620A (ja) * | 2009-05-26 | 2010-12-09 | Elpida Memory Inc | 半導体記憶装置及びこれを備える情報処理システム並びにコントローラ |
US8601188B2 (en) | 2009-10-09 | 2013-12-03 | Elpida Memory, Inc. | Semiconductor device, control method for the semiconductor device and information processing system including the same |
JP2011081881A (ja) * | 2009-10-09 | 2011-04-21 | Elpida Memory Inc | 半導体記憶装置及びデータ処理システム |
US8904071B2 (en) | 2009-10-09 | 2014-12-02 | Ps4 Luxco S.A.R.L. | Semiconductor device, control method for the semiconductor device and information processing system including the same |
US8473653B2 (en) | 2009-10-09 | 2013-06-25 | Elpida Memory, Inc. | Semiconductor device, control method for the semiconductor device and information processing system including the same |
JP2015111425A (ja) * | 2009-12-31 | 2015-06-18 | インテル コーポレイション | ハイブリッドメモリのためのシステム、方法及び装置 |
US9886343B2 (en) | 2009-12-31 | 2018-02-06 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
JP2013516020A (ja) * | 2009-12-31 | 2013-05-09 | インテル コーポレイション | ハイブリッドメモリのためのシステム、方法及び装置 |
KR101454090B1 (ko) * | 2009-12-31 | 2014-10-22 | 인텔 코포레이션 | 하이브리드 메모리를 위한 시스템, 방법 및 장치 |
US11003534B2 (en) | 2009-12-31 | 2021-05-11 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US8984189B2 (en) | 2009-12-31 | 2015-03-17 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US10956268B2 (en) | 2009-12-31 | 2021-03-23 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
US10621043B2 (en) | 2009-12-31 | 2020-04-14 | Intel Corporation | Systems, methods, and apparatuses for stacked memory |
JP2012059348A (ja) * | 2010-09-03 | 2012-03-22 | Samsung Electronics Co Ltd | 半導体メモリ装置 |
JP2012099189A (ja) * | 2010-11-04 | 2012-05-24 | Elpida Memory Inc | 半導体装置 |
US8737160B2 (en) | 2010-11-04 | 2014-05-27 | Junichi Hayashi | Semiconductor device |
US9047979B2 (en) | 2011-01-17 | 2015-06-02 | Ps4 Luxco S.A.R.L. | Semiconductor device including plural chips stacked to each other |
US8797822B2 (en) | 2011-01-17 | 2014-08-05 | Ps4 Luxco S.A.R.L. | Semiconductor device including plural chips stacked to each other |
JP2012150565A (ja) * | 2011-01-17 | 2012-08-09 | Elpida Memory Inc | 半導体装置 |
JP2012155641A (ja) * | 2011-01-28 | 2012-08-16 | Elpida Memory Inc | 半導体装置 |
US9378775B2 (en) | 2011-01-28 | 2016-06-28 | Ps4 Luxco S.A.R.L. | Semiconductor device including plural chips stacked to each other |
JP2012209497A (ja) * | 2011-03-30 | 2012-10-25 | Elpida Memory Inc | 半導体装置 |
US8913459B2 (en) | 2011-03-31 | 2014-12-16 | Ps4 Luxco S.A.R.L. | Semiconductor device including plural chips stacked to each other |
US8693230B2 (en) | 2011-03-31 | 2014-04-08 | Elpida Memory, Inc. | Semiconductor device including plural chips stacked to each other |
JP2012221540A (ja) * | 2011-04-13 | 2012-11-12 | Elpida Memory Inc | 半導体装置及びシステム |
US8958259B2 (en) | 2011-04-13 | 2015-02-17 | Ps4 Luxco S.A.R.L. | Device performing refresh operations of memory areas |
US9209160B2 (en) | 2011-07-20 | 2015-12-08 | Samsung Electronics Co., Ltd. | Semiconductor devices compatible with mono-rank and multi-ranks |
US9424906B2 (en) | 2011-11-02 | 2016-08-23 | Kabushiki Kaisha Toshiba | Timing controller with delay time units for a semiconductor storage device |
JP2013097843A (ja) * | 2011-11-02 | 2013-05-20 | Toshiba Corp | 半導体記憶装置 |
US9025400B2 (en) | 2011-11-02 | 2015-05-05 | Kabushiki Kaisha Toshiba | Semiconductor storage device |
JP2015521337A (ja) * | 2012-06-28 | 2015-07-27 | インテル・コーポレーション | Dramにおける電力低減のための構成 |
US9361970B2 (en) | 2012-06-28 | 2016-06-07 | Intel Corporation | Configuration for power reduction in DRAM |
US10424355B2 (en) | 2012-06-29 | 2019-09-24 | SK Hynix Inc. | Semiconductor integrated circuit including master chip and slave chip that are stacked |
KR102058509B1 (ko) * | 2012-06-29 | 2019-12-24 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
US10255957B2 (en) | 2012-06-29 | 2019-04-09 | SK Hynix Inc. | Semiconductor integrated circuit |
KR20140003234A (ko) * | 2012-06-29 | 2014-01-09 | 에스케이하이닉스 주식회사 | 반도체 집적회로 |
JP2016526724A (ja) * | 2013-07-01 | 2016-09-05 | インテル・コーポレーション | 不整合信号受信器に対するタイミング制御 |
US9230610B2 (en) | 2013-12-09 | 2016-01-05 | Samsung Electronics Co., Ltd. | Semiconductor memory device for use in multi-chip package |
JPWO2016038748A1 (ja) * | 2014-09-12 | 2017-06-29 | 株式会社東芝 | 記憶装置 |
US11309290B2 (en) | 2019-10-04 | 2022-04-19 | Honda Motor Co., Ltd. | Semiconductor apparatus including penetration electrodes connecting laminated semiconductor chips |
US11302379B2 (en) | 2019-10-04 | 2022-04-12 | Honda Motor Co., Ltd. | Semiconductor apparatus |
US11456028B2 (en) | 2020-03-06 | 2022-09-27 | Honda Motor Co., Ltd. | Semiconductor device and control method thereof |
CN114115440B (zh) * | 2020-08-26 | 2023-09-12 | 长鑫存储技术有限公司 | 存储器 |
CN114115440A (zh) * | 2020-08-26 | 2022-03-01 | 长鑫存储技术有限公司 | 存储器 |
Also Published As
Publication number | Publication date |
---|---|
CN100570738C (zh) | 2009-12-16 |
JP4309368B2 (ja) | 2009-08-05 |
CN1841551A (zh) | 2006-10-04 |
US7466577B2 (en) | 2008-12-16 |
US20060233012A1 (en) | 2006-10-19 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4309368B2 (ja) | 半導体記憶装置 | |
US10014037B2 (en) | Semiconductor memory package including memory device with inverting circuit | |
US8542516B2 (en) | Semiconductor system | |
US8467217B2 (en) | Semiconductor device | |
US20130021856A1 (en) | Semiconductor device | |
JP2012003795A (ja) | 半導体記憶装置及びメモリコントローラ、並びにこれらを含むデータ処理システム | |
JPH05250866A (ja) | メモリモジュール | |
KR100533976B1 (ko) | 멀티-포트 메모리 소자 | |
CN116110451A (zh) | 存储器件以及包括该存储器件的存储系统 | |
US7894231B2 (en) | Memory module and data input/output system | |
US11289135B1 (en) | Precharge timing control | |
KR20140113117A (ko) | 비대칭 액세스 타임을 가진 반도체 메모리 장치 | |
US20120146409A1 (en) | Semiconductor device having data output buffers | |
KR102458340B1 (ko) | 메모리 장치 | |
US20210103533A1 (en) | Memory system and memory chip | |
JP2015170376A (ja) | 半導体装置及びこれを備える情報処理システム | |
JP2014232555A (ja) | 半導体装置 | |
US8238133B2 (en) | Semiconductor device with a selection circuit selecting a specific pad | |
JP2012257024A (ja) | 半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20081209 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20090204 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20090414 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20090507 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4309368 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20120515 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130515 Year of fee payment: 4 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313117 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130515 Year of fee payment: 4 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140515 Year of fee payment: 5 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R360 | Written notification for declining of transfer of rights |
Free format text: JAPANESE INTERMEDIATE CODE: R360 |
|
R371 | Transfer withdrawn |
Free format text: JAPANESE INTERMEDIATE CODE: R371 |
|
S111 | Request for change of ownership or part of ownership |
Free format text: JAPANESE INTERMEDIATE CODE: R313113 |
|
R350 | Written notification of registration of transfer |
Free format text: JAPANESE INTERMEDIATE CODE: R350 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
LAPS | Cancellation because of no payment of annual fees |