JP4205553B2 - メモリモジュール及びメモリシステム - Google Patents
メモリモジュール及びメモリシステム Download PDFInfo
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- JP4205553B2 JP4205553B2 JP2003376852A JP2003376852A JP4205553B2 JP 4205553 B2 JP4205553 B2 JP 4205553B2 JP 2003376852 A JP2003376852 A JP 2003376852A JP 2003376852 A JP2003376852 A JP 2003376852A JP 4205553 B2 JP4205553 B2 JP 4205553B2
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Description
Rich Warmke, "Yellowstone, A Next Generation memory Signaling Technology" RAMBUS DEVELOPER FORUM, OCTBER 29, 2002, [平成15年10月30日検索]、インターネット<URL:http://rambus.com/rdf/rdf2002/pdf/rdf#consumer#track.pdf>
前記モジュール基板に設けられた配線と前記メモリチップとを接続する前記パッケージ基板内の配線が、同一のパッケージ基板の両面に搭載された前記メモリチップ同士を接続する第一の配線と、第一の配線の中間から分岐して前記モジュール基板に設けられた配線と平行に延伸する第二の配線から構成され、
前記第二の配線の延伸方向が、前記モジュール基板の一方の面に搭載された積層メモリと他方の面に搭載された積層メモリとで、互いに反対方向である構成である。
電源電圧または接地電位を出力するためのジャンパー配線が搭載可能なジャンパチップと、
前記ジャンパチップの出力電位にしたがって前記chip select信号をデコードし、前記メモリチップにデコード結果をそれぞれ供給するデコード回路と、
を有していてもよく、
電源電圧または接地電位を出力するためのヒューズが溶断可能に搭載されたジャンパチップと、
前記ジャンパチップの出力電位にしたがって前記chip select信号をデコードし、前記メモリチップにデコード結果をそれぞれ供給するデコード回路と、
を有していてもよい。
データを出力するためのドライバ回路、及びデータ入力時に配線端を終端する終端回路として共用されるドライバ兼用終端回路を有していてもよい。
前記メモリモジュールが搭載されるスロットと、
前記メモリモジュールとそれぞれ独立に接続され、複数の該メモリモジュールに対する同時アクセスを可能にするメモリコントローラと、
を有する構成である。
第1の実施の形態のメモリモジュールは、モジュール基板に搭載するメモリとして積層メモリを用い、2つのメモリ(メモリチップ)で信号端子を共有化(統合)するとともに、積層メモリどうしの配置間隔を広げてDQ信号配線の配線自由度を確保した構成である。
第1の実施の形態のメモリモジュールでは、メモリモジュールに搭載する積層メモリとして図3に示すような一般的なものを用いると、daisy chainバスに対して所定の間隔毎にメモリ4つ分の負荷が接続されることになるため、線路の特性インピーダンスが局所的に大きく変化し、daisy chainバスで伝送されるCA信号等の波形が劣化するおそれがある。
図9は本発明のメモリモジュールの第3の実施の形態に搭載する積層メモリの構成を示す側断面図である。
積層メモリのDQ信号端子は、通常、データ入力及びデータ出力で共用されるため、DQ信号端子にはデータを出力するためのドライバ回路が接続されている。ドライバ回路は、一般にMOSトランジスタを用いて構成され、このMOSトランジスタのドレインの拡散層容量がpoint to pointバスに対して容量性負荷として接続されることになる。ドライバ回路による容量性負荷は、メモリチップのCA信号端子の入力容量よりも大きい。したがって、4rank構成のメモリモジュールでは、DQ信号配線にメモリチップ4つ分の大きな容量性負荷が接続されることになるため、DQ信号の高速伝送が困難になるおそれがある。
図16は本発明のメモリモジュールの第5の実施の形態の構成を示す図であり、同図(a)は側断面図、同図(b)は平面図である。
図17は本発明のメモリシステムの一構成例を示すブロック図である。
図18は本発明の第7の実施の形態のメモリモジュールに搭載する積層メモリの構成を示す図であり、同図(a)は積層メモリの側断面図、同図(b)はモジュール基板と積層メモリ間のDQ信号配線接続を示す側断面図、同図(c)はモジュール基板と積層メモリ間のCA信号配線接続を示す側断面図である。
2、12、22、42 モジュール基板
3、13、23、43、63、300 積層メモリ
24 方向性結合器
25 ODT
26 コンパレータ
27 CA信号端子領域
28 DQ信号端子領域
30 ドライバ回路
44 ヒートスプレッダ
52 メモリコントローラ
301、311、401 パッケージ基板
302、312 第1のメモリチップ
303、313 第2のメモリチップ
304 封止材
305、315、405 ボール端子
306 電源/GND層
307、318 信号配線
308、319 ビアホール
309、320 チップパッド
316 電源層
317 GND層
322 ジャンパチップ
323 デコード回路
324 第1のセレクタ
325 第2のセレクタ
326 論理積回路
401 インターポーザ
402 メモリチップ
408 スルーホール
Claims (18)
- パッケージ基板の両面に複数のメモリチップを備える積層メモリが、モジュール基板の両面に搭載されるメモリモジュールにおいて、
前記モジュール基板に設けられた配線と前記メモリチップとを接続する前記パッケージ基板内の配線が、同一のパッケージ基板の両面に搭載された前記メモリチップ同士を接続する第一の配線と、第一の配線の中間から分岐して前記モジュール基板に設けられた配線と平行に延伸する第二の配線から構成され、
前記第二の配線の延伸方向が、前記モジュール基板の一方の面に搭載された積層メモリと他方の面に搭載された積層メモリとで、互いに反対方向であるメモリモジュール。 - 前記第一の配線が、前記パッケージ基板に設けられたビアホールを介して前記メモリチップ同士を接続する請求項1記載のメモリモジュール。
- 前記第一の配線が、前記メモリチップの周辺近傍で前記パッケージ基板の両面に搭載された前記メモリチップ同士を接続している請求項1または2記載のメモリモジュール。
- 前記第一の配線が、前記メモリチップの端部で前記パッケージ基板の両面に搭載された前記メモリチップ同士を接続している請求項1または2記載のメモリモジュール。
- 前記第二の配線と前記モジュール基板の配線とが、前記パッケージ基板上に設けられたボール端子を介して接続される請求項1から4のいずれか1項記載のメモリモジュール。
- 前記ボール端子が前記パッケージ基板の周辺近傍に設けられている請求項5記載のメモリモジュール。
- 前記ボール端子が前記パッケージ基板の端部に設けられている請求項5記載のメモリモジュール。
- 前記配線が、chip select信号配線、command address信号配線またはclock信号のいずれか一つに使用される請求項1から7のいずれか1項記載のメモリモジュール。
- 前記配線が、chip select信号配線及びcommand address信号配線に使用される請求項1から7のいずれか1項記載のメモリモジュール。
- 前記積層メモリが、少なくとも該積層メモリ一つ分の間隔を有して前記モジュール基板の一方の面及び他方の面にそれぞれ搭載されている請求項1から9のいずれか1項記載のメモリモジュール。
- 前記積層メモリに外部から供給される複数ビットからなるchip select信号のコードに対応して複数のメモリチップのうちのいずれか一つをアクティブに設定するためのコード設定手段を前記積層メモリに有する請求項1から10のいずれか1項記載のメモリモジュール。
- 前記コード設定手段は、
電源電圧または接地電位を出力するためのジャンパー配線が搭載可能なジャンパチップと、
前記ジャンパチップの出力電位にしたがって前記chip select信号をデコードし、前記メモリチップにデコード結果をそれぞれ供給するデコード回路と、
を有する請求項11記載のメモリモジュール。 - 前記コード設定手段は、
電源電圧または接地電位を出力するためのヒューズが溶断可能に搭載されたジャンパチップと、
前記ジャンパチップの出力電位にしたがって前記chip select信号をデコードし、前記メモリチップにデコード結果をそれぞれ供給するデコード回路と、
を有する請求項11記載のメモリモジュール。 - 前記モジュール基板の一方の面に搭載された積層メモリが有するメモリチップと、前記モジュール基板の他方の面に搭載された積層メモリが有するメモリチップとが交互に同時選択されるように、前記メモリチップをアクティブに設定するためのchip select信号配線が前記積層メモリとそれぞれ接続された請求項11から13のいずれか1項記載のメモリモジュール。
- 前記メモリチップは、
データを出力するためのドライバ回路、及びデータ入力時に配線端を終端する終端回路として共用されるドライバ兼用終端回路を有する請求項1から14のいずれか1項記載のメモリモジュール。 - 4つのメモリチップが同時にアクティブに設定される4rank構成である請求項1から15のいずれか1項記載のメモリモジュール。
- 前記配線が、daisy chainバスの一部である請求項1から16のいずれか1項記載のメモリモジュール。
- 請求項1〜17のいずれか1項に記載のメモリモジュールと、
前記メモリモジュールが搭載されるスロットと、
前記メモリモジュールとそれぞれ独立に接続され、複数の該メモリモジュールに対する同時アクセスを可能にするメモリコントローラと、
を有するメモリシステム。
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JPH07202120A (ja) | 1993-12-28 | 1995-08-04 | Hitachi Ltd | 高放熱型メモリおよび高放熱型メモリモジュール |
KR100647189B1 (ko) | 1996-12-19 | 2007-08-16 | 텍사스 인스트루먼츠 인코포레이티드 | 선택가능메모리모듈및그동작방법 |
JP3820843B2 (ja) | 1999-05-12 | 2006-09-13 | 株式会社日立製作所 | 方向性結合式メモリモジュール |
JP2001053243A (ja) * | 1999-08-06 | 2001-02-23 | Hitachi Ltd | 半導体記憶装置とメモリモジュール |
US6713854B1 (en) * | 2000-10-16 | 2004-03-30 | Legacy Electronics, Inc | Electronic circuit module with a carrier having a mounting pad array |
-
2003
- 2003-11-06 JP JP2003376852A patent/JP4205553B2/ja not_active Expired - Fee Related
-
2004
- 2004-11-02 CN CNB2004100901076A patent/CN100474433C/zh not_active Expired - Fee Related
- 2004-11-03 US US10/979,157 patent/US7102905B2/en not_active Expired - Fee Related
- 2004-11-04 TW TW093133576A patent/TWI299499B/zh not_active IP Right Cessation
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9773527B2 (en) | 2014-09-12 | 2017-09-26 | Toshiba Memory Corporation | Semiconductor device |
US10820419B2 (en) | 2018-05-30 | 2020-10-27 | Samsung Electronics Co., Ltd. | Memory system and storage device including printed circuit board where channel groups have both point to point topology and daisy chain topology |
US11277916B2 (en) | 2018-05-30 | 2022-03-15 | Samsung Electronics Co., Ltd. | Memory system and storage device including printed circuit board with subset of channels arranged in point-to-point topology and subset of channels arranged in daisy-chain topology |
Also Published As
Publication number | Publication date |
---|---|
TWI299499B (en) | 2008-08-01 |
TW200537516A (en) | 2005-11-16 |
CN100474433C (zh) | 2009-04-01 |
JP2005141829A (ja) | 2005-06-02 |
CN1614713A (zh) | 2005-05-11 |
US20050099834A1 (en) | 2005-05-12 |
US7102905B2 (en) | 2006-09-05 |
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