CN113557570A - 具有存储地址信号的cam的半导体装置 - Google Patents

具有存储地址信号的cam的半导体装置 Download PDF

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CN113557570A
CN113557570A CN202080019880.0A CN202080019880A CN113557570A CN 113557570 A CN113557570 A CN 113557570A CN 202080019880 A CN202080019880 A CN 202080019880A CN 113557570 A CN113557570 A CN 113557570A
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榎本穗乃香
诸桥圣
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Abstract

本文揭示的是一种设备，其包含：多个地址寄存器，其各自存储地址信号；多个计数器电路，其各自存储对应于所述地址寄存器中的相关联一者的计数值；第一电路，其响应于第一信号而周期性地选择所述地址寄存器中的一者；第二电路，其基于所述计数器电路中的每一者的所述计数值来选择所述地址寄存器中的一者；及第三电路，其在所述第一及第二电路选择所述地址寄存器中的相同一者时激活第二信号。

Description

具有存储地址信号的CAM的半导体装置
背景技术
在例如DRAM(动态随机存取存储器)的半导体装置中，存取集中在同一字线上可导致连接到邻近字线上的存储器单元的信息保持特性的劣化。因此，在一些情况下，除正常刷新操作之外还执行存储器单元的刷新操作以防止连接到邻近字线的存储器单元的信息丢失。此额外刷新操作称为“行锤刷新操作”。
对邻近于存取集中在其处的字线的字线执行行锤刷新操作。为实现此操作，将存取集中在其处的多个字线的地址存储在存储电路的地址中，并且在行锤刷新操作的时间从地址存储电路读取地址中的一者。然而，当将执行行锤刷新操作时，将读取存储在地址存储电路中的地址中的哪一者是待处置的问题。
发明内容
本文揭示包含用于存储地址信号的存储器的实例设备。在本公开的方面中，一种设备包含多个地址寄存器，其各自经配置以存储地址信号；多个计数器电路，其各自经配置以存储对应于所述地址寄存器中的相关联一者的计数值；第一电路，其经配置以响应于第一信号而周期性地选择所述地址寄存器中的一者；第二电路，其经配置以基于所述计数器电路中的每一者的计数值来选择所述地址寄存器中的一者；及第三电路，其经配置以在所述第一及第二电路选择所述地址寄存器中的相同一者时激活第二信号。
在本公开的另一方面中，一种设备包含多个地址寄存器，其包含各自存储地址信号的至少第一、第二及第三地址寄存器；第一电路，其经配置以响应于第一信号而选择所述地址寄存器中的一者；及地址转换器，其经配置以基于存储在由所述第一电路选择的所述地址寄存器中的一者中的所述地址信号来产生刷新地址。所述第一电路经配置以在第二信号被去激活时以此顺序选择所述第一、第二及第三地址寄存器。所述第一电路经配置以在所述第二信号被激活时以此顺序选择所述第一及第三地址寄存器而不选择所述第二地址寄存器。
在本公开的另一方面中，一种设备包含多个地址寄存器；多个计数器电路，其对应于所述多个地址寄存器被提供，所述多个计数器电路中的每一者经配置以响应于检测对存储在所述多个地址寄存器中的相关联的一者中的地址信号的存取而更新计数值；第一电路，其经配置以基于所述多个计数器电路的所述计数值来选择所述多个地址寄存器中的一者；第二电路，其经配置以选择所述多个地址寄存器中的一者，而与所述多个计数器电路的所述计数值无关；及第三电路，其经配置以在由所述第一电路及所述第二电路连续地选择所述多个地址寄存器中的相同一者时激活跳过信号。
附图说明
图1是根据本公开的实施例的半导体装置的框图。
图2是用于解释刷新控制电路的配置的框图。
图3是用于解释存取集中在其处的字线的地址与将对其执行行锤刷新操作的字线的地址之间的关系的示意图。
图4是用于解释存储电路的行锤地址的配置的框图。
图5是用于解释控制电路的配置的框图。
图6是用于解释控制电路的操作的时序图。
图7A及7B是分别展示其中响应于一个刷新命令而执行多个刷新操作的实例的时序图。
图8是LFSR电路的电路图的实例。
具体实施方式
下面将参考附图详细解释本发明的各种实施例。下文详细描述参考附图，所述附图通过说明的方式展示可在其中实践本发明的特定方面及实施例。对这些实施例进行足够详细的描述，以使所属领域的技术人员能够实践本发明。可利用其它实施例，且可在不背离本发明的范围的情况下进行结构、逻辑及电改变。本文中公开的各种实施例不一定互斥，因为一些所揭示实施例可与一或多个其它所揭示实施例组合以形成新实施例。
图1是根据本公开的实施例的半导体装置10的框图。举例来说，半导体装置10可为并入在单个半导体芯片中的DDR4 SDRAM。半导体装置10可安装在外部衬底上，例如存储器模块衬底或母板。如在图1中展示，半导体装置10包含存储器单元阵列11。存储器单元阵列11包含多个字线WL、多个位线BL及布置在字线WL及位线BL的相交点处的多个存储器单元MC。字线WL的选择由行地址控制电路12执行，且位线BL的选择由列解码器13执行。感测放大器14连接到对应位线BL及一对本地I/O线LIOT/B。所述对本地I/O线LIOT/B经由用作开关的转移门15连接到一对主I/O线MIOT/B。存储器单元阵列11被划分为包含存储器存储体BANK0到BANKm的(m+1)个存储器存储体。
包含在半导体装置10中的多个外部端子包含命令地址端子21、时钟端子22、数据端子23及电力供应端子24及25。数据端子23连接到I/O电路16。
命令地址信号CA被供应到命令地址端子21。与地址相关的供应到命令地址端子21的命令地址信号CA中的一者经由命令地址输入电路31被转移到地址解码器32。与命令相关的另一者经由命令地址输入电路31被转移到命令控制电路33。地址解码器32解码地址信号并产生行地址XADD及列地址YADD。行地址XADD被供应到行地址控制电路12，且列地址YADD被供应到列解码器13。此外，用作时钟启用信号CKE的命令地址信号CA被供应到内部时钟产生器35。
互补外部时钟信号CK及/CK被供应到时钟端子22。互补外部时钟信号CK及/CK被输入到时钟输入电路34。时钟输入电路34基于互补外部时钟信号CK及/CK产生内部时钟信号ICLK。内部时钟信号ICLK被供应到至少命令控制电路33及内部时钟产生器35。举例来说，内部时钟产生器35由时钟启用信号CKE激活，并基于内部时钟信号ICLK产生内部时钟信号LCLK。内部时钟信号LCLK被供应到I/O电路16。内部时钟信号LCLK用作时序信号，其定义在读取操作时从数据端子23输出读取数据DQ的时序。在写入操作中，从外部将写入数据输入到数据端子23。在写入操作中，可从外部将数据掩码信号DM输入到数据端子23。
电力供应电势VDD及VSS被供应到电力供应端子24。这些电力供应电势VDD及VSS被供应到电压产生器36。电压产生器36例如基于电力供应电势VDD及VSS产生各种内部电势VPP、VOD、VARY及VPERI。内部电势VPP主要用于行地址控制电路12中。内部电势VOD及VARY主要用于包含在存储器单元阵列11中的感测放大器14中。内部电势VPERI用于许多其它电路块中。
电力供应电势VDDQ及VSSQ从电力供应端子25被供应到I/O电路16。尽管电力供应电势VDDQ及VSSQ可分别与供应到电力供应端子24的电力供应电势VDD及VSS相同，但专用电力供应电势VDDQ及VSSQ被指派给I/O电路16，以便防止在I/O电路16中产生的电力供应噪声传播到另一电路块。
命令控制电路33在发出有效命令时激活有效信号ACT，并且在发出刷新命令时激活刷新信号AREF。有效信号ACT及刷新信号AREF两者都被供应到行地址控制电路12。行地址控制电路12包含刷新控制电路40。刷新控制电路40基于行地址XADD、有效信号ACT及刷新信号AREF控制用于存储器单元阵列11的刷新操作。稍后将详细描述刷新控制电路40。
当从外部发出读取命令时，在有效命令之后，命令控制电路33激活列选择信号CYE。列选择信号CYE被供应到列解码器13。响应于此信号，从存储器单元阵列11读出读取数据。从存储器单元阵列11读取的读取数据经由读取-写入放大器17及FIFO电路18转移到I/O电路16，并且经由数据端子23输出到外部。
图2是用于解释刷新控制电路40的配置的框图。
如在图2中展示，刷新控制电路40包含刷新计数器41、ARM样本产生器42、采样电路43、行锤地址存储电路44、地址转换器45及刷新地址选择器46。刷新计数器41产生正常刷新地址NRADD。正常刷新地址NRADD响应于内部刷新信号IREF而递增或递减。内部刷新信号IREF可为基于刷新信号AREF被多次激活的信号。采样电路43在激活由ARM样本产生器42产生的采样信号SMP时以某一时序对行地址XADD进行采样，并将经采样行地址XADD供应到行锤地址存储电路44。ARM样本产生器42可在有效信号ACT被激活预定次数时以某一时序激活采样信号SMP。因此，将存取集中在其处的字线WL的地址VADD供应到行锤地址存储电路44。如稍后描述，行锤地址存储电路44存储多个行地址VADD。存储在行锤地址存储电路44中的行地址VADD被供应到地址转换器45。地址转换器45转换行地址VADD以产生行刷新地址+1ADD、-1ADD、+2ADD及-2ADD。
行锤刷新地址+1ADD及-1ADD是在两侧邻近于对其指派行地址VADD的字线WL的字线WL的地址。行锤刷新地址+2ADD及-2ADD是在两侧与对其指派行地址VADD的字线WL相距两条线的字线WL的地址。举例来说，当字线WL1到WL5以图3中展示的顺序布置并且存取集中在字线WL3处时，行地址VADD对应于字线WL3，行锤刷新地址-1ADD及+1ADD分别对应于字线WL2及WL4，且行锤刷新地址-2ADD及+2ADD分别对应于字线WL1及WL5。在行锤刷新地址+1ADD、-1ADD、+2ADD及-2ADD分别被分配到其的字线WL4、WL2、WL5及WL1中，存在相关联存储器单元MC的信息存储性能降低的可能性，这是因为存取集中在与其邻近或距离其两条线的字线WL3处。正常刷新地址NRADD及行锤刷新地址+1ADD、-1ADD、+2ADD及-2ADD被供应到刷新地址选择器46。
刷新控制电路40进一步包含计数器电路47、比较电路48及刷新状态电路49。计数器电路47响应于内部刷新信号IREF使计数值CV递增或递减。每当计数值CV达到预定值时，比较电路48接收计数值CV并激活刷新状态信号RHR State。可用模式信号MODE改变预定值。因此，当将增加行锤刷新操作的频率时用模式信号MODE将预定值设置为小值并且当将减小行锤刷新操作的频率时用模式信号MODE将预定值设置为大值就足够。当刷新状态信号RHRState被激活时，刷新计数器41可临时停止正常刷新地址NRADD的更新操作。
刷新状态信号RHR State被供应到刷新状态电路49。刷新状态电路49基于内部刷新信号IREF及刷新状态信号RHR State产生刷新选择信号NR、RHR1及RHR2。
刷新状态电路49在刷新状态信号RHR State处于非有效状态中时激活刷新选择信号NR。刷新选择信号NR是在将执行正常刷新操作时激活的信号。在刷新选择信号NR被激活的情况下，刷新地址选择器46选择从刷新计数器41输出的正常刷新地址NRADD，并输出正常刷新地址NRADD作为刷新地址REFADD。在刷新状态信号RHR State处于有效状态中时，刷新状态电路49激活刷新选择信号RHR1或RHR2。刷新选择信号RHR1是在将对邻近于存取集中在其处的字线WL3的字线WL2及WL4执行行锤刷新操作时激活的信号。在刷新选择信号RHR1激活的情况下，刷新地址选择器46选择从地址转换器45输出的行锤刷新地址+1ADD及-1ADD，并输出行锤刷新地址+1ADD及-1ADD作为刷新地址REFADD。刷新选择信号RHR1还被供应到行锤地址存储电路44。刷新选择信号RHR2是在将对距离存取集中在其处的字线WL3两条线的字线WL1及WL5执行行锤刷新操作时激活的信号。在刷新选择信号RHR2被激活的情况下，刷新地址选择器46选择从地址转换器45输出的行锤刷新地址+2ADD及-2ADD，并输出行锤刷新地址+2ADD及-2ADD作为刷新地址REFADD。
图4是用于解释行锤地址存储电路44的配置的框图。
如在图4中展示，行锤地址存储电路44包含多个地址寄存器50到57、多个计数器电路60到67、比较电路70及控制电路80。尽管在图4中展示的实例中说明八个地址寄存器50到57，但包含在行锤地址存储电路44中的地址寄存器的数目不限于此。由采样电路43采样的行地址XADD分别存储在地址寄存器50到57中。计数器电路60到67分别对应于地址寄存器50到57。
比较电路70将输入行地址XADD与存储在地址寄存器50到57中的行地址XADD中的每一者进行比较。当输入行地址XADD与存储在地址寄存器50到57中的行地址XADD中的任一者匹配时，比较电路70激活命中信号HIT0到HIT7中的对应一者。当命中信号HIT0到HIT7中的任一者被激活时，控制电路80使计数器电路60到67中的对应一者的计数值递增。因此，计数器电路60到67的计数值指示由采样电路43分别对存储在地址寄存器50到57中的行地址XADD进行采样的次数。控制电路80包含指示计数器电路60到67中的一者具有最小计数值的最小指针81及指示计数器电路60到67中的一者具有最大计数值的最大指针82。
另一方面，当命中信号HIT0到HIT7中没有一个被激活时，即，当输入行地址XADD与分别存储在地址寄存器50到57中的行地址XADD中的任一者都不匹配时，控制电路80将由最小指针81指示的计数器电路60到67中的一者复位为初始值，并向地址寄存器50到57供应点数MIN。因此，输入行地址XADD在由点值MIN指示的地址寄存器50到57中的一者中被盖写。以此方式，当输入行地址XADD与分别存储在地址寄存器50到57中的行地址XADD中的任一者不匹配时，盖写存储存取频率最低的行地址XADD的地址寄存器50到57中的一者的值。
响应于刷新选择信号RHR1，将存储在地址寄存器50到57中的行地址XADD中的一者输出为行地址VADD。控制电路80进一步包含循序计数器83。当刷新选择信号RHR1被激活时，选择由最大指针82指示的点值MAX或由循序计数器83指示的点值SEQ。地址寄存器50到57中的一者由所选择点值SEL选择，并且存储在地址寄存器50到57中的所选择一者中的行地址XADD被输出为行地址VADD。对应于所选择点值SEL的计数器电路60到67中的一者的值被复位为初始值。
如在图5中展示，控制电路80进一步包含选择信号产生器84、多路复用器85及比较电路86。选择信号产生器84产生选择信号M/S，其具有在每次刷新选择信号RHR1被激活两次时被反转的值。选择信号M/S被供应到多路复用器85。当选择信号M/S具有一个逻辑电平(例如，低电平)时，多路复用器85选择从最大指针82输出的点值MAX，并且当选择信号M/S具有另一逻辑电平(例如，高电平)时，选择从循序计数器83输出的点值SEQ。由多路复用器85选择的点值MAX或SEQ被输出为点值SEL。点值SEL用于选择地址寄存器50到57中的一者。
由比较电路86将点值MAX与点值SEQ相互进行比较。当点值MAX及点值SEQ相互匹配时，比较电路86激活跳过信号SKIP。循序计数器83响应于跳过信号SKIP及选择信号M/S而执行递增计数操作。
图6是用于解释控制电路80的操作的时序图。
在图6中展示的实例中，刷新选择信号RHR1在时间t1到t17的每一者处被激活两次。当刷新选择信号RHR1被激活两次时，选择信号M/S被反转。因此，多路复用器85交替地选择点值MAX及点值SEQ。在图6中展示的实例中，在选择信号M/S处于低电平时选择点值MAX，且在选择信号M/S处于高电平时选择点值SEQ。因此，在时间t1、t3、t5、t7、t9、t11、t13、t15及t17处选择点值SEQ，并且在时间t2、t4、t6、t8、t10、t12、t14及t16处选择点值MAX。点值SEQ响应于选择信号M/S的下降边缘而递增。点值SEQ例如是3位信号并且从0递增7，且接着返回到0。点值MAX也是例如3位信号，且指示当前具有最大计数值的计数器电路60到67中的一者的地址。
当点值MAX及点值SEQ彼此匹配时，比较电路86激活跳过信号SKIP。在图6中展示的实例中，点值MAX及点值SEQ两者都在时间t6指示值“4”。因为响应于此激活计数信号UP，所以由循序计数器83指示的点值SEQ立即递增到“5”。因此，在下次激活刷新选择信号RHR1时产生的点值SEL指示值“5”及“4”，其为响应于先前点值MAX产生的点值SEL的值，不重复地输出。类似地，点值MAX及点值SEQ两者都在时间t12指示值“0”。响应于此而激活计数信号UP，并且相应地，由循序计数器83指示的点值SEQ立即递增“1”。因此，在下次激活刷新选择信号RHR1时产生的点值SEL指示值“1”及“0”，其为响应于先前点值MAX产生的点值SEL的值，不重复地输出。以此方式，根据本实施例，响应于先前点值MAX产生的点值SEL的值及响应于当前点值SEQ产生的点值SEL的值彼此不匹配。因此，可避免任何不必要的行锤刷新操作。
同时，即使在点值MAX及点值SEQ彼此匹配时，如果接下来选择点值MAX，那么不跳过循序计数器83的点值SEQ。举例来说，尽管点值MAX及点值SEQ两者都在时间t15指示值“2”，但是因为选择信号M/S在此时序处处于高电平，所以计数信号UP未被激活。即，点值SEQ保持在值“2”，并且不执行任何不必要的跳过操作。
如上文解释，在本实施例中，当点值MAX及点值SEQ彼此匹配时，跳过点值SEQ。因此，响应于先前点值MAX而产生的点值SEL的值及响应于当前点值SEQ产生的点值SEL的值彼此不匹配，并且可避免任何不必要的行锤刷新操作。
在本实施例中，响应于从外部发出的一个刷新命令，可在半导体装置10中执行多次刷新操作。在图7A及7B中，展示其中每次激活刷新信号AREF时执行五次刷新操作的实例。在图7A中展示的实例中，在时间t20到t24中的每一者处激活刷新信号AREF，并且每次激活刷新信号AREF时，连续激活内部刷新信号IREF五次。因为刷新状态信号RHR State在时间t20处于非有效状态，所以刷新选择信号NR与内部刷新信号IREF同步激活。在此情况下，响应于刷新信号AREF，对五个正常刷新地址NRADD循序地执行刷新操作。在时间t21，刷新状态信号RHR State是有效状态。在图7A中展示的实例中，在刷新状态信号RHR State被激活时的周期期间，刷新选择信号RHR1也与内部刷新信号IREF同步地被激活。在图7A中展示的实例中，在一个行锤刷新操作中，对12个行锤刷新地址+1ADD、-1ADD执行刷新操作。在此情况下，响应于一个刷新信号AREF而无法对12个地址执行刷新操作。因此，刷新状态信号RHRState保持在有效状态，直到对12个地址的行锤刷新操作完成。即，响应于在时间t21及时间t22激活的刷新信号AREF中的每一者而执行五个行锤刷新操作，并且响应于在时间t23激活的刷新信号AREF而执行两个行锤刷新操作。
在图7A中展示的实例中，第一及第二行锤刷新操作分别对由点值MAX指示的行地址VADD的+1ADD及-1ADD执行。第三及第四行锤刷新操作分别对由点值SEQ指示的行地址VADD的+1ADD及-1ADD执行。第五及第六行锤刷新操作分别对由点值MAX指示的行地址VADD的+1ADD及-1ADD执行。第七及第八行锤刷新操作分别对由点值SEQ指示的行地址VADD的+1ADD及-1ADD执行。第九及第十行锤刷新操作分别对由点值MAX指示的行地址VADD的+1ADD及-1ADD执行。第十一及第十二行锤刷新操作分别对由点值SEQ指示的行地址VADD的+1ADD及-1ADD执行。以此方式，每当刷新选择信号RHR1被激活两次时，交替地执行对应于点值MAX的行锤刷新操作及对应于点值SEQ的行锤刷新操作。
在图7B中展示的实例中，在时间t30到t34中的每一者处激活刷新信号AREF。在t30时间，因为刷新状态信号RHR State信号处于非有效状态，所以刷新选择信号NR被激活。在此情况下，与内部刷新信号IREF同步地对五个正常刷新地址NRADD循序地执行刷新操作。在时间t31，刷新状态信号RHR State切换到有效状态。在图7B中展示的实例中，在刷新状态信号RHR State被激活时的周期期间，激活刷新选择信号RHR1或RHR2。在图7B中展示的实例中，在一个行锤刷新操作中，对12个行锤刷新地址+1ADD、-1ADD执行刷新操作，并且对四个行锤刷新地址+2ADD、-2ADD执行刷新操作。在此情况下，因为响应于一个刷新信号AREF而不能对16个地址执行刷新操作，所以刷新状态信号RHR State保持在有效状态，直到对16个地址的行锤刷新操作完成。即，响应于在时间t31、时间t32及时间t33激活的刷新信号AREF中的每一者执行五个行锤刷新操作，并且响应于在时间t34激活的刷新信号AREF执行一个行锤刷新操作。响应于在时间t31激活的刷新信号AREF，对两个行锤刷新地址+1ADD、-1ADD执行刷新操作，并且对三个行锤刷新地址+2ADD、-2ADD执行刷新操作。响应于在时间t32激活的刷新信号AREF，对四个行锤刷新地址+1ADD、-1ADD执行刷新操作，并且对一个行锤刷新地址+2ADD、-2ADD执行刷新操作。
在图7B中展示的实例中，第一到第四行锤刷新操作分别对由点值MAX指示的行地址VADD的+2ADD、-2ADD、+1ADD及-1ADD执行。第五到第八行锤刷新操作分别对由点值SEQ指示的行地址VADD的+2ADD、-2ADD、+1ADD及-1ADD执行。第九及第十行锤刷新操作分别对由点值MAX指示的行地址VADD的+1ADD及-1ADD执行。第十一及第十二行锤刷新操作分别对由点值SEQ指示的行地址VADD的+1ADD及-1ADD执行。第十三及第十四行锤刷新操作分别对由点值MAX指示的行地址VADD的+1ADD及-1ADD执行。第十五及第十六行锤刷新操作分别对由点值SEQ指示的行地址VADD的+1ADD及-1ADD执行。
循序计数器83不需要是简单地使点值SEQ递增的计数器电路，并且可为产生伪随机数的线性反馈移位寄存器(LFSR)电路。
图8是LFSR电路90的电路图的实例。在图8中展示的实例中，LFSR电路90包含由三个触发器电路91到93及EXOR电路94构成的移位寄存器。触发器电路91到93级联连接，并且相应输出位B1到B3构成作为伪随机数的点值SEQ。位B2及位B3被输入到EXOR电路94，并且其输出在第一级处被反馈到触发器电路91。计数信号UP被共同供应到触发器电路91到93的时钟节点。复位信号RESET被共同供应到触发器电路91到93的复位或设置节点。因此，当复位信号RESET被激活时，点值SEQ的值被初始化为4。当计数值UP被激活时，点值SEQ的值被循序地更新。
尽管已在某些优选实施例及实例的上下文中揭示本发明，但所属领域的技术人员将理解，本发明超出特定揭示的实施例，延伸到本发明的其它替代实施例及/或用途以及明显修改及其等效物。另外，基于此揭示内容，本发明范围内的其它修改对于所属领域的技术人员将是显而易见的。还预期，可对实施例的特定特征及方面进行各种组合或子组合，并且仍落入本发明的范围内。应理解，所揭示实施例的各种特征及方面可彼此组合或替代，以便形成所揭示发明的变化模式。因此，希望本文所揭示的本发明的至少一些的范围不应受上文描述的特定揭示实施例的限制。

Claims (25)

1.一种设备，其包括：
多个地址寄存器，其各自经配置以存储地址信号；
多个计数器电路，其各自经配置以存储对应于所述地址寄存器中的相关联一者的计数值；
第一电路，其经配置以响应于第一信号而周期性地选择所述地址寄存器中的一者；
第二电路，其经配置以基于所述计数器电路中的每一者的计数值来选择所述地址寄存器中的一者；及
第三电路，其经配置以在所述第一及第二电路选择所述地址寄存器中的相同一者时激活第二信号。
2.根据权利要求1所述的设备，其中所述第一电路响应于所述第一及第二信号而更新所述地址寄存器的选择。
3.根据权利要求1所述的设备，其中所述第二电路选择对应于其的所述计数值指示所述计数器电路当中的最大值的所述地址寄存器中的一者。
4.根据权利要求1所述的设备，其进一步包括：
第四电路，其将输入地址与存储在所述地址寄存器中的所述地址信号进行比较；及
第五电路，其在所述第四电路检测到所述输入地址与所述地址信号中的一者匹配时更新所述地址寄存器中相应的一者的所述计数值。
5.根据权利要求4所述的设备，其中在所述第四电路检测到所述输入地址与所述地址信号中的任一者不匹配时，在所述地址寄存器中的一者中不盖写所述输入地址。
6.根据权利要求5所述的设备，其中在对应于其的所述计数值指示所述计数器电路当中的最小值的所述地址寄存器中的一者中盖写所述输入地址。
7.根据权利要求6所述的设备，其中对应于存储所述输入地址的所述地址寄存器的所述计数器电路的所述计数值被复位到初始值。
8.根据权利要求1所述的设备，其中所述第一及第二电路交替地选择所述地址寄存器中的一者。
9.根据权利要求1所述的设备，其进一步包括地址转换器，所述地址转换器基于存储在由所述第一或第二电路选择的所述地址寄存器中的一者中的所述地址信号来产生刷新地址。
10.根据权利要求1所述的设备，其中对应于所述地址寄存器中的所述所选择一者的所述计数值被复位为初始值。
11.根据权利要求1所述的设备，
其中所述第一电路包含选择所述地址寄存器中的一者的另一计数器电路，且其中所述另一计数器电路的计数值响应于所述第一信号而更新。
12.根据权利要求1所述的设备，
其中所述第一电路包含选择所述地址寄存器中的一者的线性反馈移位寄存器电路，且
其中所述线性反馈移位寄存器电路的计数值响应于所述第一信号而更新。
13.一种设备，其包括：
多个地址寄存器，其包含各自存储地址信号的至少第一、第二及第三地址寄存器；
第一电路，其经配置以响应于第一信号而选择所述地址寄存器中的一者；及
地址转换器，其经配置以基于存储在由所述第一电路选择的所述地址寄存器中的一者中的所述地址信号来产生刷新地址，
其中所述第一电路经配置以在第二信号被去激活时以此顺序选择所述第一、第二及第三地址寄存器，且
其中所述第一电路经配置以在所述第二信号被激活时以此顺序选择所述第一及第三地址寄存器而不选择所述第二地址寄存器。
14.根据权利要求13所述的设备，其进一步包括第二电路，所述第二电路基于指派给所述地址寄存器的计数值来选择所述地址寄存器中的一者，
其中所述地址转换器基于存储在由所述第一或第二电路选择的所述地址寄存器中的所述一者中的所述地址信号来产生所述刷新地址。
15.根据权利要求14所述的设备，其中所述第一及第二电路交替地选择所述地址寄存器中的一者。
16.一种设备，其包括：
多个地址寄存器，其各自经配置以存储地址信号；
第一及第二电路，其经配置以交替地选择所述地址寄存器中的一者；及
第三电路，其经配置以在所述第二电路在前一刻选择包含在所述地址寄存器中的第一地址寄存器时防止所述第一电路在后一刻立即选择所述第一地址寄存器。
17.根据权利要求16所述的设备，其中在所述第一电路在前一刻选择所述第一地址寄存器时所述第三电路不阻止所述第二电路在后一刻立即选择所述第一地址寄存器。
18.根据权利要求17所述的设备，其中所述第一电路周期性地选择所述地址寄存器中的一者。
19.根据权利要求18所述的设备，其中所述第二电路基于指派给所述地址寄存器的计数值来选择所述地址寄存器中的一者。
20.根据权利要求19所述的设备，其进一步包括地址转换器，所述地址转换器基于存储在由所述第一或第二电路选择的所述地址寄存器中的一者中的所述地址信号来产生刷新地址。
21.一种设备，其包括：
多个地址寄存器；
多个计数器电路，其对应于所述多个地址寄存器被提供，所述多个计数器电路中的每一者经配置以响应于检测对存储在所述多个地址寄存器中的相关联的一者中的地址信号的存取而更新计数值；
第一电路，其经配置以基于所述多个计数器电路的所述计数值来选择所述多个地址寄存器中的一者；
第二电路，其经配置以选择所述多个地址寄存器中的一者，而与所述多个计数器电路的所述计数值无关；及
第三电路，其经配置以在由所述第一电路及所述第二电路连续地选择所述多个地址寄存器中的相同一者时激活跳过信号。
22.根据权利要求21所述的设备，其中所述第二电路经配置以周期性地选择所述多个地址寄存器中的一者。
23.根据权利要求21所述的设备，其中所述第一电路经配置以选择对应于其的所述计数值指示所述计数器电路当中的最大值的所述地址寄存器中的一者。
24.根据权利要求21所述的设备，其中所述第一及第二电路经配置以交替地选择所述地址寄存器中的一者。
25.根据权利要求21所述的设备，其中对应于所述地址寄存器中的所述所选择一者的所述计数值被复位为初始值。
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