Classifications

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  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
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  • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
  • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
• • B—PERFORMING OPERATIONS; TRANSPORTING
  • B82—NANOTECHNOLOGY
  • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
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  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
• • C—CHEMISTRY; METALLURGY
  • C30—CRYSTAL GROWTH
  • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
  • C30B29/00—Single crystals or homogeneous polycrystalline material with defined structure characterised by the material or by their shape
  • C30B29/10—Inorganic compounds or compositions
  • C30B29/40—AIIIBV compounds wherein A is B, Al, Ga, In or Tl and B is N, P, As, Sb or Bi
  • C30B29/403—AIII-nitrides
  • C30B29/406—Gallium nitride
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  • H01L21/02494—Structure
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  • H01L21/02518—Deposited layers
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  • H01L21/02612—Formation types
  • H01L21/02617—Deposition types
  • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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  • H01L21/02617—Deposition types
  • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
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  • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
  • H01L33/005—Processes
  • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
  • H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
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  • H01S5/00—Semiconductor lasers
  • H01S5/02—Structural details or components not essential to laser action
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  • H01S5/00—Semiconductor lasers
  • H01S5/30—Structure or shape of the active region; Materials used for the active region
  • H01S5/34—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers
  • H01S5/343—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser
  • H01S5/34333—Structure or shape of the active region; Materials used for the active region comprising quantum well or superlattice structures, e.g. single quantum well [SQW] lasers, multiple quantum well [MQW] lasers or graded index separate confinement heterostructure [GRINSCH] lasers in AIIIBV compounds, e.g. AlGaAs-laser, InP-based laser with a well layer based on Ga(In)N or Ga(In)P, e.g. blue laser
• • H—ELECTRICITY
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  • H01L33/005—Processes
  • H01L33/0062—Processes for devices with an active region comprising only III-V compounds
  • H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
  • H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
• • H—ELECTRICITY
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  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S2304/00—Special growth methods for semiconductor lasers
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  • H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
  • H01S2304/00—Special growth methods for semiconductor lasers
  • H01S2304/04—MOCVD or MOVPE
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S117/00—Single-crystal, oriented-crystal, and epitaxy growth processes; non-coating apparatus therefor
  • Y10S117/901—Levitation, reduced gravity, microgravity, space
  • Y10S117/902—Specified orientation, shape, crystallography, or size of seed or substrate
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10S438/00—Semiconductor device manufacturing: process
  • Y10S438/942—Masking

Definitions

• the present invention relates to a substrate for a light-emitting device such as a light-emitting diode or a semiconductor laser, a substrate for an electronic device such as a field-effect transistor, and a method for manufacturing the same, using a nitride-based compound semiconductor such as gallium nitride (GaN). is there.
• a light-emitting device such as a light-emitting diode or a semiconductor laser
• a substrate for an electronic device such as a field-effect transistor
• GaN gallium nitride
• a stable sapphire substrate has been used in a light emitting device or the like using a nitride-based compound semiconductor.
• sapphire since sapphire has no cleavage plane, when a sapphire substrate is used for a semiconductor laser, there is a problem that a reflection plane cannot be formed by cleavage. Further, when sapphire is used as a substrate material for a light emitting device or the like, the sapphire substrate and the epitaxy layer to be grown on the sapphire substrate have a lattice mismatch between the sapphire substrate and a difference in the coefficient of thermal expansion. There is also a problem that crystal defects such as dislocations occur frequently.
• This semiconductor light emitting device is manufactured by growing a gallium nitride-based compound semiconductor layer on a semiconductor single crystal substrate such as a gallium arsenide (GaAs) substrate, and then forming a semiconductor single crystal substrate (GaAs substrate).
• a gallium nitride-based compound semiconductor layer on a semiconductor single crystal substrate such as a gallium arsenide (GaAs) substrate, and then forming a semiconductor single crystal substrate (GaAs substrate).
• gallium nitride-based compound semiconductor layer is used as a new substrate, and a gallium nitride-based compound semiconductor single crystal layer as an operation layer is epitaxially grown thereon to manufacture a semiconductor light emitting device.
• a gallium nitride-based compound Since the lattice constant and thermal expansion coefficient of the conductor layer and the gallium nitride-based compound semiconductor single crystal layer (epitaxial layer) grown thereon are very close to each other, dislocations etc. to the semiconductor single crystal layer (epiaxial layer) Lattice defects due to the occurrence are less likely to occur.
• the substrate and the active layer grown thereon are made of the same gallium nitride-based compound semiconductor layer, the same kind of crystals are aligned and can be easily cleaved. Therefore, a reflecting mirror such as a semiconductor laser can be easily manufactured. Disclosure of the invention
• the GaN substrate manufactured by the manufacturing method described in the above-mentioned Japanese Patent Application Laid-Open No. 8-116900 has extremely low crystal quality due to lattice mismatch, etc., and has an internal stress caused by crystal defects. As a result, large warpage occurred, and it had not been put to practical use.
• As technology advances it is required to further improve the characteristics of an optical semiconductor device using a gallium nitride-based compound semiconductor, and the present inventors need to manufacture a higher-quality GaN single crystal substrate. Occurred.
• the present invention has been made in view of the above circumstances, and an object of the present invention is to provide a GaN single crystal substrate having reduced crystal defects such as dislocations and a method for manufacturing the same.
• the method for manufacturing a GaN single crystal substrate according to the present invention includes: a mask layer forming step of forming a mask layer having a plurality of aperture windows spaced apart from each other on the GaAs substrate; and And an epitaxy layer growing step of growing an epitaxy layer comprising G a N.
• a GaN nucleus is formed in each opening window of the mask layer, and this GaN nucleus is gradually formed in a lateral direction on the mask layer, that is, the mask layer is formed. Freely without any obstacles above the mask part where the opening window is not formed Lateral growth. Then, when the GaN nucleus grows laterally, the defects in the GaN nucleus do not spread, so that a GaN single crystal substrate with greatly reduced crystal defects can be formed.
• a buffer layer forming step of forming a buffer layer on the GaAs substrate; And a lower epitaxial layer growing step of growing a lower epitaxial layer comprising:
• the lower epitaxy layer made of GaN is located below the opening window of the mask layer, and the epitaxy layer made of GaN is formed on the lower epitaxy layer. Is further reduced.
• crystal defects such as dislocations have a higher density near the buffer layer, it is better to grow the lower epitaxial layer and form the mask layer at a distance from the buffer layer.
• crystal defects can be reduced as compared with the case where the lower epitaxial layer is not grown.
• the method further includes, before the epitaxial layer growing step, forming a buffer layer on the GaAs substrate in the opening window of the mask layer. It is also preferable to further include a layer forming step.
• the low-temperature buffer layer does not grow on the mask portion of the mask layer composed of Si 2 and Si 3 N 4 , but is formed only in the opening window.
• a plurality of the opening windows of the mask layer are arranged at a pitch L in a ⁇ 10 ⁇ 10> direction of the lower epitaxy layer.
• the ⁇ 10 — 10> window group is pitched d (0.75L ⁇ d ⁇ 1.3L) in the ⁇ 1—210> direction of the lower epitaxy layer.
• each of the ⁇ 10-10> window groups is located at the center position of each of the opening windows of the ⁇ 10-10> window group adjacent to each other.
• each open window of each 10 ⁇ 10> window group has a center position that is approximately 10 ° ⁇ 10> away from the center position of each adjacent open window of the ⁇ 1 0-10> window group. Since it is shifted by 1/2 L, GaN crystal grains of regular hexagonal pyramid or frustum of regular hexagonal pyramid growing from each opening window hardly produce pits with crystal grains grown from adjacent opening windows, leaving no gap. As a result, crystal defects and internal stress in the epitaxial layer can be reduced.
• a plurality of the opening windows of the mask layer are arranged on the (111) plane of the GaAs substrate by pitches L in a 11-2> direction.
• a window group is formed at a pitch d (0.75 L) in the (1 1 1) plane of the (1 1 1) plane of the GaAs substrate.
• each of the ⁇ 1 1 ⁇ 2> window groups is such that each of the ⁇ 11 1 ⁇ 2> window groups in which the center positions of the respective opening windows are adjacent. It is preferable that they are juxtaposed with each other by about 1/2 L in the above-mentioned 11-2> direction with respect to the center position.
• each open window of each 11 ⁇ 2> window group is approximately one center in the ⁇ 11 ⁇ 2> direction relative to the center position of each adjacent open window of the ⁇ 1 1 1 2> window group.
• the regular hexagonal pyramid or truncated regular hexagonal pyramid G a N crystal grains that grow from each open window hardly produce pits with the crystal grains that grow from the adjacent open windows and are connected without gaps.
• crystal defects and internal stress in the epitaxial layer can be reduced.
• the epitaxial layer in the step of growing the epitaxial layer, is grown thick to form a GaN single crystal ingot, and the ingot is cut into a plurality of pieces. It is also desirable to further include a cutting step for performing the cutting step.
• the GaN single crystal ingot is cut into a plurality of pieces, a plurality of GaN single crystal substrates with reduced crystal defects can be obtained in one manufacturing process.
• the epitaxial layer growing step in the epitaxial layer growing step, the epitaxial layer is grown thick to form a GaN single crystal ingot, and the plurality of ingots are formed. It is also desirable to further include a cleavage step for cleaving at a predetermined distance.
• the GaN single crystal ingot is cleaved into a plurality of pieces, a single manufacturing process can obtain a plurality of GaN single crystal substrates with reduced crystal defects.
• the ingot is cleaved along the cleavage plane of the GaN crystal, a plurality of GaN single crystal substrates can be easily obtained.
• an ingot is formed by growing a thick GaN epitaxial layer on the GaN single crystal substrate obtained by the above-described manufacturing method to form a GaN single crystal ingot. It is preferable that the method further includes a step of cutting the ingot into a plurality of pieces.
• a GaN epitaxial layer is grown on the GaN single crystal substrate manufactured by the above-described manufacturing method to form an ingot, and a plurality of GaN single crystal substrates are formed simply by cutting the ingot. You can get one. That is, a plurality of GaN single-crystal substrates with reduced crystal defects can be manufactured with a simple operation.
• FIGS. 1A to 1D are diagrams respectively showing the first to fourth steps of the method for manufacturing a GaN single crystal substrate according to the first embodiment.
• FIG. 2 is a diagram showing a vapor phase growth apparatus used for the HVP E method.
• FIG. 3 is a view showing a vapor phase growth apparatus used for the metal organic chloride vapor phase epitaxy method.
• FIG. 4 is a plan view of the mask layer of the first embodiment.
• 5A to 5D are diagrams respectively showing first to fourth steps of the epitaxial growth according to the first embodiment.
• 6A to 6D are diagrams respectively showing the first to fourth steps of the method for manufacturing a GaN single crystal substrate according to the second embodiment.
• FIG. 7 is a plan view of a mask layer according to the second embodiment.
• FIGS. 8A to 8D are diagrams respectively showing the first to fourth steps of the method for manufacturing a GaN single crystal substrate according to the third embodiment.
• FIG. 9 is a plan view of a mask layer according to the third embodiment.
• FIGS. 10A and 10B are diagrams each showing a growth process of the second epitaxial layer according to the third embodiment.
• FIGS. 11 to 11D are diagrams respectively showing the first to fourth steps of the method for manufacturing a GaN single crystal substrate according to the fourth embodiment.
• FIG. 12 is a plan view of a mask layer according to the fourth embodiment.
• FIG. 13A to 13E are views showing first to fifth steps of the method for manufacturing a GaN single crystal substrate according to the fifth embodiment, respectively.
• FIG. 14 is a plan view of a mask layer according to the sixth embodiment.
• FIG. 15 is a plan view of the mask layer of the seventh embodiment.
• FIGS. 16A to 16F are views respectively showing the first step to the sixth step of the method for manufacturing a GaN single crystal substrate according to the eighth embodiment.
• FIGS. 17A to 17C are diagrams showing first to third steps of the method for manufacturing a GaN single crystal substrate according to the ninth embodiment, respectively.
• FIG. 188 and FIG. 18 are diagrams respectively showing the first step and the second step of the method for manufacturing a GaN single crystal substrate according to the tenth embodiment.
• FIGS. 19A to 19C are diagrams illustrating first to third steps of the method for manufacturing a GaN single crystal substrate according to the first embodiment, respectively.
• FIG. 20 is a diagram showing a light emitting diode using a GaN single crystal substrate according to the third embodiment.
• FIG. 21 is a diagram showing a semiconductor laser using the GaN single crystal substrate of the third embodiment.
• FIG. 22 is a diagram showing a vapor phase growth apparatus used for the sublimation method.
• the lattice direction and the lattice plane of the crystal may be used.
• the individual direction is indicated by []
• the set direction is indicated by ⁇ >
• the individual plane is indicated by ()
• the set plane is indicated by ⁇ .
• "-" (bar) is attached to the number in crystallography, but a negative sign is added before the number for the convenience of preparing the specification.
• FIGS. 1A to 1D The GaN single-crystal substrate and the method of manufacturing the same according to the first embodiment are described in FIGS. 1A to 1D. This will be described with reference to manufacturing process drawings.
• a Ga As substrate 2 is set in a reaction vessel of a vapor phase growth apparatus.
• a GaAs (1 1 1) A substrate having a GaAs (1 1 1) plane as a Ga plane or a GaAs (1 1 1) plane having an As plane as a GaAs (1 1 1) plane.
• Any of the B substrates can be used.
• a buffer layer 4 made of GaN is formed on the GaAs substrate 2.
• the formation method of the buffer layer 4 includes a vapor phase growth method such as a HVPE (Hydride Vapor Phase Epitaxy) method, a metal organic chloride vapor phase growth method, and a MOCVD method.
• a vapor phase growth method such as a HVPE (Hydride Vapor Phase Epitaxy) method, a metal organic chloride vapor phase growth method, and a MOCVD method.
• FIG. 2 is a diagram showing a normal-pressure gas phase growth apparatus used for the HVPE method.
• the apparatus includes a reaction chamber 59 having a first gas introduction port 51, a second gas introduction port 53, a third gas introduction port 55, and an exhaust port 57, and a heating chamber 59 for heating the reaction chamber 59.
• the resistance heating heater consists of 6 1 and.
• a source boat 63 made of Ga metal and a rotation support member 65 that supports the GaAs substrate 2 are provided in the reaction chamber 59.
• a preferred method of forming the buffer layer 4 using such a vapor phase growth apparatus will be described.
• the GaAs substrate 2 is formed by a resistance heating heater 61. While maintaining the temperature at about 450 ° C to about 530 ° C, hydrogen chloride (HC1) is divided into partial pressures of 4 x 10 " 4 at ⁇ ! ⁇ 4 ⁇ from the second gas introduction port 53. by. the treatment is introduced into G a metal Sosubo Ichito 63 1 0- 3 atm, reacts with hydrogen chloride (HC 1) is a Ga metal, gallium chloride (Ga C 1) is generated.
• HC1 hydrogen chloride
• Ammonia (NH 3 ) is introduced from the first gas introduction port 51 at a partial pressure of 0.3 latm to 0.3 a tm, and the NH 3 and GaC 1 are reacted near the GaAs substrate 2, Gallium nitride (GaN) is generated, and the first gas introduction port 51 and the second gas introduction port 53 are supplied with hydrogen as a carrier gas. (H 2 ) is introduced. In addition, only hydrogen (H 2 ) is introduced into the third gas introduction port 55.
• GaN Gallium nitride
• H 2 hydrogen
• a buffer layer 4 of GaN having a thickness of about 500 ⁇ to about 1200 ⁇ is formed on the GaAs substrate 2.
• the HVP E method the growth rate of the buffer layer does not change much even if the synthesis amount of gallium chloride (GaCl) is increased, and it is considered that the reaction is rate-limiting.
• a buffer layer can be formed under substantially the same conditions as when a GaAs (111) A substrate is used.
• FIG. 3 is a diagram showing a growth apparatus used for the metalorganic chloride vapor phase epitaxy.
• This apparatus has a reaction chamber 79 having a first gas introduction port 71, a second gas introduction port 73, a third gas introduction port 75, and an exhaust port 77, and heats the reaction chamber 79. It consists of 8 and 1 resistance heating heaters.
• a rotation support member 83 for supporting the GaAs substrate 2 is provided in the reaction chamber 79.
• a method of forming the buffer layer 4 using such a growth apparatus will be described.
• a GaAs (111) A substrate is used as the GaAs substrate 2
• the temperature of the GaAs substrate 2 is controlled by the resistance heater 81.
• TMG trimethylgallium
• H1 hydrogen chloride
• GaCl gallium chloride
• NH 3 ammonia
• HC1 hydrogen chloride
• H 2 Hydrogen
• GaN having a thickness of about 500 angstroms to about 1200 angstroms can be formed on the GaAs substrate 2.
• a buffer layer 4 is formed.
• the growth rate of the ⁇ j fa layer 4 can be set to about 0.08 m / hr to about 0.18 ⁇ m / hr.
• the buffer layer can be formed under substantially the same conditions as when a GaAs (111) A substrate is used.
• the MOCVD method refers to a method in which an organic metal containing Ga, for example, trimethylgallium (TMG), and ammonia (NH 3 ) are blown together with a carrier gas onto a heated GaAs substrate 2 in a cold-wall type reaction furnace.
• TMG trimethylgallium
• NH 3 ammonia
• GaN is grown on the GaAs substrate 2.
• the temperature of the GaAs substrate 2 when spraying an organic metal or the like containing Ga onto the GaAs substrate 2 is about 450 ° C. to about 60 ° C. when the GaAs (111) A substrate is used.
• the temperature is preferably about 450 ° C. to about 550 ° C.
• the organic metal containing Ga for example, triethyl gallium (TEG) can be used in addition to TMG.
• a first epitaxial layer (lower epitaxial layer) 6 made of GaN is grown on the buffer layer 4.
• a vapor phase growth method such as the HVP E method, the metalorganic chloride vapor phase growth method, and the MOCVD method can be used in the same manner as the formation method of the buffer layer 4. .
• preferable conditions for growing the first epitaxial layer 6 by these vapor phase epitaxy methods will be described.
• the buffer layer When growing the first epitaxial layer 6 by the HVPE method, the buffer layer
• the apparatus shown in FIG. 2 can be used.
• GaA s When a Ga As (111) A substrate is used as the substrate 2, the temperature of the Ga As substrate 2 is maintained at about 920 ° C to about 1030 ° C by the resistance heating heater 61.
• the first epitaxial layer 6 is grown.
• the growth rate of the first epitaxial layer 6 can be set to about 20 m / hr to about 200 m / hr.
• growth rate, GAC l partial pressure i.e., large dependence on HC 1 minute pressure, HC 1 partial pressure, 5 x 1 0- 4 atn! It can take a range of ⁇ 5 x 1 0- 2 atm.
• the temperature of the Ga As substrate 2 is raised to about 850 ° C to about 950 ° C by the resistance heating heater 61. Grows the first epitaxial layer 6 with.
• the apparatus shown in FIG. 3 can be used similarly to the formation of the buffer layer 4.
• a GaAs (111) A substrate is used as the GaAs substrate 2
• the temperature of the GaAs substrate 2 is maintained at about 920 ° C to about 1030 ° C by the resistance heating heater 81.
• the first epitaxial layer 6 is grown.
• the growth rate of the first epitaxial layer 6 can be set at about 10 m / hr to about 60 m / hr.
• the partial pressure of GaC 1 should be increased by increasing the partial pressure of TMG, but the partial pressure was higher than the equilibrium vapor pressure of TMG at the gas pipe temperature. If, occurs liquefaction of TMG to the gas pipe inner wall, for contamination and clogging of pipes occurs, the partial pressure of TMG can not be raised indiscriminately, it believed to be about 5 x 1 0- 3 atm is the upper limit. For this reason, the upper limit of the growth rate is considered to be about 60 m / hr.
• the temperature of the GaAs substrate 2 is maintained at about 850 ° C to about 950 ° C by the resistance heating heater 81.
• the growth rate of the first epitaxial layer 6 can be set to about 10 m / hr to about 50 m / hr.
• the partial pressure of trimethylgallium and the like introduced into the reaction chamber 79 is as described above. From the reasons, is 5 x 1 0- 3 atm becomes the upper limit.
• the temperature of the GaAs substrate 2 when the organic metal containing Ga is sprayed on the GaAs substrate 2 is GaAs (111) )
• the temperature is preferably about 750 ° C to about 900 ° C
• the temperature is preferably about 730 ° C to about 820 ° C. The above is the growth condition of the first epitaxial layer 6.
• a second step shown in FIG. 1B taken out in the middle of manufacturing the wafer from the growth apparatus, S iN also on the Epitakisharu layer 6 to form a mask layer 8 made of S i0 2.
• Mask layer 8 is about 1 0 O nm to about 500 nm thick S i N film or S i 0 2 film was formed by a plasma C VD, etc., the S iN film or S I_ ⁇ 2 film photolithography It is formed by patterning with.
• FIG. 4 is a plan view of the wafer in the second step shown in FIG. 1B.
• a plurality of stripe-shaped stripe windows 10 are formed in the mask layer 8 of the present embodiment.
• the stripe window 10 is formed so as to extend in the 10 ⁇ 10> direction of the first epitaxial layer 6 made of GaN.
• the arrows in FIG. 4 indicate the crystal orientation of the first epitaxial layer 6.
• the process proceeds to the third step shown in FIG. 1C.
• the wafer on which the mask layer 8 has been formed is placed again in the reaction vessel of the vapor phase growth apparatus.
• the second epitaxy layer 12 is grown on the mask layer 8 and the portion of the first epitaxy layer 6 exposed from the stripe window 10.
• the method of growing the second epitaxial layer 12 there are HVPE, metalorganic chloride vapor phase epitaxy, MOCVD, and the like, like the method of growing the first epitaxial layer 6.
• the thickness of the second epitaxy layer 12 is about 15 to about 1,000 m.
• the growth process of the second epitaxial layer 12 will be described with reference to FIGS. 5A to 5D. This will be described in detail.
• the second epitaxial layer 12 in the initial stage of the growth of the second epitaxial layer 12 of G aN, the second epitaxial layer 12 does not grow on the mask layer 8 and G a N nuclei grow only on the first epitaxial layer 6 in the striped window 10. Then, as the growth progresses, the thickness of the second epitaxial layer 12 increases, and with this increase in thickness, as shown in FIG. 5B, the second epitaxial layer 12 Lateral growth occurs. As a result, as shown in FIG. 5C, the epitaxial layers 12 that have grown from both sides on the mask layer 8 are connected, and they are integrated.
• the second epitaxial layer 12 After being integrated by lateral growth, the second epitaxial layer 12 grows upward and increases in thickness, as shown in FIG. 5D.
• the growth rate in the thickness direction becomes faster than before the unification. The above is the growth process of the second epitaxial layer 12.
• the stripe window 10 is formed so as to extend in the 10 ⁇ 10> direction of the first epitaxial layer 6 made of G a N. Therefore, the width direction of the striped window 10 and the ⁇ 1_2 10> direction of the first epitaxial layer 6 substantially match.
• the GaN epitaxial layer has a high growth rate in the ⁇ 1-210> direction, the GaN epitaxial layer becomes adjacent to the epitaxial layer after the lateral growth of the second epitaxial layer 12 begins. The time until the layers 12 are integrated is reduced. Therefore, the growth rate of the second epitaxial layer 12 is increased.
• the striped window 10 does not necessarily need to extend in the ⁇ 10—10> direction of the first epitaxy layer 6; for example, it may extend in the ⁇ 111> direction of the epitaxy layer 6. It may be formed so as to be present.
• the dislocation density of the second epitaxial layer 12 will be described.
• a plurality of dislocations 14 exist inside the second epitaxial layer 12.
• the second epitaxy layer 1 2 Even if ⁇ grows laterally, dislocations 14 hardly spread in the lateral direction. Further, even if the dislocations 14 spread in the horizontal direction, they do not become threading dislocations extending in the horizontal direction and penetrating the upper and lower surfaces. For this reason, a low dislocation density region having a lower dislocation density than a region above the stripe window 10 is provided above a portion of the mask layer 8 where the stripe window 10 is not formed (hereinafter, referred to as a “mask portion”).
• the dislocation density of the second epitaxial layer 12 can be reduced.
• the dislocations 14 hardly extend upward. No.
• the upper surface of the second epitaxial layer 12 has no voids and threading dislocations and has excellent burying properties and flatness.
• the process proceeds to the fourth step shown in FIG. 1D.
• the wafer is set in an etching apparatus, and the GaAs substrate 2 is completely removed with an ammonia-based etching solution. Further, after the GaAs substrate 2 is removed, the removal surface of the GaAs substrate 2, that is, the lower surface of the buffer layer 4 is polished to complete the GaN single crystal substrate 13 according to the present embodiment. I do.
• the second epitaxy layer 1 Polish the upper surface of 2 to make it mirror-finished. Specifically, it is preferable that after the lapping polishing is performed on the upper surface of the second epitaxial layer 12, the puff polishing is further performed.
• the width P of the mask portion shown in FIGS. 1B and 4 is preferably in the range of about 2 ⁇ m to about 20 ⁇ m.
• the width P of the mask portion is smaller than the lower limit, the effect of the lateral growth of the second epitaxial layer 12 tends to decrease.
• the width P is larger than the upper limit, the second edge The mass productivity tends to decrease as the growth time of the epitaxial layer 12 increases.
• the window width Q of the striped window 10 be in the range of about 0.3 ⁇ m to about 10 HI. Striped windows By setting the window width Q of 10 within this range, the effect of the mask can be obtained.
• the buffer layer 4 made of A1N may be grown instead of GaN.
• the MOVPE method can be used. Specifically, after the inside of the reaction vessel is sufficiently evacuated in advance, the GaAs (111) A substrate is heated to about 550 ° C to about 700 ° C and the GaAs (11 1) When the B substrate is used, the GaAs substrate 2 is heated to about 550 ° C to about 700 ° C, and hydrogen is used as a carrier gas, and trimethyl aluminum (TMA) and ammonia (NH) are used as source gases. 3 ) is introduced. By such a process, the buffer layer 4 made of A1N having a thickness of about 100 angstroms to about 1000 angstroms is formed on the GaAs substrate 2.
• Mask layer 8 the thickness of about 1 00 nm to about 500 nm of S iN film or S I_ ⁇ 2 film formed by plasma C VD, etc., in the S i N film or S I_ ⁇ 2 film photolithography It is formed by patterning.
• FIG. 7 is a plan view of the wafer in the first step shown in FIG. 6A.
• a plurality of stripe-shaped stripe windows 10 are also formed in the mask layer 8 of the present embodiment, similarly to the first embodiment.
• the stripe window 10 is formed so as to extend in the direction of the GaAs substrate 2. 7 indicate the crystal orientation of the GaAs substrate 2.
• the buffer layer 24 is formed on the GaAs substrate 2 inside.
• the buffer layer 24 can be formed by the HVPE method, the metal organic chloride vapor phase epitaxy method, the MOCVD method, or the like, as in the first embodiment.
• the thickness of the buffer layer 24 is preferably about 50 nm to about 12 O nm.
• an epitaxial layer 26 of GaN is grown on the buffer layer 24.
• the epitaxial layer 26 is preferably grown to a thickness of about 150 to about 1000 m by HVPE, metal organic chloride vapor phase growth, MOCVD, or the like, as in the first embodiment. Also in this case, the crystal defects of the epitaxial layer 26, particularly the crystal defects above the mask portion of the mask layer 8 and the upper surface of the epitaxial layer 26 can be reduced by the lateral growth of the epitaxial layer. .
• the stripe window 10 is formed so as to extend in the 1 1 ⁇ 2> direction of the Ga As substrate 2, the width direction of the stripe window 10 and the — 10> Direction is almost the same.
• the GaN epitaxial layer grows in the 1-10> direction of the GaAs substrate 2 at a high speed. Therefore, after the lateral growth of the epitaxial layer 26 starts, the adjacent epitaxial layer 26 The time until the two are integrated is reduced. Therefore, the growth rate of the epitaxial layer 26 increases.
• the stripe window 10 does not necessarily need to extend in the 11-2> direction of the GaAs substrate 2; for example, it may be formed so as to extend in the ⁇ 1-10> direction of the GaAs substrate 2. Good.
• the process proceeds to the fourth step shown in FIG. 6D, and the Ga As substrate 2 is removed to complete the GaN single crystal substrate 27 of the present embodiment.
• a method for removing the Ga As substrate 2 there is, for example, etching.
• the GaAs substrate 2 can be removed by subjecting the GaAs substrate 2 to etching for about 1 hour using an ammonia-based etching solution. In addition, using aqua regia, GaAs-based The plate 2 can be subjected to wet etching. After the GaAs substrate 2 is removed, the removal surface of the GaAs substrate 2, that is, the lower surfaces of the mask layer 8 and the buffer layer 24 may be subjected to polishing. Further, similarly to the first embodiment, the upper surface of the epitaxial layer 26 may be polished.
• a GaN substrate having few crystal defects and small internal stress can be manufactured only by growing the epitaxial layer once. Compared to the embodiment, the number of manufacturing steps can be reduced, and the cost can be reduced.
• the present inventors have repeated trial and error to produce a higher quality GaN substrate. As a result, the present inventors have found that it is important to reduce the internal stress of the grown GaN epitaxial layer in order to manufacture a high-quality GaN substrate.
• the internal stress of a GaN epitaxial layer can be considered as being divided into thermal stress and true internal stress.
• This thermal stress is caused by a difference in thermal expansion coefficient between the GaAs substrate and the epitaxial layer.
• the direction in which the GaN substrate warps can be predicted by this thermal stress.However, the actual warpage of the entire GaN substrate without removing the GaAs substrate must be in the opposite direction to the predicted direction. Even after the removal of the GaAs substrate, the GaN substrate still warps, indicating that true internal stress exists in the GaN epitaxial layer.
• the substrate may be warped or cracked, so that a large-area, high-quality GaN single-crystal substrate cannot be obtained.
• the present inventors investigated the cause of the generation of true internal stress.
• the causes of the true internal stresses that have been reached as a result are as follows. That is, the GaN epitaxial layer generally has a hexagonal columnar crystal, and a grain boundary having a slight inclination exists at the interface between the columnar grains, and a mismatch in the atomic arrangement is observed. Furthermore, there are many dislocations in the GaN epitaxial layer. These grain boundaries and dislocations cause volume shrinkage of the GaN epitaxial layer through the growth and disappearance of defects, and are the cause of the generation of true internal stress.
• Embodiments of the invention completed on the basis of the cause of the generation of the true internal stress are the GaN single crystal substrates and the method of manufacturing the same according to the third to fifth embodiments.
• the GaAs substrate 2 is formed in the same manner as in the first embodiment.
• a buffer layer 4 made of GaN and a first epitaxial layer (lower epitaxy layer) 6 made of GaN are grown thereon.
• a plurality of square opening windows 30 are formed in the mask layer 28.
• the windows 10 are arranged at a pitch L in the ⁇ 10—10> direction of the first epitaxial layer 6 to form a ⁇ 10—10> window group 32.
• the 10 ⁇ 10> window group 32 is located at a position where the center position of each opening window 10 is adjacent to the center position of each opening window 10 of the window group 32.
• a plurality of juxtapositions are arranged at a pitch d in the 1 ⁇ 2 10> direction of the first epitaxial layer 6 while shifting by 1/2 L in the 10> direction.
• the center position of each window 30 means the position of the center of gravity of each window 30.
• Each opening window 30 was a square having a side length of 2 m, the pitch L was 6 / m, and the pitch d was 5 m.
• a second epitaxial layer 34 is grown on the mask layer 28 in the same manner as in the first embodiment.
• FIG. 10A shows the initial growth of the second epitaxial layer 34.
• a regular hexagonal pyramid or a truncated regular hexagonal GaN crystal grain 36 grows from each opening window 30.
• FIG. 10B when the GaN crystal grains 36 grow laterally on the mask layer 28, each GaN crystal grain 36 has a gap (pit) between the other GaN crystal grains 36. G) are connected without setting.
• each GaN crystal grain 36 covers the mask layer 28, and a second epitaxy layer 34 having a mirror-like surface is formed.
• each opening window 30 is displaced by 1/2 L in the c 10 ⁇ 10> direction. Since a plurality of windows 10 32 are arranged side by side in the ⁇ 1 ⁇ 210> direction, the GaN crystal grains 36 of a truncated hexagonal pyramid grow with almost no gaps. Internal stress is greatly reduced.
• dislocations hardly occur in the region corresponding to the upper portion of the mask layer 28 of the second epitaxial layer 34 due to the lateral growth of the GaN crystal grains 36.
• the process proceeds to the fourth step shown in FIG. 8D, the GaAs substrate 2 is removed by etching treatment or the like, and the GaN single crystal substrate 35 of the present embodiment is removed. Is completed.
• each opening window 30 of the mask layer 28 is a square having a side of 2 zm, but the shape and dimensions of the opening window 30 of the mask layer 28 are not limited thereto, and the growth conditions It is desirable to make appropriate adjustments according to the conditions.
• a square having a side of 1 to 5 ⁇ m and a circle having a diameter of 1 to 5 ⁇ m can be used.
• the shape of each window 10 is not limited to a square or a circle, but may be an ellipse or a polygon.
• the area of each opening window 30 is arbitrary desirable to 0. 7 ⁇ M 2 ⁇ 50 ⁇ M 2.
• each opening window 30 is made larger than this range, defects occur frequently in the epitaxial layer 34 in each opening window 30 and the internal stress tends to increase. On the other hand, if the area of each opening window 30 is made smaller than this range, formation of each opening window 30 becomes difficult, and the growth rate of the epitaxial layer 34 tends to decrease.
• the total area of each opening window 30 is preferably 10 to 50% of the total area of all the opening windows 30 and the mask portion of the mask layer 28. When the total area of each opening window 30 is in this range, the defect density and internal stress of the GaN single crystal substrate can be significantly reduced.
• the pitch L is set to 6 zm and the pitch d is set to 5 ⁇ m, but the lengths of the bit L and the pitch d are not limited thereto.
• the pitch L is desirably in the range of 3 to 10 m. If the pitch L is longer than 10 1m, The time until the GaN crystal grains 36 are connected to each other increases, and a large amount of time is spent for growing the second epitaxial layer 34. On the other hand, if the pitch L is less than 3 ⁇ m, the distance over which the crystal grains 36 grow laterally becomes short, and the effect of the lateral growth is reduced. For the same reason, it is desirable that the pitch d be in a range of 0.75 L ⁇ d ⁇ l.3L.
• the distance that each of the windows 30 of the ⁇ 10—10> window group 32 is shifted in the adjacent ⁇ 10—10> window group 32, particularly the 1 0—10> direction, of the adjacent ⁇ 10—10> window group 32 is not necessarily accurate. It is not necessary to be 1/2 L, and if it is about 2/5 L to 3/5 L, the internal stress can be reduced.
• the thickness of the mask layer 28 be in the range of about 0.05111 to about 0.5 ⁇ m. This is because if the mask layer 28 is too thicker than this range, cracks will occur during the growth of GaN, while if it is thinner than this range, the GaAs substrate will be damaged by evaporation during the growth of GaN. It is. [Fourth embodiment]
• FIGS. 11A to 11D a GaN single-crystal substrate and a method for manufacturing the same according to the fourth embodiment will be described with reference to manufacturing process diagrams shown in FIGS. 11A to 11D.
• This embodiment is the same as the second embodiment except for the shape of the mask layer.
• FIG. 12 is a plan view of the wafer in the first step shown in FIG. 11A.
• the shape of the mask layer 38 of the present embodiment is similar to the shape of the mask layer 28 of the third embodiment.
• a plurality of opening windows 40 are formed in the mask layer 38.
• Each of the opening windows 40 is arranged at a pitch L in the ⁇ 1> 1-2> direction of the GaAs substrate 2, and a ⁇ 1> 1-2> window group 42 is formed.
• the 1 1 2> window group 42 is located in the 1 1 2> direction with respect to the center position of each opening window 40 of the ⁇ 1 1 1 2> window group 42 where the center position of each opening window 40 is adjacent.
• a plurality of the GaAs substrates 2 are arranged in parallel in the ⁇ 1-10> direction at a pitch d while being shifted from each other by 1/2 L.
• the only difference between the mask layer 38 of the present embodiment and the mask layer 28 of the third embodiment is the arrangement direction of the respective windows.
• the buffer layer 24 is formed on the GaAs substrate 2 in the opening window 40 in a second step shown in FIG. 11B.
• an epitaxial layer 26 of GaN is grown on the buffer layer 24 in a third step shown in FIG. 11C.
• GaN crystal grains of a truncated regular hexagonal pyramid grow from each opening window 40 in the initial stage of growth. Then, when the GaN crystal grains grow laterally on the mask layer 38, each GaN crystal grain is connected without providing a gap (pit) between the other GaN crystal grains. Then, each GaN crystal grain covers the mask layer 38, and the epitaxy layer 26 having a mirror-like surface is formed.
• each opening window 40 is necessarily extended in the direction -
• it may be formed so as to extend in the ⁇ 1-10> direction of the GaAs substrate 2.
• the process proceeds to the fourth step shown in FIG. 11D, and the GaAs substrate 2 is removed to complete the GaN single crystal substrate 39 of the present embodiment.
• the front and back surfaces of the GaN single crystal substrate 39 have large roughness, the front and back surfaces may be polished.
• a GaN substrate with significantly reduced crystal defects can be manufactured only by growing the epitaxial layer once. The cost can be reduced.
• a GaN single crystal substrate and a method of manufacturing the same according to a fifth embodiment will be described with reference to FIGS. 13A to 13E.
• a mask layer 38 preferably having a thickness of about 10 Onm to about 50 O nm is formed on the GaAs substrate 2 as in the fourth embodiment.
• a buffer layer 24 having a thickness of preferably about 500 nm to about 1200 nm is formed on the GaAs substrate 2 in the opening window 40.
• a first epitaxial layer 44 of GaN is grown on the buffer layer 24 and the mask layer 38.
• the thickness of the first epitaxial layer 44 is preferably in the range of about 50 m to about 300.
• the GaN crystal grains grown from each opening window 40 have no gaps (pits) between them and other GaN crystal grains. The structure is such that the mask layer 38 is embedded.
• the wafer on which the first epitaxial layer 44 has been formed is arranged in an etching apparatus, and is etched with aqua regia for about 10 hours to completely remove the GaAs substrate 2. I do. In this way, once the thickness is about 50 ⁇ m A thin GaN single crystal substrate with a thickness of 300 m is formed.
• a second epitaxy made of GaN is formed on the first epitaxy layer 44 by the HVPE method, metalorganic chloride vapor phase epitaxy method, MOCVD method, etc.
• Layer 46 is grown to a thickness of about 100 m to about 700 m.
• a GaN single crystal substrate 47 having a thickness of about 150 ⁇ m to about 1000 ⁇ m is formed.
• the heat of the GaAs substrate 2, the sofa layer 24 and the epitaxial layers 44 and 46 is reduced. It is possible to prevent the occurrence of thermal stress due to the difference in expansion coefficient. Therefore, a high-quality GaN single-crystal substrate with less warpage and cracks can be manufactured as compared with the case where the epitaxial layer is grown to the end without removing the GaAs substrate 2 on the way.
• the reason why the thickness of the first epitaxial layer 44 is set to about 300 / m or less is that if the first epitaxial layer 44 is too thick, the influence of thermal stress increases. .
• the reason why the thickness of the first epitaxial layer 44 is set to about 50 m or more is that if the first epitaxial layer 44 is too thin, the mechanical strength is weak and handling is difficult.
• a mask layer having a stripe window as in the second embodiment may be used as the mask layer of the present embodiment.
• the front and back surfaces of the GaN single crystal substrate 47 may be polished.
• FIG. 14 is a view showing the shape and arrangement of each opening window of the mask layer 48 used in the present embodiment.
• each opening window is formed in a rectangular shape (strip shape), and the ⁇ 10—10> direction of the first epitaxial layer 6, which is the layer immediately below the mask layer 48, is defined as the longitudinal direction.
• the rectangular window is 50.
• Each rectangular window 50 is arranged at a pitch L in a direction of 10 ⁇ 10> of the first epitaxial layer 6 to form a group of 10 ⁇ 10> rectangular windows 52.
• the ⁇ 1 0—1 0> rectangular window group 52 has the center position of each rectangular window 50 in the adjacent ⁇ 10 ⁇ 10> rectangular window group 52, particularly the 1 0—10> direction. While being shifted by 1/2 L, a plurality of layers are juxtaposed at a pitch d in the direction of the first epitaxial layer 6.
• the pitch L is set such that when the length of the rectangular window 50 in the longitudinal direction is long, the region where the second epitaxial layer does not grow laterally in the ⁇ 10—10> direction becomes large, and the internal stress is increased. In view of the fact that it is difficult to reduce the amount, it is preferable to set the range of about 4 to about 20 ⁇ m. Further, it is desirable that the length of the mask between the rectangular windows 50 adjacent in the longitudinal direction, that is, the ⁇ 10-10> direction, be about 1 m to about 4 / m. This is because the growth of GaN in the ⁇ 10—10> direction is slow, so that if the mask length is too long, it takes a long time to form the second epitaxial layer.
• the mask width (d ⁇ w) between the rectangular windows 5 2 adjacent in the 1 ⁇ 2 1 0> direction of the first epitaxial layer 6 should be about 2 ⁇ m to about 10 ⁇ m. Is desirable. If the mask width (d ⁇ w) is too wide, it takes time for the hexagonal columnar crystal grains to be continuous, while if the mask width (d ⁇ w) is too narrow, the effect of lateral growth cannot be obtained. This is because it is difficult to reduce crystal defects. Further, the width w of each rectangular window 50 is desirably about 1 m to about 5 zm.
• a second epitaxy layer 12 made of GaN is grown on the mask layer 48 in the same manner as in the third embodiment.
• GaN crystal grains of a regular hexagonal pyramid grow from each rectangular window 50.
• each GaN crystal grain is connected without providing a gap (pit) between other GaN crystal grains, and the mask layer 48 is connected. The structure becomes embedded.
• dislocations hardly occur in the region corresponding to the upper part of the mask layer 48 of the second epitaxy layer due to the lateral growth of GaN crystal grains.
• each rectangular window 50 is formed such that the longitudinal direction of each rectangular window 50 coincides with the 10 ⁇ 10> direction of the first epitaxial layer 6, the rectangular window 50 is formed on the mask layer 48.
• the growth rate of the second epitaxial layer to be grown can be increased. This is because the ⁇ 1 1 2 1 1 ⁇ plane with a high growth rate appeared in the early stage of GaN growth, the growth rate in the ⁇ 1-210> direction increased, and the crystal was formed in each rectangular window 50. This is because the time required for the island-shaped GaN crystal grains to become a continuous film is shortened.
• the second layer formed on the mask layer 48 can be improved.
• FIGS. 7 a GaN single crystal substrate and a method of manufacturing the same according to a seventh embodiment will be described with reference to FIGS.
• This embodiment is characterized by the shape of the window of the mask layer.
• the buffer layer and the epitaxial layer are formed in the same manner as in the above embodiments.
• each opening window of the mask layer 58 is a hexagonal window 60 formed in a regular hexagonal ring shape.
• the six sides of the hexagonal window 60 are formed so as to coincide with the ⁇ 10-10> direction of the lower epitaxial layer of the mask layer 58.
• the growth rate of the epitaxy layer formed on the mask layer 58 can be increased. This is because the ⁇ 1 1 2 1 1 ⁇ plane with a high growth rate grows in the ⁇ 1-2 1 0> direction in the early stage of the growth of GaN.
• the width a of the hexagonal window 60 should be approximately 2 m, the length of one side of the outer regular hexagon b should be approximately 5 m, and the mask width w between adjacent hexagonal windows 60 should be approximately 3 m. Is desirable. However, these values are not limited to this range.
• the arrow in FIG. 15 indicates the crystal orientation of the epitaxy layer below the mask layer 58.
• the wafer After growing an epitaxial layer on the mask layer 58, the wafer is subjected to an etching process to completely remove the GaAs substrate. Further, the removal surface of the GaAs substrate is polished to form the GaN single crystal substrate of the present embodiment.
• the GaN single crystal substrate of the present embodiment also has the effect of the lateral growth of the GaN crystal grains in a region corresponding to the upper part of the epitaxial layer on the mask layer. Causes almost no dislocation.
• the growth rate of the epitaxy layer formed on the mask can be improved.
• the six sides of the hexagonal window 42 are formed so as to coincide with the ⁇ 111> direction of the GaAs substrate.
• FIG. 16A shows the formation of the mask layer 8 in the first step
• FIG. 16B shows the formation of the buffer layer 24 in the second step
• FIG. 16C shows the formation of the epitaxial layer 26 in the third step.
• the growth of and the removal of the Ga As substrate 2 in the fourth step shown in FIG. 16D are performed in the same manner as in the second embodiment, and therefore the description is omitted.
• the thickness of the GaN single crystal substrate from which the GaAs substrate 2 has been removed is desirably about 50 111 to about 300 im, or more, as in the second embodiment.
• the GaN single crystal is grown by growing the GaN single crystal as shown in FIG. To form an ingot 64.
• a growth method of the epitaxial layer 62 there are an HVP E method, an organic metal chloride vapor phase epitaxy method, a MOCVD method, etc. as in the above-described embodiments. A law may be adopted.
• the sublimation method is a growth method performed using a growth apparatus 90 as shown in FIG. 22.More specifically, the sublimation method is carried out in a reaction furnace 94 in which a GaN powder 92 as a raw material and a substrate 2 are installed to face each other.
• This sublimation method is difficult to control delicately, but is suitable for thickening the epitaxial layer, that is, for producing ingots.
• the temperature of the reactor is set at about 1000 ° C. to about 1300 ° C., and ammonia is flowed at about 10 sccm to about 100 sccm using nitrogen gas as a carrier gas.
• the GaN single crystal ingot 64 is made into a plurality of GaN single crystal substrates 66.
• a method of forming the ingot 64 into a plurality of GaN single crystal substrates a method of cutting the ingot 64 with a slicer or the like of the inner peripheral teeth is used.
• a plurality of GaN single crystal ingots are cut or cleaved, a plurality of GaN single crystal substrates with reduced crystal defects can be obtained with a simple operation. it can. That is, mass productivity can be improved as compared with the above embodiments.
• the height of the ingot 64 is preferably about 1 cm or more. If the ingot 64 is less than 1 cm, there is no mass production effect.
• the manufacturing method according to the present embodiment forms an ingot 64 based on the GaN single crystal substrate obtained by performing the manufacturing steps according to the second embodiment shown in FIGS. 6A to 6D. Is not limited to this method.
• the ingot 64 may be formed based on the GaN single crystal substrate that has undergone the manufacturing steps of the first to seventh embodiments.
• the GaN single crystal substrate 66 of the present embodiment has an electron mobility in the range of 1 ⁇ 10 1 ⁇ cm— 3 to 1 ⁇ 10 2 ° cm— 3 with n-type carrier concentration without intentional doping.
• the specific resistance is 1 x 10- 4 Q cm ⁇ ; it can be controlled to be within ⁇ ⁇ ⁇ ⁇ ⁇ ⁇ m has been found by experiments.
• the mask layer 8 and the buffer layer 24 are formed on the GaAs substrate 2.
• the method for forming the mask layer 8 and the buffer layer 24 is the same as in the above embodiments.
• an epitaxial layer 68 made of GaN is grown at a stretch to form an ingot 70.
• Growth of epitaxy layer 68 The method is the same as the method of growing the epitaxial layer 62 of the eighth embodiment. Note that the height of the ingot 70 is preferably about 1 cm or more.
• a GaN single crystal ingot 70 is formed into a plurality of GaN single crystal substrates 72 by a cutting process or a cleavage process. .
• a plurality of GaN single crystal ingots are cut or cleaved, a plurality of GaN single crystal substrates with reduced crystal defects can be obtained with a simple operation. it can. That is, mass productivity can be improved as compared with the first to seventh embodiments. Further, since the GaN epitaxial layer is grown only once, the manufacturing process can be simplified and the cost can be reduced as compared with the eighth embodiment.
• the GaN single-crystal substrate 72 of the present embodiment also has an n-type carrier concentration of 1 ⁇ 10 16 cm 13 to 1 ⁇ 10 3 without intentional doping, similarly to the GaN single-crystal substrate 66 of the eighth embodiment. 2 ° cm— 3 , electron mobility within 60 cm 2 to 800 cm 2 , resistivity 1 xl O— 4 Q cm or more: controlled to within ⁇ ⁇ ⁇ ⁇ cm Experiments have shown that this is possible.
• a GaN single crystal substrate and a method for manufacturing the same according to the tenth embodiment will be described with reference to FIGS. 18A to 18B.
• an epitaxy layer 74 is grown on the GaN single crystal substrate 66 manufactured in the eighth embodiment to form a GaN single crystal ingot 76.
• the HVPE method, the organometallic chloride vapor phase epitaxy method, the MOCVD method, the sublimation method, or the like can be used for the growth method of the epitaxial layer 74 as in the above embodiments.
• Ga The N single crystal ingot 76 is made into a plurality of GaN single crystal substrates 78. Thereby, a GaN single crystal substrate 78 of the present embodiment is obtained.
• the ingot is manufactured using the GaN single crystal substrate 66 manufactured in the eighth embodiment as a seed crystal, but the seed crystal of the ingot is not limited to this.
• the GaN single crystal substrate 72 of the ninth embodiment can be used as a seed crystal.
• a GaN single crystal substrate and a method for manufacturing the same according to the first embodiment will be described with reference to FIGS. 19A to 19C.
• a buffer layer 79 having a thickness of about 50 nm to about 120 nm is formed on the GaAs substrate 2.
• an epitaxial layer 81 made of GaN is grown on the buffer layer 79 without forming a mask layer, and a GaN layer having a height of about 1 cm or more is formed.
• a single crystal ingot 83 is formed.
• HVPE, metal organic chloride vapor phase epitaxy, MOCVD, sublimation, etc. can be used.
• lateral growth of the epitaxial layer does not occur and crystal defects are not few, but dislocation can be reduced by thickening the epitaxial layer.
• a GaN single crystal ingot 83 is formed into a plurality of GaN single crystal substrates 85 by a cutting process or a cleavage process.
• the GaN single crystal substrate manufactured according to each of the above embodiments is n-type and has conductivity
• a GaN-based layer including an InGaN active layer is epitaxially grown on the GaN single crystal substrate by MOCVD or the like, so that light emission is obtained.
• Light emitting devices such as diodes and electronic devices such as field effect transistors (MES FETs) can be formed. Since these light-emitting devices and the like are manufactured using a high-quality GaN substrate with few crystal defects manufactured in each of the above-described embodiments, their characteristics are higher than those of a light-emitting device and the like using a sapphire substrate. Significantly improved.
• the (000 1) plane of the epitaxial layer grown on the GaN single crystal substrate grows homoepitaxially parallel to the (000 1) plane of the GaN single crystal substrate, and the cleavage planes match.
• the above light emitting devices and the like have excellent performance.
• FIG. 20 is a diagram showing a light emitting diode 80 using the GaN single crystal substrate 35 obtained in the third embodiment.
• the light emitting diode 80 on the GaN single crystal substrate 35, a GaN buffer layer 1 0 1, S i and doped n-type GaN barrier layer 1 02, and one thickness of 3 angstrom flop I n 0. 45 Ga 0 . and 55 N well layer 103, Mg de -.. flop p-type a 1 0 2 Ga 0 8 and N barrier layer 1 04, M g doped p-type G aN contactor and coat layer 1 05, a quantum well growing the It has a structure.
• the light-emitting diode 80 can change the emission color depending on the composition ratio of the AND-InGaN well layer 103. For example, when the composition ratio of In is 0.2, blue light is emitted.
• the light emission luminance of the light emitting diode using the conventional sapphire substrate was 0.5 cd, which was 2.5 times, that is, 5 times.
• FIG. 21 is a diagram showing a semiconductor laser 82 using the GaN single crystal substrate 35 obtained in the third embodiment.
• the oscillation life which was about several minutes in the past, exceeded 100 hours, and a significant improvement in characteristics was realized. Specifically, the oscillation life, which was about 1.5 minutes in the past, has increased to about 120 hours.
• the semiconductor laser is not limited to the GaN single crystal substrate 35 of the third embodiment, and a GaN single crystal substrate of another embodiment can of course be used.
• a field effect transistor (MES FET) was manufactured based on the GaN single crystal substrate of the present embodiment.
• MES FET field effect transistor
• a high transconductance (gm) of 43 mS / mm was obtained even at a high temperature of 500 ° C, and the GaN single crystal substrate of this embodiment can be used as a substrate for electronic devices. It turned out to be effective.
• Example 1
• Example 1 which is an example of the GaN single crystal substrate of the first embodiment and the method of manufacturing the same will be described with reference to FIGS. 1A to 1D.
• GaAs substrate 2 As the GaAs substrate 2, a GaAs (111) A substrate having a GaAs (111) surface as a Ga surface was used.
• the buffer layer 4, the first epitaxial layer 6, and the second epitaxial layer 12 are all formed of organic gold using the vapor phase growth apparatus shown in FIG. -
• a buffer layer 4 was formed by metal organic chloride vapor phase epitaxy.
• Isseki 8 1 resistive heating heat Isseki 8 1 was heated maintaining the temperature of the GaAs substrate 2 to approximately 500 ° C, trimethyl gallium (TMG) partial pressure 6 x 10 one 4 atm, hydrogen chloride partial pressure 6 X 1 0- 4 atm, it was introduced into each reaction chamber 79 and ammonia at a partial pressure 0. 13 atm. Then, the thickness of the buffer layer 4 was set to about 800 angstroms.
• a first epitaxial layer 6 was grown on the buffer layer 4 by a metal organic chloride vapor phase epitaxy method.
• the resistance heater 81 was raised maintaining the temperature of the GaAs substrate 2 to approximately 970 ° C, trimethyl gallium (TMG) the partial pressure 2 X 1 ⁇ one 3 a tm, hydrogen chloride partial pressure 2 X 10- 3 atm and ammonia were introduced into the reaction chamber 79 at a partial pressure of 0.2 atm.
• TMG trimethyl gallium
• the thickness of the first epitaxial layer 6 was reduced to about 4 ⁇ m.
• a mask layer 8 made of SiO 2 was formed on the first epitaxial layer 6.
• the longitudinal direction of the stripe window 10 is directed to [10-10] of the first epitaxial layer 6, the thickness of the mask layer 8 is about 300 nm, the width P of the mask portion is about 5 ⁇ m, The window width Q was about 2 m.
• a second epitaxial layer 12 was grown by metalorganic chloride vapor phase epitaxy.
• resistive heating heat Isseki 81 was heated maintaining the temperature of the G a As the substrate 2 to approximately 970 ° C, trimethyl gallium (TMG) the partial pressure 2 X 10- 3 a tm, hydrogen chloride partial pressure of 2 It was introduced into the reaction chamber 79, respectively x 10- 3 a tm, ammonia partial pressure 0. 25 atm.
• TMG trimethyl gallium
• the thickness of the second epitaxial layer 12 was set to about 100 ⁇ m.
• the wafer was set in an etching apparatus, and the GaAs substrate 2 was completely removed by etching the GaAs substrate 2 with an ammonia-based etchant for about 1 hour. . Finally, the ground surface is removed from the GaAs substrate 2. Polishing was performed to complete the GaN single crystal substrate 13.
• this GaN single crystal substrate has a (000 1) plane on the substrate surface. Its crystallinity is determined by X-ray analysis with an X-ray half-width of 4.5 minutes, and the dislocation density is 10 units per unit area. It was about 7 (cm— 2 ). As a result, the number of crystal defects has been greatly reduced compared to the case where the GaN epitaxy layer was formed on a conventional sapphire substrate with a defect density of 10 9 (cm 2 ) per unit area. Do you get it.
• Example 2 which is another example of the first embodiment will be described with reference to FIGS. 1A to 1D.
• Ga As substrate 2 a GaAs (111) A substrate was used.
• the buffer layer 4, the first epitaxy layer 6, and the second epitaxy layer 12 were all formed by the HVP E method using the vapor phase growth apparatus shown in FIG.
• the buffer layer 4 was formed by the HVPE method.
• resistive heating heat Isseki 61 holds raising the temperature of the GaAs substrate 2 to approximately 500 ° C, respectively hydrogen chloride partial pressure 5 X 10- 3 at m, and ammonia at a partial pressure of 0. 1 atm Reaction Introduced into chamber 59.
• the thickness of the buffer layer 4 was set to about 800 angstroms.
• the first epitaxial layer 6 was grown on the buffer layer 4 by the HVPE method. At this time, by resistive heating heating evening 61 it was heated maintaining the temperature of the GaAs substrate 2 to approximately 97 0 ° C, respectively hydrogen chloride partial pressure 2 x 10- 2 atm, and ammonia at a partial pressure of 0. 25 a tm reaction Introduced into chamber 79. Then, the growth rate was set to about 80 m / hr, and the thickness of the first epitaxy layer 6 was set to about 4 m.
• a mask layer 8 was formed on the first epitaxial layer 6. At this time, the longitudinal direction of the stripe window 10 is aligned with the first epitaxy layer 6. -
• the thickness of the mask layer 8 was set to about 300 nm, the width P of the mask part was set to about 5 / m, and the window width Q was set to about 2 ⁇ m.
• a second epitaxial layer 12 was grown by the HVPE method.
• the temperature of the GaAs substrate 2 was raised to about 970 ° C by the resistance heating heater 61, and the partial pressure of hydrogen chloride was 2.5 x 10-2 atm, and the partial pressure of ammonia was 0.
• Each was introduced into reaction chamber 79 at 25 atm.
• the growth rate was set to about 100 / m / hr, and the thickness of the second epitaxy layer 12 was set to about 100,111.
• the HVP method since the HVP method is used, the growth rate of the epitaxial layer can be increased as compared with the first embodiment using the metalorganic chloride vapor phase epitaxy. did it.
• the GaAs substrate 2 is completely etched by placing the wafer in an etching apparatus and wet-etching the GaAs substrate 2 with an ammonia-based etching solution for about 1 hour. Removed. Finally, the removal surface of the GaAs substrate 2 was polished to complete the GaN single crystal substrate 13.
• this GaN single crystal substrate has a (000 1) plane on the substrate surface. Its crystallinity is determined by X-ray analysis with an X-ray half-width of 4.5 minutes, and the dislocation density is determined by 5 was x 1 0 7 (cm- 2) about. Thus, compared to the defect density in the case of forming a G a N Epitakisharu layer of the conventional sapphire substrate was per unit area 1 0 9 (cm- 2), the crystal defects were greatly reduced I understood.
• Example 3 which is an example of the second embodiment will be described with reference to FIGS. 6A to 6D.
• the GaAs substrate 2 has a G a As (1
• the B substrate was used.
• the buffer layer 24 and the second epitaxial layer 2 Both were formed by metalorganic chloride vapor phase epitaxy using the vapor phase epitaxy apparatus shown in FIG.
• a mask layer 8 was formed on the GaAs substrate 2 in a first step shown in FIG. 6A.
• the longitudinal direction of the stripe window 10 is directed to [11-2] of the GaAs substrate 2
• the thickness of the mask layer 8 is about 350 nm
• the width P of the mask section is about 4 ⁇ m
• the window width is Q was about 2 m.
• a buffer layer 24 was formed on the GaAs substrate 2 in the stripe window 10 by metalorganic chloride vapor phase epitaxy.
• the resistance pressurized thermal heating evening 8 1 was heated maintaining the temperature of the G a As the substrate 2 to approximately 500 ° C, trimethyl Chirugariumu (TMG) the partial pressure 6 x 1 0- 4 atm, hydrogen chloride partial pressure 6 x 1 0 one 4 atm, were introduced into each reaction chamber 79 and ammonia at a partial pressure of 0. 1 a tm. Then, the thickness of the buffer layer 24 was reduced to about 700 ⁇ .
• TMG trimethyl Chirugariumu
• an epitaxial layer 26 was grown on the buffer layer 24 by a metal organic chloride vapor phase epitaxy method.
• resistive heating heating evening 8 1 was heated maintaining the temperature of the G a
• Torimechirugariu arm (TMG) the partial pressure 3 X 1 0- 3 atm, hydrogen chloride minute pressure 3 x 1 0- 3 atm, were introduced into each reaction chamber 79 to ⁇ Nmonia partial pressure 0. 2 atm.
• the growth rate was set to about 30 m / hr, and the thickness of the epitaxial layer 26 was set to about 100 m.
• the wafer is placed in an etching apparatus, and the GaAs substrate 2 is wet-etched with an ammonia-based etching solution for about 1 hour, thereby converting the Ga As substrate 2 into an etching solution. Removed completely. Finally, the surface from which the Ga As substrate 2 had been removed was polished to complete the GaN single crystal substrate 27.
• the GaN single crystal substrate manufactured according to this example had a dislocation density of about 210 7 (cm ⁇ 2 ) per unit area. That is, the GaN single crystal substrate manufactured according to the present embodiment has a higher dislocation density than the GaN single crystal substrates according to the first and second embodiments. Despite this, it was found that crystal defects were significantly reduced as compared with the case where a GaN epitaxial layer was formed on a conventional sapphire substrate. Further, in the present embodiment, the number of manufacturing steps is smaller than in the first embodiment and the second embodiment, so that the cost can be reduced.
• Example 4 which is an example of the third embodiment will be described with reference to FIGS. 8A to 8D.
• the GaAs substrate 2 As the GaAs substrate 2, a GaAs (111) A substrate was used. Further, the buffer layer 4, the first epitaxy layer 6, and the second epitaxy layer 34 were all formed by the metalorganic chloride vapor phase epitaxy using the vapor phase epitaxy apparatus shown in FIG. First, in the first step shown in FIG. 8A, the buffer layer 4 was formed by metalorganic chloride vapor phase epitaxy. At this time, the temperature of the GaAs substrate 2 was raised to about 5 ° C.
• the resistance heater 81 by the resistance heater 81, and the partial pressure of trimethylgallium (TMG) was 6 ⁇ 10-4 atm, and the partial pressure of hydrogen chloride was 6 ⁇ 1 0- 4 atm, it was introduced into each reaction chamber 79 and ammonia at a partial pressure of 0. 1 atm. Then, the thickness of the buffer layer 4 was set to about 700 angstroms.
• TMG trimethylgallium
• a first epitaxial layer 6 was grown on the buffer layer 4 by a metal organic chloride vapor phase epitaxy method.
• resistive heating heating evening 81 was heated maintaining the temperature of the GaAs substrate 2 to approximately 970 ° C, trimethyl gallium (TMG) partial pressure 2 X 1 0 one 3 atm, hydrogen chloride partial pressure 2 X 10- 3 atm and ammonia were introduced into the reaction chamber 79 at a partial pressure of 0.2 atm.
• TMG trimethyl gallium
• a mask layer 28 made of Si 2 was formed on the first epitaxial layer 6.
• the opening window 30 is a square with a side length of 2 ⁇ m, and the pitch L of the window group 32 is 6 6 ⁇ pitch d is 5 m.
• adjacent ⁇ 10-10> window groups 32 were shifted by 3 ⁇ m in the 10-10> direction.
• a second epitaxial layer 34 was grown by metal organic chloride vapor phase epitaxy.
• resistive heating heat Isseki 8 1 was heated maintaining the temperature of the G a As the substrate 2 to approximately 1000 ° C, trimethylgallium (TMG) partial pressure 4 X 1 0- 3 atm, hydrogen chloride partial pressure 4 x 1 0 3 atm, were introduced into each reaction chamber 79 and ammonia at a partial pressure 0. 2 atm.
• the growth rate was set to about 25 m / hr, and the thickness of the second epitaxial layer 12 was set to about 100 m.
• the wafer is set in an etching apparatus, and the GaAs substrate 2 is completely etched by aqua regia for about 10 hours. Removed. Finally, the removal surface of the GaAs substrate 2 was polished to complete the GaN single crystal substrate 35.
• the characteristics of the GaN single crystal substrate manufactured according to this example were as follows. That is, the defect density was about 3 x 1 0 7 (cm- 2 ) about had been significantly reduced than ever. No crack was observed.
• the radius of curvature of the GaN single crystal substrate manufactured by omitting the separate mask layer forming step was about 65 mm, whereas the radius of curvature of the GaN single crystal substrate of this example was about 770 mm, and the GaN single crystal substrate was warped.
• the internal stress which was conventionally 0.05 GPa, was reduced to about 0.005 GPa to about 1/10 in the GaN single crystal substrate of this example.
• Example 5 which is an example of the fifth embodiment
• FIGS. It will be described with reference to FIG.
• GaAs substrate 2 As the GaAs substrate 2, a GaAs (111) A substrate was used. Further, the buffer layer 24, the first epitaxy layer 44, and the second epitaxy layer 46 were all formed by the HVP E method using the vapor phase growth apparatus shown in FIG.
• a mask layer 38 was formed on the GaAs substrate 2.
• the opening window 40 was made circular with a diameter of 2 m, and the pitch L of the window group was set to 6 m, and the pitch d was set to 5.5 / m.
• adjacent 1 1 ⁇ 2> windows were shifted by 3 zm in the 1 1 ⁇ 2> direction.
• the buffer layer 24 was formed on the GaAs substrate 2 in the opening window 40 by the HVPE method.
• resistance heating heater evening Te 6 1 Niyotsu was heated maintaining the temperature of the GaAs substrate 2 to approximately 500 ° C
• hydrogen chloride minute was introduced into the reaction chamber 59, respectively pressure 6 x 10- 4 a tm, ammonia partial pressure 0. 1 a tm.
• the thickness of the buffer layer 24 was reduced to about 700 ⁇ .
• a first epitaxial layer 44 was grown on the buffer layer 24 by the HVP E method.
• the growth rate was set to about 25 m / hr, and the thickness of the first epitaxial layer 44 was set to about 50 mm.
• ⁇ : ⁇ was placed in an etching apparatus and etched with aqua regia for about 10 hours to completely remove the GaAs substrate 2. In this way, a thin GaN single crystal substrate having a thickness of about 50 ⁇ m was once formed.
• H is formed on the first epitaxial layer 44.
• a second epitaxial layer 46 of GaN was grown to a thickness of about 130 .mu.m at a growth rate of about 100 .mu.m / hr at a partial pressure of 0.2 atm.
• a GaN single crystal substrate 47 having a thickness of about 180 zm was formed.
• the defect density on the substrate surface of the GaN single crystal substrate of the present example formed as described above was remarkably reduced to about 2 ⁇ 10 7 / cm 2 , and cracks were observed. Did not.
• the warpage of the GaN single crystal substrate could be reduced as compared with the conventional one, and the internal stress was very small, 0.002 GPa.
• Example 6 which is an example of the eighth embodiment will be described with reference to FIGS. 16A to 16F.
• a GaAs (111) A substrate is used as the GaAs substrate 2.
• the nozzle layer 24, the epitaxial layer 26, and the epitaxial layer 62 were all formed by the HVP E method using the vapor phase growth apparatus shown in FIG.
• a mask layer 8 was formed on the GaAs substrate 2 in the first step shown in FIG. 16A.
• the longitudinal direction of the stripe window 10 is directed to [111] of the GaAs substrate 2
• the thickness of the mask layer 8 is about 300 nm
• the width P of the mask portion is about 5 ⁇ m
• the window width Q is about
• a buffer layer 24 was formed on the GaAs substrate 2 in the stripe window 10 by the HVPE method while keeping the temperature of the GaAs substrate 2 at about 500 ° C.
• the thickness of the buffer layer 24 was set to about 800 ⁇ .
• an epitaxy layer 26 is grown on the buffer layer 24 by the HVPE method for about 200 ⁇ m. I let it.
• the GaAs substrate 2 is removed by etching with aqua regia. did.
• the epitaxy layer 62 is further thickened on the epitaxy layer 26 by the HVP E method while maintaining the temperature in the reaction chamber 59 at 120 ° C., and G a An N single crystal ingot 64 was formed.
• the ingot 64 had a slightly depressed top center, a height from the bottom to the top center of about 2 cm, and an outer diameter of about 55 mm.
• the ingot 64 is cut by a slicer of the inner peripheral teeth, and a GaN single crystal substrate 66 having an outer diameter of about 5 Omm and a thickness of about 350 ⁇ m is formed. 20 were obtained. No remarkable warpage was observed on the GaN single crystal substrate 66. After the cutting process, the GaN single crystal substrate 66 was subjected to lapping polishing and finish polishing.
• the carrier concentration was n-type 2 ⁇ 10 18 cm ⁇ 3
• the electron mobility was
• the carrier concentration was n-type 8xi0 18 cii 3 and the electron mobility was 15
• the quality of the characteristic of the intermediate portion of the ingot 64 can be assured to be at or near the value during this period, and the trouble of performing a full inspection can be eliminated.
• Example 7 which is another example of the eighth embodiment will be described with reference to FIGS.
• a GaAs (111) A substrate was used as the GaAs substrate 2.
• the buffer layer 24, the epitaxial layer 26, and the epitaxial layer 62 were all formed by a metal organic chloride vapor phase epitaxy method using the vapor phase epitaxy apparatus shown in FIG.
• a mask layer 8 was formed on the GaAs substrate 2.
• the longitudinal direction of the stripe window 10 is directed to [11-2] of the GaAs substrate 2
• the thickness of the mask layer 8 is about 500 nm
• the width P of the mask portion is about 5 ⁇ m
• the window width Q is about
• the buffer layer 24 was formed on the GaAs substrate 2 in the stripe window 10 by the HVPE method while the temperature of the GaAs substrate 2 was set to about 490 ° C. Formed by In addition, the thickness of the noise layer 24 was set to about 800 angstroms.
• the temperature of the GaAs substrate 2 was set to about 970 ° C., and the epitaxial layer was formed on the buffer layer 24 by metalorganic chloride vapor phase epitaxy. 26 was grown about 25 ⁇ m.
• the GaAs substrate 2 was removed by etching with aqua regia.
• the temperature in the reaction chamber 79 is set at 1,000 ° C., and the epitaxy layer 62 is formed on the epitaxy layer 26 by the HVP E method.
• the HVP E method was further thickened to form a GaN single crystal ingot 64.
• Ingot 64 had a slightly concave upper center, a height from the bottom to the center of the upper surface of about 3 cm, and an outer diameter of about 3 Omm.
• the ingot 64 is cut by a slicer of the inner peripheral teeth, and a GaN single crystal substrate 66 having an outer diameter of about 20 to about 30 mm and a thickness of about 400 ⁇ m is obtained.
• a GaN single crystal substrate 66 having an outer diameter of about 20 to about 30 mm and a thickness of about 400 ⁇ m is obtained.
• No remarkable warpage was observed on the GaN single crystal substrate 66.
• the GaN single crystal substrate 66 was subjected to lapping polishing and finish polishing.
• the carrier concentration was n-type 2 ⁇ 10 18 cm 3 and the electron mobility was 250 cm 2 / V s
• the specific resistance was 0.015 Qcm.
• Example 8 which is an example of the ninth embodiment will be described with reference to FIGS. 17A to 17C.
• a GaAs (111) A substrate is used as the GaAs substrate 2.
• the buffer layer 24 and the epitaxial layer 68 were both formed by the HVP E method using the growth apparatus shown in FIG.
• a mask layer 8 was formed on the GaAs substrate 2.
• the longitudinal direction of the stripe window 10 is directed to [11-2] of the GaAs substrate 2
• the thickness of the mask layer 8 is about 250 nm
• the width P of the mask portion is about 5 ⁇ m
• the window width Q is about 3 m.
• the buffer layer 24 was formed on the Ga As substrate 2 in the stripe window 10 by the HVP E method while keeping the temperature of the Ga As substrate 2 at about 500 ° C.
• the thickness of the nozzle layer 24 was set to about 900 angstroms.
• an epitaxial layer 68 was grown on the buffer layer 24 by the HVP E method. Then, an ingot 70 of a GaN single crystal was formed.
• the ingot 70 had a shape in which the center of the upper surface was slightly depressed, and the height from the bottom to the center of the upper surface was about 1.6 cm.
• the ingot 70 was cut by a slicer having inner teeth to obtain 12 GaN single crystal substrates 72 having a thickness of about 300 ⁇ m. No significant warpage was observed on the GaN single crystal substrate 72.
• the GaN single crystal substrate 72 was subjected to lapping polishing and finish polishing.
• the manufacturing cost was reduced to about 60% of that of Example 1. As described above, in the present embodiment, the cost was significantly reduced, and the manufacturing time per sheet was able to be shortened.
• the carrier concentration was n-type 1 ⁇ 10 ls cnr 3
• the electron mobility was 100 cm 2 / Vs
• the The resistance was 0.005 ⁇ .
• Example 9 which is an example of the tenth embodiment will be described with reference to FIGS.
• the GaN single-crystal substrate manufactured in Example 6 was used.
• An epitaxial layer 74 was grown thereon to form a GaN single crystal ingot 76.
• the epitaxial layer 74 was grown by HVPE with the temperature of the Ga As substrate 2 kept at about 1010 ° C.
• the ingot 76 had a shape in which the center of the upper surface was slightly depressed, the height from the bottom to the center of the upper surface was about 2.5 cm, and the outer diameter was about 55 mm.
• the ingot 76 is cut by a slicer of the inner peripheral teeth, and 15 GaN single crystal substrates 78 having an outer diameter of about 50 mm and a thickness of about 600 ⁇ m are obtained. Obtained.
• Example 1 only one single crystal substrate was obtained by one manufacturing process, but in this example, 15 substrates were obtained by one manufacturing process. Further, the manufacturing cost was reduced to about 55% as compared with the case of manufacturing by the same process as in Example 1. As described above, in the present embodiment, the cost was significantly reduced, and the manufacturing time per sheet could be shortened.
• the carrier concentration was n-type 1 ⁇ 10 17 cm- 3
• the electron mobility was 650 cm 2 / Vs
• the The resistance was 0.08 ⁇ cm.
• Example 10 which is another example of the tenth embodiment will be described with reference to FIGS. 18A to 18B.
• an epitaxy layer 74 was grown on the GaN single-crystal substrate manufactured in Example 7 to form a GaN single-crystal ingot 76.
• the epitaxial layer 74 was grown by the sublimation method with the temperature of the GaAs substrate 2 set to about 1200 ° C. using the growth apparatus shown in FIG.
• the amount of ammonia poured into the reaction vessel was 20 sccm.
• the ingot 76 is flatter than the ingots of the sixth to ninth embodiments, The height was about 0.9 cm and the outer diameter was about 35 mm.
• the ingot 76 is cut by the slicer of the inner peripheral teeth to obtain five GaN single crystal substrates 78 having an outer diameter of about 35 mm and a thickness of about 500 ⁇ m.
• the ingot 76 is cut by the slicer of the inner peripheral teeth to obtain five GaN single crystal substrates 78 having an outer diameter of about 35 mm and a thickness of about 500 ⁇ m.
• Example 1 to 5 only one single-crystal substrate was obtained by one manufacturing process, but in this example, five substrates were obtained by one manufacturing process. Also, the manufacturing cost was reduced to about 80% of Example 1. As described above, in the present embodiment, the cost was significantly reduced, and the manufacturing time per sheet was shortened.
• Example 11 which is an example of the eleventh embodiment will be described with reference to FIGS.
• a buffer layer 79 made of GaN with a thickness of about 90 nm is formed on the GaAs substrate 2 at about 500 ° C by the HVPE method. did. Note that a GaAs (111) B substrate was used as the Ga As substrate.
• an epitaxial layer 81 made of GaN was grown on the buffer layer 79 by the HVPE method to form an ingot 83 of a GaN single crystal.
• the epitaxial layer 81 was grown by the HVP E method while keeping the temperature of the Ga As substrate 2 at about 1030 ° C.
• the ingot 83 had a shape in which the center of the upper surface was slightly depressed, and the height from the bottom to the center of the upper surface was about 1.2 cm.
• the ingot is sliced by the inner tooth slicer.
• the substrate 83 was cut to obtain 10 GaN single crystal substrates 85 having a thickness of about 300 m.
• Examples 1 to 5 only one single crystal substrate was obtained by one manufacturing process.
• ten substrates were obtained by one manufacturing process.
• the manufacturing cost was reduced to about 70% of Example 1. As described above, in the present embodiment, the cost was significantly reduced, and the manufacturing time per one piece was able to be shortened.
• GaN nuclei are formed in each opening window of the mask layer, and the GaN nuclei gradually move in the lateral direction on the mask layer, that is, the opening windows of the mask layer. It grows freely laterally without any obstacles toward the upper part of the mask portion where no is formed. Therefore, according to the method for manufacturing a GaN single crystal substrate of the present invention, it is possible to efficiently and reliably obtain the GaN single crystal substrate of the present invention in which crystal defects are significantly reduced.

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• 1998
  • 1998-10-29 CN CNB2004100445548A patent/CN100344004C/zh not_active Expired - Fee Related
  • 1998-10-29 KR KR1020007004695A patent/KR100629558B1/ko not_active IP Right Cessation
  • 1998-10-29 DE DE69842052T patent/DE69842052D1/de not_active Expired - Lifetime
  • 1998-10-29 CA CA002311132A patent/CA2311132C/en not_active Expired - Fee Related
  • 1998-10-29 CN CNB988127164A patent/CN1175473C/zh not_active Expired - Fee Related
  • 1998-10-29 WO PCT/JP1998/004908 patent/WO1999023693A1/ja not_active Application Discontinuation
  • 1998-10-29 EP EP98950452A patent/EP1041610B1/en not_active Expired - Lifetime
  • 1998-10-29 EP EP10001771A patent/EP2200071B1/en not_active Expired - Lifetime
  • 1998-10-30 TW TW093103485A patent/TWI236056B/zh not_active IP Right Cessation
  • 1998-10-30 TW TW087118081A patent/TW591699B/zh not_active IP Right Cessation
• 2000
  • 2000-04-28 US US09/560,818 patent/US6693021B1/en not_active Expired - Fee Related
• 2001
  • 2001-03-26 HK HK01102181A patent/HK1031469A1/xx not_active IP Right Cessation
• 2003
  • 2003-10-24 US US10/691,540 patent/US7357837B2/en not_active Expired - Fee Related
  • 2003-10-24 US US10/691,569 patent/US7504323B2/en not_active Expired - Fee Related
• 2006
  • 2006-12-22 US US11/643,875 patent/US7521339B2/en not_active Expired - Fee Related
• 2009
  • 2009-03-10 US US12/382,180 patent/US20090263955A1/en not_active Abandoned
• 2011
  • 2011-01-17 JP JP2011007252A patent/JP2011084469A/ja active Pending

Patent Citations (8)

Non-Patent Citations (7)