US20030001249A1 - Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device - Google Patents

Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device Download PDF

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Publication number
US20030001249A1
US20030001249A1 US10/227,817 US22781702A US2003001249A1 US 20030001249 A1 US20030001249 A1 US 20030001249A1 US 22781702 A US22781702 A US 22781702A US 2003001249 A1 US2003001249 A1 US 2003001249A1
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United States
Prior art keywords
tub
leads
semiconductor device
semiconductor chip
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
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US10/227,817
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English (en)
Inventor
Yoshihiko Shimanuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
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Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to US10/227,817 priority Critical patent/US20030001249A1/en
Application filed by Individual filed Critical Individual
Publication of US20030001249A1 publication Critical patent/US20030001249A1/en
Assigned to RENESAS TECHNOLOGY CORPORATION reassignment RENESAS TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
Priority to US10/879,010 priority patent/US7804159B2/en
Priority to US12/222,099 priority patent/US7777312B2/en
Priority to US12/610,900 priority patent/US7821119B2/en
Priority to US12/897,221 priority patent/US8115298B2/en
Priority to US13/357,076 priority patent/US8637965B2/en
Priority to US14/108,507 priority patent/US8969138B2/en
Priority to US14/623,032 priority patent/US9484288B2/en
Priority to US15/166,603 priority patent/US20160276253A1/en
Abandoned legal-status Critical Current

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    • H01L2924/18301—Connection portion, e.g. seal being an anchoring portion, i.e. mechanical interlocking between the encapsulation resin and another package part

Definitions

  • the present invention relates generally to semiconductor fabrication technologies and, more particularly, to techniques adapted for miniaturization and thickness reduction plus cost down as well as reliability improvements.
  • a first prior known approach to satisfying the above technological requirements is to employ a resin sealed or hermetic surface-mount semiconductor device structure as disclosed in, for example, Published Unexamined Japanese Patent Application (“PUJPA”) No. 5-129473.
  • the prior art device as taught thereby is such that as shown in FIG. 29, this device employs a lead frame 35 with a pattern of electrical leads 33 and a chip support paddle or die pad 34 , also known as a “tub” among those skilled in the art, being located on the same surface, wherein the prior art is featured in that the leads 33 are electrically connected at lower surfaces to a semiconductor chip 36 via bonding wires 37 , wherein the lower surfaces are for use as external electrodes each functioning as an electrical connector portion with external circuitry operatively associated with the semiconductor device.
  • FIG. 29 Unfortunately the first prior art shown in FIG. 29 is associated with a problem which follows. As this is structurally designed so that the tub 34 's parts-mount surface side is exposed from the lower surface of the semiconductor device, the tub 34 will possibly come into direct contact with leads on the parts mount substrate when mounting the semiconductor device on the mount substrate, which in turn makes it impossible to form any leads at corresponding portions of the mount substrate, resulting in a noticeable decrease in the degree of freedom of substrate design schemes. Another problem is that since the device is structurally arranged so that the tub 34 is sealed only at its one surface, the resulting contact area between the tub 34 and a sealing material 38 used decreases causing the tight contact or adhesiveness to degrade accordingly, which would result in a decrease in reliability of the semiconductor device.
  • FIG. 30 A second prior art resin sealed semiconductor device is found in PUJPA No. 10-189830 (JP-A-10-189830).
  • This device is shown in FIG. 30, which includes a semiconductor element 42 as mounted on a tub 41 that in turn is supported by a hanging or “suspending” lead 40 of a lead frame 39 , metal fine leads 45 for electrical interconnection between electrodes 43 on the upper surface of said semiconductor element 42 and associative inner leads 44 , a sealing resin material 46 for use in sealing an outer surrounding region of the semiconductor element 42 containing metal fine lead regions over the upper surface of semiconductor element 42 , and external connect terminals 47 that are laid out in a bottom surface region of said sealing resin 46 for connection with said inner leads 44 , wherein said suspension lead 40 has been subjected to the so-called “up-set” processing thus having step-like differences 48 , called “stepped portions,” and wherein the sealing resin 46 is also formed at part underlying said tub 41 to a thickness corresponding to the amount of said upset processing.
  • the second prior art shown herein is such that since the suspension lead 40 of the lead frame 39 has been subject to the up-set processing to have the stepped portions 48 , it becomes possible to permit the sealing resin 46 to be present at the part underlying the tub 41 , which in turn makes it possible to provide substantially the double-face sealed semiconductor device structure with respect to the lead frame 39 , thereby offering increased reliability when compared to said first prior art discussed above.
  • Another advantage of the prior art is that in view of the fact that this is structurally designed to prevent exposure of the tub 41 's parts-mount substrate side from the lower surface of the semiconductor device, the tub 41 will no longer come into contact with those leads on the mount substrate, thereby increasing the degree of freedom in parts mount design schemes.
  • Another object of this invention is to provide an improved semiconductor device capable of increasing productivities while reducing production costs and a method of manufacturing the device as well as a parts mount structure of same.
  • a further object of the invention is to provide a semiconductor device capable of-preventing any accidental electrical shortcircuiting and unwanted lead dropdown detachment otherwise occurring during parts mounting processes and a method of manufacturing the device as well as a parts mount structure of same.
  • a semiconductor device comprising a tub supported by a plurality of suspension leads, a plurality of leads disposed to surround periphery of said tub, a semiconductor chip mounted on one principal surface of said tub and electrically connected to one principal surface of said plurality of leads, and a sealing resin for sealing said plurality of leads and said semiconductor chip plus said tub, wherein the remaining principal surface opposite to said one principal surface of said plurality of leads is exposed from said sealing resin-and that said tub is less in thickness than said plurality of leads.
  • a method of manufacturing a semiconductor device comprises the steps of: preparing a matrix lead frame including a plurality of lead frames each having a plurality of leads and a tub less in thickness than said plurality of leads plus a suspension lead for support of said tub; performing die bonding for mounting a semiconductor chip on or over the tub of each said lead frame; performing wire bonding for connection by wires between said semiconductor chip and the plurality of leads of said lead frame; sealing with a sealing resin said lead frame and said semiconductor chip plus said wires to permit said plurality of leads to be exposed on a lower surface side thereof; and cutting said matrix lead frame into a plurality of unitary lead portions at part in close proximity to a seal region as sealed at said step of sealing with the sealing resin to thereby obtain a plurality of semiconductor devices.
  • a mounting structure of a semiconductor device in accordance with the invention is a semiconductor device that is arranged to include a pattern of electrical leads on a mount substrate, a tub supported by a plurality of suspension leads, a plurality of leads as laid out to surround the periphery of said tub, a semiconductor chip that is mounted on or over one principal surface of said tub and is electrically connected to one principal surface of said plurality of leads, and a sealing resin material for use in sealing said plurality of leads and said semiconductor chip plus said tub, wherein the remaining principal surface on an opposite side to said one principal surface of said plurality of leads is exposed from said sealing resin, and wherein an adhesive material is used to attain coupling with the other principal surface of those leads of the semiconductor device with said tub formed to be less in thickness than said plurality of leads.
  • a resin sealed semiconductor device comprises a tub for support of a semiconductor chip, a seal section as formed by resin sealing of said semiconductor chip, a plurality of tub suspension leads including a supporting portion for use in supporting said tub and an exposed portion as coupled thereto and exposed to a surface on a semiconductor device mount side surface of said seal section, said supporting portion being formed to be thinner than said exposed portion, a plurality of leads disposed around said tub and exposed to said semiconductor device mount side surface of said seal section, and a connection member for connection between a surface electrode of said semiconductor chip and a corresponding one of said leads, wherein said tub suspension leads are coupled together via said tub.
  • the support portion of the tub at the tub suspension leads is formed to have a decreased thickness, it is possible to bury or embed the support portion in the seal section with the sealing resin covering the same thereby enabling provision of the intended structure with the tub suspension lead's exposed portion being exposed only at the end(s) at a corner or corners on the back surface of the seal section.
  • a resin sealed semiconductor device which comprises a tub supporting a semiconductor chip and being smaller than said semiconductor chip, a seal section as formed by resin sealing of said semiconductor chip, a supporting portion for support of said tub, a plurality of leads disposed around said tub and exposed to a semiconductor device mount side surface of said seal section, and a connection member for connection between more than one surface electrode of said semiconductor chip and a corresponding one of said leads, wherein said tub and said semiconductor chip are in contact by adhesion with each other at an inside location relative to said surface electrode of said semiconductor chip.
  • the invention it is possible to support the specified part at or near the end portion on the back surface of the semiconductor device by a bonding stage including a heatup wire-bonding process. This makes it possible during wire bonding to apply suituble ultrasonic waves and/or heat to wires being bonded, thereby enabling improvement in reliability and adhesiveness of such wire bonding.
  • a method of manufacturing a resin sealed semiconductor device comprises the steps of: preparing a lead frame including a tub capable of supporting a semiconductor chip, a plurality of tub suspension leads having a support section for use in supporting said tub and an exposed portion coupled thereto with said support section being thinner than said exposed portion, and a plurality of leads as disposed around said tub; adherently securing said tub and said semiconductor chip together; using a connection member to connect a surface electrode of said semiconductor chip to a corresponding one of said leads; forming a seal section by causing a sealing resin to flow onto an opposite surface to a chip support surface of said tub while covering a thickness reduced portion of said tub suspension lead with said sealing resin and then by disposing said plurality of leads and said exposed portion of said tub suspension lead on a semiconductor device mount side surface to thereby resin-mold said semiconductor chip; and subdividing said tub suspension lead into portions at said exposed portion of said tub suspension lead while separating said plurality of leads from a frame body of said lead frame.
  • FIG. 1 shows a diagram of a perspective view of an exterior appearance of a semiconductor device in accordance with an embodiment 1 of the present invention.
  • FIG. 2 shows a diagram of a plan view (lower surface side) of the semiconductor device shown in FIG. 1.
  • FIG. 3 shows a plan view of a unitary lead section of the embodiment 1 of the invention.
  • FIG. 4 shows a cross-sectional view of the unit lead section shown in FIG. 3 as taken along cutaway line A-A.
  • FIG. 5 shows a sectional view of the unit lead section shown in FIG. 3 taken along line B-B.
  • FIG. 6 shows a plan view of the semiconductor device shown in FIG. 1 as partly broken to make visible its internal configuration for illustration purposes only.
  • FIG. 7 shows a sectional view of the semiconductor device shown in FIG. 6 taken along line C-C.
  • FIG. 8 shows a sectional view of the semiconductor device shown in FIG. 6 taken along line D-D.
  • FIG. 9 shows a sectional view of the semiconductor device 1 shown in FIG. 6 taken along line E-E.
  • FIG. 10 shows a diagram of in cross-section a method of manufacturing the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 11 shows a plan view of a matrix lead frame for use during manufacture of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 12 shows an enlarged plan view of main part (upper surface side) of a unitary lead frame of the matrix lead frame shown in FIG. 11.
  • FIG. 13 shows an enlarged plan view of main part (lower surface side) of the unitary lead frame of the matrix lead frame shown in FIG. 11.
  • FIG. 14 shows a sectional view of the unit lead frame shown in FIG. 12 taken along line F-F.
  • FIG. 15 shows a sectional view of the unit lead frame shown in FIG. 12 taken along line G-G.
  • FIG. 16 shows a conceptual diagram showing a method of depositing an adhesive onto a tub at a die-bonding process step of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 17 shows a conceptual diagram showing a method of mounting a semiconductor chip on the tub at the die-bonding step of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 18 shows a conceptual diagram showing a wire-bonding method of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 19 shows a conceptual diagram showing a state in which a metal frame structure such as a metal tool and a matrix lead frame have been aligned in position with each other at a resin sealing process step of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 20 shows a conceptual diagram showing a state in which the metal tool is clamped at the resin sealing step of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 21 shows a conceptual diagram showing a state in which the metal tool is disassembled at the resin sealing step of the semiconductor device in accordance with the embodiment 1 of the invention.
  • FIG. 22 shows a perspective view of an exterior appearance showing a state in which the semiconductor device in accordance with the embodiment 1 of the invention has been mounted to a parts mount substrate.
  • FIG. 23 shows a sectional view of the device structure of FIG. 22 taken along line H-H.
  • FIG. 24 shows a plan view of a unitary lead section of an embodiment 2 of the invention.
  • FIG. 25 shows a sectional view of the unit lead section shown in FIG. 24 take along line I-I.
  • FIG. 26 shows a sectional view of the unit lead section shown in FIG. 24 take along line J-J.
  • FIG. 27 shows a partial see-through diagram of a semiconductor device in accordance with the embodiment 2 of the invention.
  • FIG. 28 shows a sectional view of the semiconductor device shown in FIG. 27 as taken along line K-K.
  • FIG. 29 shows a sectional view of the first prior art semiconductor device that has been already discussed in the introductory part of the description.
  • FIG. 30 shows a sectional view of the second prior art semiconductor device as also stated previously in the introductory part of the description.
  • FIG. 31 shows a plan view of an exemplary semiconductor device in accordance with an embodiment 3 of the invention as partly broken at its sealing section to render visible its internal configuration for illustration purposes only.
  • FIG. 32 shows a sectional view of the semiconductor device shown in FIG. 31 as taken along line L-L.
  • FIG. 33 shows a process flow diagram showing an example of the procedure for assembly of the semiconductor device shown in FIG. 31.
  • FIG. 34 shows parts (a), (b), (c), (d) and (e) are sectional flow diagrams showing an exemplary structure per main process step in the assembly of the semiconductor device shown in FIG. 31.
  • FIG. 35 shows a perspective view of an exterior appearance showing an example of the structure of a semiconductor device in accordance with an embodiment 4 of the invention.
  • FIG. 36 shows a bottom view of the structure of the semiconductor device shown in FIG. 35.
  • FIG. 37 shows a sectional view of the semiconductor device shown in FIG. 35 taken along line M-M.
  • FIG. 38 shows a sectional view of the semiconductor device shown in FIG. 35 taken along line N-N.
  • FIG. 39 shows a partial sectional view of one exemplary state at a wire-bonding process step during the assembly of the semiconductor device shown in FIG. 35.
  • FIG. 40 shows a partial plan view of one example of the resultant structure when completion of molding in a semiconductor device in accordance with an embodiment 5 of the invention, which structure is partly broken to visualize its internal configuration for illustration purposes only.
  • FIG. 41 shows a sectional view of the semiconductor device shown in FIG. 40 taken along line P-P.
  • FIG. 42 shows a partial plan view of an exemplary lead frame structure for use during assembly of the semiconductor device shown in FIG. 40.
  • FIG. 43 shows an enlarged partial sectional view of a structure of part “T” of FIG. 41.
  • FIG. 44 shows an enlarged partial sectional view for showing an exemplary lead cut method at the part T of FIG. 41.
  • FIG. 45 shows portions (a), (b), (c), (d) and (e) are diagrams each showing a lead structure of part “Q” of FIG. 40, wherein (a) is a bottom view, (b) is a plan view, (c) is a groove sectional view, (d) is a sectional of (b) taken along line U-U, and (e) is a sectional view of (b) along line V-V.
  • FIG. 46 shows a plan view of a modified example of the lead structure of the part Q of FIG. 40.
  • FIG. 47 shows an enlarged partial plan view of a structure of part “R” of FIG. 40.
  • FIG. 48 shows portions (a) and (b) are diagrams showing a structure of part “S” of FIG. 40, wherein (a) is an enlarged partial plan view whereas (b) is a sectional view of (a) along line X-X.
  • FIG. 49 shows portions (a) and (b) are diagrams showing a structure of part “W” of FIG. 48( a ), wherein (a) is an enlarged partial plan view and (b) is a groove sectional view of (a).
  • FIG. 50 shows portions (a), (b) and (c) are diagrams showing an example of the structure of a is semiconductor device in accordance with an embodiment 8 of the invention, wherein (a) is a plan view, (b) is a side view, and (c) is a bottom view.
  • FIG. 51 shows an enlarged partial bottom view of a structure of part “Y” of FIG. 50( c ).
  • FIG. 52 shows a partial plan view of an exemplary structure of a semiconductor device in accordance with an embodiment 9 of the invention as obtained at the termination of molding, the structure having an internal configuration depicted herein as seen through a seal section thereof.
  • FIG. 53 shows a sectional view of the semiconductor device shown in FIG. 52 as taken along line Z-Z.
  • FIG. 54 shows an enlarged partial sectional view of a structure of the device at part “AB” of FIG. 53.
  • FIG. 55 shows an enlarged partial sectional view diagram showing one example of a method of cutting leads at the part “AB” of FIG. 53.
  • FIG. 56 shows portions (a), (b), (c) and (d) are partial sectional diagrams showing an etching method that is one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • FIG. 57 shows portions (a), (b), (c) and (d) are partial sectional diagrams showing an etching method as one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • FIG. 58 shows portions (a), (b), (c) and (d) are partial sectional diagrams showing an etching method as one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • FIG. 59 shows portions (a), (b) and (c) are partial sectional diagrams showing a pressing method as one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • FIG. 60 shows (a), (b) and (c) are partial sectional diagrams showing a pressing method as one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • FIG. 61 shows (a), (b) and (c) are partial sectional diagrams showing a press method as one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • FIG. 62 shows a partial plan view of an exemplary structure of a semiconductor device in accordance with a variant of the invention as obtained at the termination of molding, the structure having an internal configuration depicted herein as seen through a seal section thereof.
  • FIG. 63 shows a sectional view of the semiconductor device shown in FIG. 62 taken along line CC-CC.
  • FIG. 64 shows a partial plan view of an exemplary structure of a semiconductor device in accordance with another variant of the invention as obtained at the termination of molding, the structure having an internal configuration depicted herein as seen through a seal section thereof.
  • FIG. 1 is a diagram showing a perspective view of an exterior appearance of a semiconductor device in accordance with an embodiment 1 of the present invention
  • FIG. 2 is a diagram showing a plan view (lower surface side) of the semiconductor device
  • FIG. 3 depicts a plan view of a unitary lead section (details will be described later) of the embodiment 1, wherein broken lines indicate a seal region.
  • FIG. 4 is a cross-sectional view of the unit lead section of FIG. 3 as taken along line A-A
  • FIG. 5 is a sectional view of the unit lead section of FIG. 3 taken along line B-B
  • FIG. 6 is a plan view of the semiconductor device of FIG. 1 as partly broken to make visible its internal configuration for illustration purposes only;
  • FIG. 4 is a cross-sectional view of the unit lead section of FIG. 3 as taken along line A-A
  • FIG. 5 is a sectional view of the unit lead section of FIG. 3 taken along line B-B
  • FIG. 6 is a plan view of the semiconductor device of
  • FIG. 7 is a sectional view of the semiconductor device of FIG. 6 taken along line C-C;
  • FIG. 8 is a sectional view of the semiconductor device of FIG. 6 taken along line D-D; and
  • FIG. 9 is a sectional view of the semiconductor device 1 of FIG. 6 taken along line E-E.
  • the semiconductor device 1 of the illustrative embodiment 1 is a semiconductor device of the areal or “surface” mount type which is structurally arranged so that electrical leads 2 for use as external connection terminals are partly exposed at outer periphery of the semiconductor device on its lower surface side.
  • This semiconductor device 1 includes a thin plate that is made of copper- or iron-based materials and machined to have a desired shape. As shown in FIGS.
  • this thin plate has a centrally disposed chip support paddle or die pad (also called “tub”) 5 that is supported by four suspending leads (referred to as tub suspension leads hereinafter) 4 which are integrally formed with the “tub” pad 5 , and a plurality of leads 2 laid out surrounding said tub 5 .
  • This thin plate will be referred to as a unit lead section 3 hereinafter.
  • the Lower surface side of said tub suspension leads 4 (excluding outer end portions) and tub 5 is subjected to etching treatment so that the resultant thickness is approximately half of the thickness of other portions.
  • This processing is generally called half-etching treatment.
  • the unit lead section 3 of the embodiment 1 has on its lower surface side a stepped portion 6 due to such half-etching treatment.
  • a semiconductor chip 8 is mounted on an upper surface (one principal surface) of the tub 5 of said unit lead section 3 as shown in FIGS. 6 - 8 .
  • the semiconductor chip 8 may include certain integrated circuitry such as a microcomputer, application-specific integrated circuit (ASIC), gate array, system large-scale integrated circuit (LSI), memory or the like, and a plurality of electrical connection pads 7 made of aluminum (Al) or other similar suituble conductive materials for use as external connection terminals of the integrated circuitry.
  • the semiconductor chip 8 is rigidly bonded by adhesive 9 such as nonconductive paste or nonconductive films with the integrated circuitry facing upwardly.
  • Respective pads 7 of this semiconductor chip 8 are electrically connected to one principal surface of said leads 2 via conductive wires 10 made of gold (Au) or Al or else.
  • Said semiconductor chip 8 , wires 10 , tub 5 , tub suspension leads 4 and leads 2 (upper surface portions and side surface portions) are sealed by a sealing resin material 11 including but not limited to epoxy resin or silicon resin for the purposes of improvement in protectiveness and humidity resistivity. Note however that the lower surface portions (the other principal surface) of the leads 2 for use as external terminals are exposed on the lower side surface side of the semiconductor device.
  • sealed portions 12 Those portions sealed by the sealing resin 11 will be referred to hereafter as sealed portions 12 .
  • a respective one of said leads 2 is specifically fabricated so that its upper surface is greater in area than the exposed lower surface in order to prevent unwanted dropdown detachment from the sealed portion 12 thereof.
  • the leads 2 as exposed from the semiconductor device are subject to external packaging processing including but not limited to soldering metallization using Pb—Sn-based soldering processes.
  • a thin-film fabricated through external packaging processes will be referred to as metallized or metal-plated portion 13 hereafter.
  • Said external packaging may also be done by metal-plating techniques using Pb free solder materials such as Sn—Ag or Sn—Zn-based ones.
  • Designing said metal-plated portion to have a thickness of about 10 micrometers ( ⁇ m) makes it possible for the semiconductor device 1 to retain a stand-off from the lower surface of the sealed portion 12 , which corresponds to the thickness of the metal-plated portion 13 .
  • the plated portion 13 is not depicted in FIGS. 2 and 4 for purposes of convenience in illustration only.
  • the semiconductor device 1 of this is embodiment is such that unlike the prior art with its stepped portion 6 formed by folding machining (up-set processing), the stepped portion 6 is formed by half-etching techniques thereby permitting the sealing resin 11 to exist at such locations; thus, it becomes possible to seal the tub 5 and tub suspension leads 4 with the sealing resin 11 while at the same time realizing the intended thickness-reduced structure, which in turn makes it possible to avoid the problem as to the degradation of reliability otherwise occurring due to a decrease in close contact or adhesiveness as resulted from a decrease in contact area between the sealing resin 11 and the tub 5 .
  • Another advantage of the embodiment is that letting the lower surfaces of the leads 2 be exposed from the lower surface of the sealing section 12 of the semiconductor device 1 for use as external connection terminals makes it possible to prevent deformation of leads during carriage and/or mounting processes to thereby improve the reliability.
  • the leads 2 are projected by little degree from the side surfaces of the seal section 12 , it is possible to achieve miniaturization or “shrinkage” of planar size of the semiconductor device 1 .
  • said leads 2 are arranged so that the upper surface sealed is greater in area than the lower surface exposed, sufficiently enhanced adhesiveness is obtainable to thereby enable retainment of increased reliability, irrespective of the fact that the effective bonding surface with respect to the seal resin 11 consists essentially of the upper and lower surfaces.
  • FIG. 11 is a diagram showing a plan view of a matrix lead frame for use in the manufacture of the semiconductor device in accordance with said embodiment 1;
  • FIG. 12 shows an enlarged plan view (upper surface side) of a unit lead frame (details will be explained later) of the matrix lead frame of FIG. 11;
  • FIG. 13 is an enlarged plan view (lower surface side) of the unit lead frame of the matrix lead frame of FIG. 11;
  • FIG. 14 is a cross-sectional view of the structure of FIG. 12 as taken along line F-F; and, FIG. 15 is a sectional view of the structure of FIG. 12 taken along line G-G.
  • the matrix lead frame 14 shown herein is formed through patterning of a copper- or iron-based metal plate by etching techniques. As shown in FIG. 11, the matrix lead frame 14 is arranged so that a specified number of regions (referred to hereafter as unit lead frame 15 ) each corresponding to the surface area of a single semiconductor device 1 are formed thereon—here, ten separate equally spaced regions consisting of two rows extending in a direction along long sides and five columns along short sides, by way of example.
  • each unit lead frame 15 is slits (referred to hereafter as stress relax slits 16 ) used for relaxation of stress forces as will possibly be applied to the matrix lead frame 14 during manufacturing processes, with guide pins 17 for use as supporting and position alignment pins during manufacturing being formed along the long sides of the matrix lead frame 14 .
  • stress relax slits 16 slits used for relaxation of stress forces as will possibly be applied to the matrix lead frame 14 during manufacturing processes, with guide pins 17 for use as supporting and position alignment pins during manufacturing being formed along the long sides of the matrix lead frame 14 .
  • a tub 5 is centrally disposed over the unit lead frame 15 while being supported by its associated four tub suspension leads 4 , wherein a plurality of leads 2 are provided at those locations in close proximity to the tub 5 in such a manner as to surround the tub 5 , these leads being supported by the frame.
  • the Lower surface side of said tub suspension leads 4 (excluding outer end portions) and tub 5 is subjected to half-etching treatment so that the resultant thickness is about half of the thickness of other portions of the unit lead frame 15 .
  • the unit lead frame 15 of the embodiment 1 has a stepped portion 6 on its lower surface side as shown in FIGS. 14 - 15 .
  • This stepped portion 6 is not the one that is formed at a separate process step (referred to as after- or post-treatment hereafter) after completion of patterning using either punching or etching methods as in the prior art, but the one that permits simultaneous execution of both patterning and half-etching at a time; thus, it is possible to reduce costs for massproduction of the matrix lead frame 14 .
  • the matrix lead frame 14 of the embodiment 1 does no longer require fold/bend machining processes applied to the matrix lead frame after completion of patterning as in the prior art, which in turn makes it possible to prevent occurrence of problems such as tub displacement/strain defects due to such bend/fold machining.
  • FIG. 16 is a conceptual diagram showing a method of depositing adhesive onto a tub
  • FIG. 17 is a conceptual diagram showing a method of mounting a semiconductor chip on the tub
  • FIG. 18 is a conceptual diagram showing a wire-bonding method
  • FIG. 19 is a conceptual diagram showing the state in which a metal frame structure such as metal tool and a matrix lead frame have been position-aligned at a resin sealing process step
  • FIG. 20 is a conceptual diagram showing the state in which the metal tool is clamped at the resin sealing step
  • FIG. 21 is a conceptual diagram showing the state in which the metal tool is disassembled at the resin sealing step.
  • the both metal tools thus clamped have an inner space (referred to as cavity 24 hereafter) that is defined at a level corresponding to the mating surface thereof, which space permits the semiconductor chip 8 and wires 10 plus tub 5 along with tub suspension leads 4 (not shown) and leads 2 (upper surface and side surface portions) to be sealed with the sealing resin 11 .
  • the invention should not exclusively be limited thereto and may alternatively be modifiable in such a manner that a matrix lead frame 14 may be prepared which is such that external packaging treatment such as Pd metallization or the like has been applied in advance to those lead regions as exposed from semiconductor devices.
  • external packaging treatment such as Pd metallization or the like has been applied in advance to those lead regions as exposed from semiconductor devices.
  • the external packaging process is no longer required during the manufacture of the semiconductor device 1 whereby the requisite number of process steps may be reduced thus increasing productivities accordingly.
  • the matrix lead frame 14 is prepared which has its stepped portion 6 as formed by half-etching techniques, the invention should not be limited only to this approach and may alternatively be modified so that a matrix lead frame 14 is prepared with its stepped portion 6 being formed through coiling patterning techniques.
  • FIG. 22 is a diagram showing a perspective view of an exterior appearance showing the state that the semiconductor device in accordance with the embodiment 1 has been mounted to a parts mount substrate
  • FIG. 23 is a sectional view of the device structure of FIG. 22 taken along line H-H.
  • a method is employable which includes the steps of coating or “painting” a chosen bonding material such as cream solders or the like on leads 28 of the mount substrate 27 which correspond to those leads 2 on the lower surface of a sealing section 12 of the semiconductor device 1 , temporarily attaching the semiconductor device 1 to the leads 28 of mount substrate 27 with the bonding material 29 coated thereon, and thereafter performing reflow processes in a heating furnace (not shown).
  • the semiconductor device 1 of the embodiment 1 is as thin as 1 mm, or more or less, in height when mounted while simultaneously permitting its planar dimensions to be significantly smaller than those packages with leads projecting outwardly from lateral sides of a seal section, which packages typically include quad flat package (QFP) structures, thus enabling achievement of high-density mountubilities. It is also possible to prevent occurrence of any unwanted electrical shorting between the tub and leads on a parts-mount substrate because of the fact that each tub is not exposed from the lower surface of its associated semiconductor device unlike the prior art.
  • QFP quad flat package
  • FIG. 24 is a diagram showing a plan view of a unitary lead section of an embodiment 2 of the invention. Note that broken lines are used in FIG. 24 to indicate a seal region.
  • FIG. 25 depicts a cross-sectional view of the unit lead section of FIG. 24 as take along line I-I;
  • FIG. 26 is a sectional view of the unit lead section of FIG. 24 take along line J-J;
  • FIG. 27 is a partial see-through-diagram of a semiconductor device in accordance with the embodiment 2; and,
  • FIG. 28 is a sectional view of the semiconductor device of FIG. 27 taken along line K-K.
  • a difference of the embodiment 2 from embodiment 1 is that whereas the embodiment 1 is the structure capable of sealing each tub 5 and tub suspension leads 4 with the sealing resin 11 because of the presence of the stepped portion 6 on the lower surface side of such tub suspension leads 4 (excluding outer end portions) and tub 5 , the embodiment 2 is arranged to have another stepped portion 6 at distal end portions on the tub 5 side of the leads 2 (referred to hereafter as inner end portions 31 ) in addition to the lower surface side of the tub suspension leads 4 (excluding outer end portions) and tub 5 , thereby making it possible to seal the inner end portions 31 of leads 2 in addition to such tub 5 and tub suspension leads 4 .
  • the remaining parts of the embodiment 2 are substantially the same as those of the embodiment 1; thus, only different points will be explained below, and an explanation as to such similar points will be eliminated herein.
  • a unit lead section 3 of the embodiment 2 has a centrally located tub 5 that is supported by four tub suspension leads 4 , wherein a plurality of leads 2 are provided to surround said tub 5 .
  • Said tub suspension leads 4 (excluding external end portions) and the tub 5 plus inner end portions 31 of the plurality of leads 2 are subjected to half-etching treatment to have a thickness about half of that of the other portions.
  • a semiconductor chip 8 is mounted and secured on the tub 5 by adhesive 9 such as nonconductive paste or nonconductive film or else.
  • This semiconductor chip 8 has respective pads 7 which are electrically connected to said plurality of leads 2 via conductive wires 10 made of Au or Al or the like.
  • the semiconductor chip 8 , wires 10 , tub 5 , tub suspension leads 4 and leads 2 are sealed by a sealing resin material 11 including but not limited to epoxy resin or silicon resin for the purposes of improvement in protectiveness and humidity resistivity.
  • a sealing resin material 11 including but not limited to epoxy resin or silicon resin for the purposes of improvement in protectiveness and humidity resistivity.
  • the lower surfaces of outer end portions 30 of the leads 2 for use as external connection terminals are exposed on the lower surface side of the semiconductor device 1 .
  • the semiconductor device 1 of the embodiment 2 is arranged so that the inner end portions 31 of the leads 2 are subjected to half-etching treatment to form a stepped portion 6 which is then sealed by the sealing resin 11 , thereby enabling the inner end portions 31 of leads 2 to have relatively free shapes.
  • the lower surfaces of the leads 2 as exposed from the seal section 12 are limited in shape to those based on standards and regulations of the Electronic Industries Association of Japan (EIAJ); however, in regard to the leads 2 within the seal section 12 , no specific standards are present thus making it possible to freely design the shape and lead pitch values thereof into optimal ones in a way pursuant to the size of semiconductor chip 8 and also the number of pads used.
  • EIAJ Electronic Industries Association of Japan
  • the embodiment 2 offers similar advantages to those of the embodiment 1 in that i) it has the stepped portion 6 as formed by half-etching treatment, ii) the sealing resin 11 is capable of being exist at such location, iii) the lower surfaces of the leads 2 are exposed from the lower surface of the semiconductor device 1 for use as external connect terminals, and iv) the leads 2 are projected by a very little amount from side surfaces of the seal section 12 ; in addition, regarding the inner end portions 31 of the leads 2 , it is possible to appropriately design the shape and lead pitch values thereof into optimal ones in a way pursuant to the size of semiconductor chip 8 and also the number of pads because of the fact that the stepped portion 6 is formed by half-etching techniques on the lower surfaces of the inner end portions of leads 2 and is then sealed by the seal resin 11 .
  • FIG. 31 is a diagram showing a plan view of an exemplary semiconductor device in accordance with an embodiment 3 of the present invention while letting a sealing section be partly broken to make visible its internal configuration for illustration purposes only;
  • FIG. 32 depicts a cross-sectional view of the semiconductor device shown in FIG. 31 as taken along line L-L;
  • FIG. 33 is a process flow diagram showing an example of the procedure for assembly of the semiconductor device shown in FIG. 31; and, FIGS. 34 ( a ) to ( e ) are sectional flow diagrams showing an exemplary structure per main process step in the assembly of the semiconductor device shown in FIG. 31.
  • the semiconductor device of the embodiment 3 is generally similar to the semiconductor device as set forth in conjunction with the embodiment 2 discussed above, and is a quad flat non-leaded (QFN) package 49 of the peripheral type with a plurality of leads 2 being disposed at the periphery of a back surface 12 a of its sealing section 12 (semiconductor device mounting surface side).
  • QFN quad flat non-leaded
  • the QFN package 49 is structurally arranged to include a tub 5 supporting thereon a semiconductor chip 8 , a sealing member 12 with the semiconductor chip 8 sealed by resin, tub suspension leads 4 for support of the tub 5 , a plurality of leads 2 which are disposed around the tub 5 and exposed to a back surface 12 a of the sealing member 12 while having a thickness-increased portion 2 a and thickness-reduced portion 2 b thinner than the portion 2 a for formation of a stepped portion with respect to a thickness direction, wires 10 which are connecting members for electrical connection between bonding pads (electrodes) 7 of the semiconductor chip 8 and those leads 2 corresponding thereto, and an adhesive 9 such as silver paste for use in bonding the semiconductor chip 8 and tub 5 together.
  • the thickness-increased or “thick” portion 2 a and thickness-reduced or “thin” portion 2 b are provided at a respective one of the leads 2 disposed at the periphery of the back surface 12 a of sealing member 12 whereby the thick portion 2 a of such lead 2 is exposed to the periphery of the back surface 12 a of sealing member 12 while causing the thin portion 2 b to be covered or coated with a sealing resin material 11 .
  • the leads 2 are each formed to provide the thin portion 2 b that is less in thickness than the thick portion 2 a , wherein one of them—i.e. thick portion 2 b to which a wire 10 is to be connected—is buried in the sealing member 12 to function as an inner lead whereas the other, i.e. thick portion 2 a , has its surface exposed to the back surface 12 a of such sealing member 12 , which is for use as a to-be-connected portion 2 c functioning as an outer lead.
  • the tub 5 is supported by the tub suspension leads 4 , and, as shown in FIG. 37 regarding the embodiment 4 as described below, the tub suspension leads 4 are designed to have a support portion 4 a supporting the tub 5 and more than one exposed portion 4 b that is coupled thereto and is exposed to the back surface 12 a of the sealing member 12 , wherein the support portion 4 a is formed to be thinner than the exposed portion 4 b.
  • tub suspension leads 4 are coupled together via the tub 5 , and the exposed portion 4 b of tub suspension leads 4 is the same in thickness as the thick portion 2 a of leads 2 .
  • a respective one of the plurality of tub suspension leads 4 consists essentially of a support section 4 a that is coupled to the tub 5 and is substantially the same in thickness as this tub 5 and more than one exposed portion 4 b that is coupled to this support section 4 a and is greater in thickness than the support section 4 a while causing the plurality of tub suspension leads 4 to be integrally coupled together via the tub 5 .
  • the tub suspension leads 4 are each provided with a step-like level difference due to the presence of such thick portion (exposed section 4 b ) and thin portion (support section 4 a ) with the plurality of tub suspension leads 4 being linked together via the tub 5 .
  • the support section 4 a at the tub suspension leads 4 is buried or embedded within the sealing member 12 whereas the exposed section 4 b is exposed at corner end portions of the back surface 12 a of the sealing member 12 .
  • fabrication of a step-like difference due to the presence of the thick portion 2 a and thin portion 2 b at leads 2 of QFN package 49 (patterning for formation of thick portion 2 b ) and fabrication of a step-like difference due to the support section 4 a and exposed sections 4 b at tub suspension leads 4 (patterning for formation of support section 4 a ) may be performed by etching techniques (e.g. half-etching treatment) as in an embodiment 11, to be described later in the description, or alternatively by press machining such as coiling process as in such later-discussed embodiment 11, by way of example.
  • etching techniques e.g. half-etching treatment
  • a matrix lead frame 14 which is a lead frame comprising a tub S capable of supporting a semiconductor chip 8 , tub suspension leads 4 having a support section 4 a supporting the tub 5 and more than one exposed section 4 b that is coupled to the support section 4 a and is greater in thickness than support section 4 a , a plurality of leads 2 as laid out around the tub 5 with a thick portion 2 a and thin portion 2 b thinner than portion 2 a for formation of a step-like difference or stepped portion with respect to the thickness direction (at step S 1 ).
  • step S 3 perform wire bonding as shown at step S 3 for connection between pads 7 of the semiconductor chip 8 and their corresponding leads 2 by use of wires 10 that are employed as interconnect members.
  • step S 4 Thereafter, perform molding as shown at step S 4 thereby forming a sealing member 12 as shown in FIG. 34( c ).
  • the semiconductor chip 8 is resin-molded by a method including the steps of covering both the thin portions 2 b of leads 2 and the support section 4 a of tub suspension leads 4 with a sealing resin material 11 while letting such seal resin 11 flow onto a surface (referred to hereafter as back surface 5 b ) on the opposite side to a chip support surface 5 a of the tub 5 , with the thick portions 2 a of the plurality of leads 2 and the exposed portions 4 b of tub suspension leads 4 being disposed at the periphery on the back surface 12 a.
  • tub suspension leads 4 subdivide the tub suspension leads 4 into portions at the exposed portions 4 b of tub suspension leads 4 while substantially simultaneously separating the plurality of leads 2 from a frame section 14 a of the matrix lead frame 14 (lead frame), thus completing the QFN package 49 as shown in FIG. 34( e ) (at step S 6 ).
  • the sealing resin material 11 can flow into the thinner part side resulting in occurrence of a need to cut both metals and resin (sealing resin 11 ) together at a lead cut process step thus leading to risks of creation of defects; on the contrary, if the exposed portions 4 b of tub suspension leads 4 and the thick portions 2 a of leads 2 are formed to have the same thickness then the sealing resin 11 will no longer be disposed at cutting locations, which in turn makes it possible to facilitate smooth effectuation of the intended lead cutting processes.
  • FIG. 35 is a diagram showing a perspective view of an exterior appearance of an exemplary structure of a semiconductor device in accordance with an embodiment 4 of the invention
  • FIG. 36 shows a bottom view of the structure of the semiconductor device shown in FIG. 35
  • FIG. 37 is a cross-sectional view of the semiconductor device shown in FIG. 35 taken along line M-M
  • FIG. 38 is a sectional view of the semiconductor device shown in FIG. 35 taken along line N-N
  • FIG. 39 is a partial sectional view of one exemplary state at a wire-bonding process step during assembly of the semiconductor device shown in FIG. 35.
  • the semiconductor device of the embodiment 4 is a QFN package 50 that is essentially similar to the semiconductor device as has been explained in conjunction with the embodiment 3 above.
  • a plurality of tub suspension leads 4 has a support section 4 a for use in supporting a tub 5 and also exposed portions 4 b that are coupled thereto and exposed to the back surface 12 a of a sealing member 12 , wherein the support section 4 a is formed so that it is thinner than the exposed portions 4 b while causing said tub suspension leads 4 be coupled together via the tub 5 .
  • the tub suspension leads 4 are designed so that these are integrally coupled together via the tub 5 while causing the support section 4 a of relatively reduced thickness and exposed portions 4 b of relatively increased thickness to be formed in the tub suspension leads 4 , wherein the exposed portions 4 b which are thick portions in the tub suspension leads 4 are disposed at four corner edge portions of the back surface 12 a of the sealing member 12 as shown in FIG. 36.
  • the support section 4 a in the tub suspension leads 4 is covered by a sealing resin material 11 while simultaneously permitting the exposed portions 4 b to be disposed at the corner edge portions of the back surface 12 a of the sealing member 12 .
  • a chip support surface Sa of the tub 5 and chip mount side surfaces 4 c of the tub suspension leads 4 are formed on the same flat plane.
  • the QFN package 50 of this embodiment 4 is for minimization of exposure of the tub suspension leads 4 to the pack surface 12 a of sealing member 12 to thereby prevent undesired electrical shorting between such tub suspension leads 4 and neighboring leads 2 associated therewith during mounting of a parts mount substrate; to this end, this embodiment is arranged so that the remaining portions (support portion 4 a ) of the tub suspension leads 4 other than the exposed portions 4 b as exposed to the corner edges of the sealing member 12 are buried or embedded within the sealing member 12 .
  • the exposed portions 4 b that are thick portions in the tub suspension leads 4 come to have those portions at which any sealing resin 11 is not disposed and which consists of only metals—here, the tub suspension leads 4 will later be subject to lead cutting processes.
  • the support section 4 a of tub suspension leads 4 is formed to be less in thickness than the exposed portions 4 b by using either etching techniques (half-etching treatment) or press machining such as coiling methods, rather than by using tub-up processing through bend machining, to thereby ensure that the support surface Sa of the tub 5 and the chip mount side surfaces 4 c of the tub suspension leads 4 are formed on the same flat plane; thus, the tub 5 and the support section 4 a of tub suspension leads 4 are formed to have the same thickness as shown in FIG. 37.
  • tub 5 and the support section 4 a which is the same in thickness as tub 5 have a thickness ranging from about 0.08 to 0.1 mm (cutaway amount is 0.1 to 0.12 mm).
  • the tub 5 supporting thereon a semiconductor chip 8 is formed so that it is smaller in size than the semiconductor chip 8 .
  • the QFN package 50 is the one of small size tub structure.
  • the tub 5 and the semiconductor chip 8 are rigidly secured (die-bonded) together by adhesive 9 such as silver paste at specified portions (positions) lying inside of bonding pads 7 of the semiconductor chip 8 .
  • a manufacturing method of the QFN package 50 of the embodiment 4 is substantially the same as that of the QFN package 49 of the embodiment 3, except that when letting a semiconductor chip 8 be adhered to its associated tub 5 at the die bonding process step, the semiconductor chip 8 is brought into contact with the tub 5 at locations (regions) inside of its pads 7 .
  • Another advantage is that since the sealing resin 11 is no longer disposed at the exposed portions 4 b due to the fact that the exposed portions 4 b are thicker than the support section 4 a at the tub suspension leads 4 , it becomes possible to ensure that only those metals of exposed portions 4 b which contain none of the sealing resin 11 are cut away during cutting of the tub suspension leads 4 , thereby preventing creation of any possible nick or gouge defects, which in turn makes it possible to improve the cutting performance at tub suspension lead cutting process steps.
  • Still another advantage lies in an ability to improve the surface flatness of the tub 5 per se due to the fact that the jointing of the plurality of tub suspension leads 4 via the tub 5 permits the tub 5 to be integrally coupled with the tub suspension leads 4 while allowing them to be formed of a well planarized plane coupled with the chip mount side surface thereof.
  • a further advantage is that letting the tub 5 and semiconductor chip 8 be contacted together at inside locations than the pads 7 of semiconductor chip 8 makes it possible to support by the bonding stage 20 those portions in close proximity to the ends of the back surface 8 b of semiconductor chip 8 .
  • FIG. 40 is a diagram showing a partial plan view of one example of the resultant structure when completion of molding in a semiconductor device in accordance with an embodiment 5 of the instant invention, which structure is partly broken to visualize its internal configuration for illustration purposes only;
  • FIG. 41 depicts a cross-sectional view of the semiconductor device shown in FIG. 40 as taken along line P-P;
  • FIG. 42 is a partial plan view of an exemplary lead frame structure for use during assembly of the semiconductor device shown in FIG. 40;
  • FIG. 43 is an enlarged partial sectional view of a structure of part “T” of FIG. 41;
  • FIG. 44 is an enlarged partial sectional view for showing an exemplary lead cutting method at the part T of FIG. 41;
  • FIG. 45 is a diagram showing a lead structure of part “Q” of FIG. 40, wherein (a) is a bottom view, (b) is a plan view, (c) is a sectional view of a groove section, (d) is a sectional view along line U-U of (b), (e) is a sectional view along line V-V of (b); and, FIG. 46 is a plan view of one possible modified example of the lead structure of part Q of FIG. 40.
  • FIG. 40 depicts an inside structure of a sealing member 12 at the termination of a molding process while presenting it in a manner as seen transparently through the sealing member 12 and semiconductor chip 8 for illustration purposes only.
  • a tub 5 shown in FIG. 40 is of the cross-type small tub structure (wherein the tub 5 is smaller in size than the semiconductor chip 8 ).
  • a respective one of the plurality of leads 2 has a to be-connected portion 2 c as exposed to the periphery of a back surface 12 a of the sealing member 12 and a thickness reduced or “thin” portion 2 b as formed at an end on the tub 5 side to be thinner than to-be-connected portion 2 c , wherein each lead 2 is provided with an inner groove portion (groove) 2 e and outer groove portion (groove) 2 f in a specified surface of the to-be-connected portion 2 c (this surface will be referred to as a wire bonding surface 2 d hereinafter) on the opposite side to the exposed side as disposed within the sealing member 12 .
  • pads 7 of semiconductor chip 8 are connected by wires 10 to wire bonding surfaces 2 d of to-be-connected portions 2 c of those leads 2 corresponding thereto while causing the thin portions 2 b of such leads 2 to be covered by a sealing resin material 11 with the wires 10 being bonded to the to be-connected portions 2 c between the outer grooves 2 f and inner grooves 2 e.
  • the thin portions 2 b of the leads 2 of the embodiment 5 are formed into a knife-edge or “sword tip”-like shape to permit its tub side end to slightly project toward the tub 5 , which shape may be fabricated through etching treatment (half-etching patterning) and/or press machining such as coiling.
  • An exemplary amount of such projection may range from about 50 to 150 ⁇ m.
  • the inner grooves 2 e as provided in the wire bond surfaces 2 d of the leads 2 are for use as markings indicative of bonding points during wire bonding. Accordingly, by forming such inner grooves 2 e in the wire bonding surfaces 2 d of leads 2 in specified regions lying outside of the thin portions 2 b , it becomes possible to prevent the wires 10 from being bonded at such thin portions 2 b.
  • inner grooves 2 e are the grooves acting as the bonding point marks, the size thereof is smaller than that of outer grooves 2 f as shown in FIG. 45.
  • the outer grooves 2 f are the locations for receival of cutting stress forces during cutting of the leads 2 ; during lead cutting as shown in FIG. 44, let any possible cutting stress forces be concentrated to these outer grooves 2 f to ensure that no such forces are hardly applied to bonding portions of the wires 10 .
  • the outer grooves 2 f are the ones for use in blocking a flow of hot-melt metals for metallization on the wire bonding surfaces 2 d of the leads 2 during formation of a metallized layer 21 such as at a wire bonding silver metallization step as shown in FIG. 43.
  • the outer grooves 2 f are formed so that these are greater in size than the inner grooves 2 e . This makes it possible to reliably perform both prevention of unwanted concentration of stress forces during lead cutting and also undesired metal flowage during metallization processes.
  • outer grooves 2 f and inner grooves 2 e should not be limited to those discussed above and may alternatively be modified so that the both of them have an elliptical shape of the same size as shown in FIG. 46, by way of example.
  • the leads 2 are such that each is provided on its side surfaces with knife edge portions 2 g which are projected by little toward the width direction thereof.
  • provision of the inner grooves 2 e and outer grooves 2 f in the wire bonding surfaces 2 d of leads 2 permits the sealing resin material 11 to enter and fill the both groove portions; thus, it is possible to prevent unwanted dropdown detachment of the leads 2 in the elongate direction thereof (QFN horizontal direction at right angles to the QFN height direction). In short, it is possible to prevent pullout of the leads 2 toward the extending direction thereof.
  • the pads 7 of semiconductor chip 8 are connected by wires 10 to specified portions lying between the inner grooves 2 e and outer grooves 2 f at the to-be-connected portions 2 c of leads 2 as shown in FIG. 41 when connecting by wire bonding techniques the pads 7 of semiconductor chip 8 to the to-be-connected portion 2 c of corresponding leads 2 during a wire bonding process.
  • outer groove 2 f which is a single groove may be provided in the wire bonding surface 2 d of a lead 2 ; if this is the case, a wire 10 will be bonded for electrical connection to its associated to-be-connected portion 2 c at an inside location relative to the outer groove 2 f.
  • the inner groove 2 e which is a single groove may be provided in the wire bonding surface 2 d of a lead 2 ; in such case, a wire 10 will be bonded to a to-be-connected portion 2 c at part lying outside of the inner groove 2 e.
  • FIG. 47 is a diagram showing an enlarged partial plan view of a structure of part “R” of FIG. 40, which has been explained in conjunction with the embodiment 5 above.
  • the embodiment 6 is directed to a case where certain leads 2 of the plurality of leads 2 which are disposed neighboring a tub suspension lead 4 and placed on the opposite sides thereof-are taken up, wherein a tapered section (cutaway portion) 2 h is provided at a selected distal end of each lead 2 opposing the tub suspension lead 4 for formation of a gap 2 i lying between the lead 2 and tub suspension lead 4 and extending along this lead 4 .
  • This taper section 2 h is a cutaway portion for formation of the gap 2 i as required for effectuation of necessary processes when forming a lead pattern by etching treatment or press machining techniques-for example, a gap of about 80% of a lead plate thickness will be required for patterning purposes.
  • tub suspension lead side distal end of a lead 2 neighboring a tub suspension lead 4 comes closer to the tub suspension lead 4 so that it will become impossible or at least greatly difficult to perform the intended patterning of such tub suspension lead 4 or alternatively its neighboring lead 2 .
  • FIG. 48 is a diagram showing a structure of part “S” of FIG. 40 as has been explained in conjunction with the embodiment 5, wherein a portion (a) is an enlarged partial plan view whereas (b) is a sectional view of (a) as taken along line X-X; and FIG. 49 is a diagram showing a structure of part “W” of FIG. 48( a ), wherein (a) is an enlarged partial plan view and (b) is a groove sectional view of (a).
  • the embodiment 7 is directed to a case where the plurality of (four) tub suspension leads 4 for use in supporting a tub 5 are designed so that each of the tub suspension leads 4 comprises an exposed portion 4 b as exposed to an end portion of a back surface 12 a of a sealing member 12 and a groove portion 4 d which is a thickness-reduced or “thin” portion bridging between the inside and outside of a molding line 12 b (outer periphery) of the sealing member 12 .
  • a molding metal frame structure's gate 26 (see FIG. 19) is formed at a nearby location corresponding to the mold line 12 b of the tub suspension leads 4 ; accordingly, a sealing resin material 11 is formed to have an increased thickness at or near such location resulting in that the tub suspension leads 4 are cut in a way that resembles breaking (pull-put destruction) at lead cutting process steps.
  • this groove 4 d is a notch (cutaway) for permitting concentration of stress forces to thereby ensure that the breaking (cutting) of the tub suspension leads 4 is readily done during lead cutting processes, which notch is formed at a preselected location corresponding to the mold line 12 b of the sealing member 12 of the tub suspension leads 4 (region linking between the inside and outside of the mold line 12 b ) for giving a chance during breaking of the tub suspension leads.
  • the groove 4 d is formed in the exposure side surface of a tub suspension lead 4 lying on the opposite side to a chip mount side surface 4 c thereof.
  • the groove 4 d is formed in the surface of tub suspension lead 4 corresponding to the back surface 12 a side (back side) of the sealing member 12 .
  • the groove 4 d is formed into an elliptical shape that is lengthened in the elongate direction of a tub suspension lead 4 , and further is surrounded by a sidewall 4 e.
  • the sealing member 12 is fabricated through resin molding processes while letting the groove 4 d of tub suspension lead 4 correspond to the mold line 12 b (outer periphery) of the sealing member 12 at a molding process step. More specifically the sealing member 12 is formed to ensure that the ellipse-shaped groove 4 d at the tub suspension lead 4 is disposed bridging between the inside and outside of the mold line 12 b.
  • FIG. 50 is a diagram showing an exemplary structure of a semiconductor device in accordance with an embodiment 8 of this invention, wherein (a) is a plan view, (b) is a side view, and (c) is a bottom view; and FIG. 51 is an enlarged partial bottom view of a structure of part “Y” of FIG. 50( c ).
  • the embodiment 8 is the case where the length of the exposed portion 4 b of tub suspension lead 4 in its elongate direction is formed to be shorter than the length of the to-be-connected portion 2 c of lead 2 in the elongate direction thereof.
  • the length (LX) of the exposed portion 4 b of tub suspension lead 4 be formed so that it is shorter than the length (LP) of the to-be-connected portion 2 c of lead 2 (LX ⁇ LP). Furthermore, it will be preferable that a relation of a distance (LY) between the to-be-connected portion 2 c of a lead 2 neighboring the tub suspension lead 4 and the exposed portion 4 b of such tub suspension lead 4 versus a distance (LZ) between neighboring leads be designed to satisfy (LY) ⁇ (LZ).
  • FIG. 52 is a diagram showing a partial plan view of an exemplary structure of a semiconductor device in accordance with an embodiment 9 of the invention as obtained at termination of molding, the structure having an internal configuration as seen through a seal section thereof;
  • FIG. 53 is a cross-sectional view of the semiconductor device shown in FIG. 52 as taken along line Z-Z;
  • FIG. 54 is an enlarged partial sectional view of a structure of the device at part “AB” of FIG. 53;
  • FIG. 55 is an enlarged partial sectional view diagram showing one example of a method of cutting leads at the part “AB” of FIG. 53.
  • leads 2 in a semiconductor device that comprises a plurality of leads 2 having extension portions 2 j that extend toward the center of a tub 5 or its nearby part and are disposed in close proximity thereto, along with effects and advantages thereof.
  • FIG. 52 is the one that depicts an inside structure of a sealing member 12 obtained at the termination of molding as seen transparently through the sealing member 12 and a semiconductor chip 8 for illustration purposes.
  • the semiconductor device of the embodiment 9 is arranged so that a respective one of the plurality of leads 2 as disposed around a tub 5 has an extended portion 2 j extending toward the center of such tub 5 or its nearby part and is laid out in close proximity thereto and a to-be-connected portion 2 c as exposed to the periphery of a back surface 12 a of the sealing member 12 , wherein the extension 2 j of each lead 2 is formed to be thinner than the to-be-connected portion 2 c and is covered by a sealing resin material 11 , and wherein a lead groove portion (groove) 2 k is formed in a wire bonding surface 2 d that is a surface of the to-be-connected portion 2 c on the opposite side to an exposure side as disposed within the sealing member 12 .
  • the semiconductor device of the embodiment 9 is the one which is structurally designed so that the extension 2 j is provided at a tub side end of each lead 2 for extending this lead to thereby eliminate increase in distance between the leads 2 and semiconductor chip 8 when enlargement of a package and shrinkage of semiconductor chip 8 due to an increase in pin number would result in an increase in distance between lead 2 and semiconductor chip 8 .
  • each lead 2 is provided at its tub side end with an extension 2 j extending toward the center of the tub 5 or its nearby location (toward its corresponding pad 7 ), thus facilitating bonding of a wire 10 thereto.
  • each lead 2 is formed into a shape that is radially extended from nearby periphery of the tub 5 toward the outside as shown in FIG. 52.
  • the extension 2 j since the length (LP) of the to-be-connected portion 2 c as exposed to the back surface 12 a of the sealing member 12 is defined by the EIAJ standards as shown in FIG. 54, the extension 2 j must be buried or embedded within the sealing member 12 in the event that the lead 2 is provided with such extension 2 j ; in view of this, the semiconductor device of the embodiment 9 is specifically arranged so that the extension 2 j is formed to be thinner than the to-be-connected portion 2 c and is then embedded within the sealing member 12 without having to make higher the position of the extension 2 j (without performing any lead rise-up processing).
  • the extension 2 j at each lead 2 is formed so that it is thinner than the to-be-connected portion 2 c as exposed to the back surface 12 a of the sealing member 12 and is simultaneously covered by the sealing resin 11 together with the tub 5 .
  • the thinner formation of the extension 2 j than the to-be-connected portion 2 c makes it possible to prevent dropdown detachment of its associative lead 2 in the thickness direction of the sealing member 12 .
  • extension 2 j has an increased distance in its elongate direction in comparison with the knife edge-shaped thin portion 2 b shown in FIG. 41, it is also possible to dispose the bonding stage 20 (see FIG. 39) at a specified location beneath the extension 2 j during wire bonding, which in turn makes it possible to apply optimal ultrasonic waves or heat to both the wires 10 and the leads 2 during wire bonding.
  • extension 2 j may be formed thinner by etching treatment (half-etching patterning) or alternatively press machining techniques such as coiling.
  • a lead groove portion (groove) 2 k is formed at a selected location of the to-be-connected portion 2 c of each lead 2 near the outside of the wire bonding surface 2 d (surface on the opposite side to the exposure side) that is laid out within the sealing member 12 .
  • This lead groove 2 k is the same in function to the outer groove portion 2 f (see FIG. 43) as has been explained in conjunction with the embodiment 5; thus, it is possible to concentrate cutting stress forces to this lead groove 2 k during cutting processes using a punch 54 shown in FIG. 55, thereby preventing such stresses from being applied to bonding portions of wires 10 .
  • the presence of the lead groove 2 k makes it possible to block a flow of hot-melt metals when forming a metal-plated layer 21 such as a silver-metallized one used for wire bonding purposes as shown in FIG. 54.
  • FIGS. 56 ( a ), ( b ), ( c ), ( d ), FIGS. 57 ( a ), ( b ), ( c ), ( d ), and FIGS. 58 ( a ), ( b ), ( c ), ( d ) are partial sectional diagrams showing a patterning method using etch techniques as one example of a lead frame machining method used for assembly of the semiconductor device in accordance with the invention.
  • the embodiment 10 is for explanation of one exemplary patterning method of leads 2 and tub 5 of any one of the semiconductor devices as stated supra in conjunction with the embodiments 1 to 9, etching treatment (half-etching patterning) will be explained.
  • etching liquid or etchant 52 as used during etch patterning of the embodiment 10 is liquid solution of iron (II) oxide or else, although not exclusively limited thereto.
  • FIGS. 56 ( a ), ( b ), ( c ), ( d ) show a method (procedure) of fabricating the intended sectional shape or “profile” of leads 2 such as shown in FIG. 45( e ) for example;
  • FIGS. 57 ( a ), ( b ), ( c ), ( d ) show a method (procedure) of fabricating the profile of leads 2 such as shown in FIG. 45( d ) by way of example.
  • the etching amount on the top and bottom surfaces of leads 2 is appropriately adjusted by changing or varying the opening width (aperture area) of certain parts (portions “A” and “B”) whereat a photoresist film 53 is not formed, thus enabling obtainment of respective sectional shapes.
  • FIGS. 58 ( a ), ( b ), ( c ), ( d ) show a method (procedure) of back-surface processing of the tub 5 shown in FIG. 53 and also performing thinning processing of extensions 2 j of leads 2 , for example.
  • FIG. 58( a ) fabricate a photoresist film 53 at fine pitch (B) only on the processing surface side of the tub 5 and the like; then, as shown in FIG. 58( b ), coat or “paint” etching liquid 52 only on said processing side, thereby realizing the intended back-surface processing of the tub 5 and the thinning processing of the extensions 2 j of leads.
  • FIGS. 59 ( a ), ( b ), ( c ), FIGS. 60 ( a ), ( b ), ( c ), and FIGS. 61 ( a ), ( b ), ( c ) are partial sectional diagrams showing press methodology as one example of a lead frame machining method used for assembly of the semiconductor device of the invention.
  • the embodiment 11 is for explanation of one example of the processing method of the leads 2 and tub 5 of the semiconductor devices as has been explained in conjunction with the embodiments 1 to 9 stated supra—here, press machining such as coiling will be explained below.
  • FIGS. 59 ( a ), ( b ), ( c ) show a method (procedure) of performing by press machining techniques the back-surface processing of the tub 5 shown in FIG. 53 for example;
  • FIGS. 60 ( a ), ( b ), ( c ) show a method (procedure) of performing thinning of the extensions 2 j of leads 2 shown in FIG. 53 by press machining techniques, by way of example.
  • the both of them are for thinning either the tub 5 supported by a receiving base or pedestal 55 or the leads 2 or else through coiling by use of a punch 54 .
  • said coiling may be carried out at the beginning of raw material processing; or alternatively, said coiling may be applied to only necessary portions after completion of fabrication of a lead frame pattern.
  • FIGS. 61 ( a ), ( b ), ( c ) show a method (procedure) of forming the lead profile as shown for example in FIG. 45( d ) by use of press machining techniques.
  • tub 5 is of a circular or cross-like shape
  • shape of such tub 5 should not be limited thereto and may be replaced with any one of those for use in semiconductor devices in accordance with modified examples as shown in FIGS. 62 and 64.
  • the tub 5 shown in FIGS. 62 and 63 is designed to have a small tub structure by quartering; in this case, it is possible to improve the shrinkability of such tub 5 in the horizontal direction (direction horizontal relative to tub suspension leads 4 ) to thereby improve the temperature cycling characteristics of semiconductor devices, which in turn makes it possible to reduce chip cracking and/or package cracking accidents.
  • the tub 5 shown in FIG. 64 is designed to have a frame-shaped small tub structure; in this case, as it is possible to increase the bonding area of a sealing resin material 11 and the back surface 8 b of a semiconductor chip 8 , it becomes possible to suppress peel-off of the semiconductor chip 8 and others.
  • the lead frame used therein is the matrix lead frame 14
  • said lead frame may alternatively be modified to employ a multi-string configuration with the unit lead frames 15 being laid out into a single linear array.
  • the semiconductor device used is a small size QFN package
  • said semiconductor device may be modified to those semiconductor devices of the types other than the QFN as far as they are of the peripheral type as assembled using the lead frame.
  • leads are formed to have their sealed or hermetic upper surfaces wider than exposed lower surfaces thereof, it is possible to attain sufficiently increased adhesiveness irrespective of the fact that the resulting bonding surfaces with the sealing resin consist of upper and side surfaces only, thereby enabling retainment of the reliability required.
  • tub support section at tub suspension leads is formed to be thinner than the exposed portion, it is possible to attain the intended structure with the exposed portion being exposed only to corner edge portions of the back surface of a sealing section. Whereby, it is possible to increase or maximize the clearance as defined on the back surface of the seal section between the exposed portions of the tub suspension leads and its neighboring leads; in addition, arranging the tub to be embedded within the seal section makes it possible to prevent electrical shorting otherwise occurring when mounting a semiconductor device onto a parts-mount substrate.
  • tub suspension leads are coupled together via a tub resulting in integral linkage between the tub and the tub suspension leads while permitting formation by a flat plane coupled to its chip mount side surface, the surface flatness of the tub per se may be improved. As a result, it is possible to make easier the procedure of mounting a semiconductor chip onto the tub during bonding while simultaneously improving the chip adhesiveness.
  • tub and its associative semiconductor chip are bonded together at a selected location lying inside of an array of surface electrodes of the semiconductor chip, it is possible to stubly support by a bonding stage those portions at or near the end portions on the back surface of the semiconductor chip.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
US10/227,817 1999-06-30 2002-08-27 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device Abandoned US20030001249A1 (en)

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US10/227,817 US20030001249A1 (en) 1999-06-30 2002-08-27 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US10/879,010 US7804159B2 (en) 1999-06-30 2004-06-30 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US12/222,099 US7777312B2 (en) 1999-06-30 2008-08-01 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US12/610,900 US7821119B2 (en) 1999-06-30 2009-11-02 Semiconductor device
US12/897,221 US8115298B2 (en) 1999-06-30 2010-10-04 Semiconductor device
US13/357,076 US8637965B2 (en) 1999-06-30 2012-01-24 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US14/108,507 US8969138B2 (en) 1999-06-30 2013-12-17 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US14/623,032 US9484288B2 (en) 1999-06-30 2015-02-16 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US15/166,603 US20160276253A1 (en) 1999-06-30 2016-05-27 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

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US62334400A 2000-08-31 2000-08-31
US10/227,817 US20030001249A1 (en) 1999-06-30 2002-08-27 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

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US62334400A Continuation 1999-06-30 2000-08-31

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US10/879,010 Expired - Fee Related US7804159B2 (en) 1999-06-30 2004-06-30 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US12/222,099 Expired - Fee Related US7777312B2 (en) 1999-06-30 2008-08-01 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US12/610,900 Expired - Fee Related US7821119B2 (en) 1999-06-30 2009-11-02 Semiconductor device
US12/897,221 Expired - Fee Related US8115298B2 (en) 1999-06-30 2010-10-04 Semiconductor device
US13/357,076 Expired - Fee Related US8637965B2 (en) 1999-06-30 2012-01-24 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US14/108,507 Expired - Fee Related US8969138B2 (en) 1999-06-30 2013-12-17 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US14/623,032 Expired - Lifetime US9484288B2 (en) 1999-06-30 2015-02-16 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US15/166,603 Abandoned US20160276253A1 (en) 1999-06-30 2016-05-27 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

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US12/222,099 Expired - Fee Related US7777312B2 (en) 1999-06-30 2008-08-01 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US12/610,900 Expired - Fee Related US7821119B2 (en) 1999-06-30 2009-11-02 Semiconductor device
US12/897,221 Expired - Fee Related US8115298B2 (en) 1999-06-30 2010-10-04 Semiconductor device
US13/357,076 Expired - Fee Related US8637965B2 (en) 1999-06-30 2012-01-24 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US14/108,507 Expired - Fee Related US8969138B2 (en) 1999-06-30 2013-12-17 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US14/623,032 Expired - Lifetime US9484288B2 (en) 1999-06-30 2015-02-16 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device
US15/166,603 Abandoned US20160276253A1 (en) 1999-06-30 2016-05-27 Semiconductor device and a method of manufacturing the same and a mounting structure of a semiconductor device

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JP4388586B2 (ja) 2009-12-24
US20040232442A1 (en) 2004-11-25
KR20080005312A (ko) 2008-01-10
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US8969138B2 (en) 2015-03-03
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