TWI704251B - 字元線應用所使用的鎢 - Google Patents

字元線應用所使用的鎢 Download PDF

Info

Publication number
TWI704251B
TWI704251B TW105104238A TW105104238A TWI704251B TW I704251 B TWI704251 B TW I704251B TW 105104238 A TW105104238 A TW 105104238A TW 105104238 A TW105104238 A TW 105104238A TW I704251 B TWI704251 B TW I704251B
Authority
TW
Taiwan
Prior art keywords
tungsten
substrate
depositing
component
patent application
Prior art date
Application number
TW105104238A
Other languages
English (en)
Other versions
TW201700773A (zh
Inventor
米歇爾 丹納克
漢娜 班諾爾克
拉許納 胡瑪雲
高舉文
Original Assignee
美商蘭姆研究公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商蘭姆研究公司 filed Critical 美商蘭姆研究公司
Publication of TW201700773A publication Critical patent/TW201700773A/zh
Application granted granted Critical
Publication of TWI704251B publication Critical patent/TWI704251B/zh

Links

Images

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/02Pretreatment of the material to be coated
    • C23C16/0272Deposition of sub-layers, e.g. to promote the adhesion of the main coating
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/06Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material
    • C23C16/08Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of metallic material from metal halides
    • C23C16/14Deposition of only one other metal element
    • CCHEMISTRY; METALLURGY
    • C23COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
    • C23CCOATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C16/00Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28556Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD
    • H01L21/28562Selective deposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76843Barrier, adhesion or liner layers formed in openings in a dielectric
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76853Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H01L21/76855After-treatment introducing at least one additional element into the layer
    • H01L21/76856After-treatment introducing at least one additional element into the layer by treatment in plasmas or gaseous environments, e.g. nitriding a refractory metal liner
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/76871Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H01L21/76876Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for deposition from the gas phase, e.g. CVD
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/01Manufacture or treatment
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/48Data lines or contacts therefor
    • H10B12/488Word lines
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B43/00EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53257Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
    • H01L23/53266Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401Multistep manufacturing processes
    • H01L29/4011Multistep manufacturing processes for data storage electrodes
    • H01L29/40117Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B12/00Dynamic random access memory [DRAM] devices
    • H10B12/30DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/34DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being at least partially in a trench in the substrate
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B41/00Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Composite Materials (AREA)
  • Inorganic Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Chemical Vapour Deposition (AREA)
  • Semiconductor Memories (AREA)

Abstract

本文所揭露的是在記憶體元件中形成鎢字元線之方法及相關設備。本文亦揭露的是用於沉積無氟鎢(FFW)之方法及相關設備。根據各種實施例,該等方法涉及使用鎢氯化物(WClx )前驅物及含硼(B)、含矽(Si)或含鍺(Ge)還原劑之多成分鎢膜之沉積。

Description

字元線應用所使用的鎢
本發明係關於字元線應用所使用的鎢。
使用化學氣相沉積(CVD)技術的鎢(W)膜沉積是半導體製造處理的必要部分。例如,鎢膜可能以水平內連線、在相鄰金屬層之間的介層窗(via)、以及在第一金屬層和矽基板上的元件之間的接觸窗(contact)的形式被使用做為低電阻的電連接。在示例的鎢沉積處理中,阻障層被沉積在介電基板上,接著沉積鎢膜的薄成核層。此後,鎢膜的其餘部分被沉積在成核層上作為主體層。通常,鎢主體層係藉由在化學氣相沉積處理中利用氫氣(H2)將六氟化鎢(WF6)還原而形成。
鎢膜亦可使用在各種記憶體應用,包括動態隨機存取記憶體(DRAM)之埋藏字元線(bWL)結構之形成。在bWL沉積之範例中,可藉由使用WF6之CVD處理而將鎢層沉積在鈦氮化物(TiN)層上以形成TiN/W雙層。
本文所揭露的是在基板上沉積鎢的方法。在某些實施例中,該方法包括:脈衝式輸送(pulsing)還原劑,其中該還原劑係含硼(B)、含矽(Si)或含鍺(Ge);及脈衝式輸送鎢氯化物前驅物,其中該鎢氯化物前驅物係藉由 該還原劑或其產物加以還原,以在基板上形成多成分含鎢膜,該多成分含鎢膜包括B、Si及Ge其中一或多者。
在某些實施例中,該方法涉及脈衝式輸送第三反應物以形成三元含鎢膜。第三反應物可為含氮或含碳反應物,俾使三元含鎢膜包括鎢、矽、鍺及硼其中一者、及碳及氮其中一者。包括矽、鍺、硼、碳及氮其中二或更多者之四元及更多元膜可以被形成。在某些實施例中,該多成分膜是二元膜。
在某些實施例中,多成分含鎢膜是用於字元線之擴散阻障物。在某些實施例中,多成分含鎢膜是用於金屬閘極之功函數層。
在某些實施例中,在鎢氯化物脈衝期間之基板溫度是至少400℃。在某些實施例中,在鎢氯化物脈衝期間之基板溫度是至少450℃。在某些實施例中,在鎢氯化物脈衝期間之基板溫度是至少500℃。在某些實施例中,在鎢氯化物脈衝期間之基板溫度是至少550℃。
在某些實施例中,在鎢氯化物及還原劑脈衝期間之基板溫度是至少400℃。在某些實施例中,在鎢氯化物及還原劑脈衝期間之基板溫度是至少450°C。在某些實施例中,在鎢氯化物及還原劑脈衝期間之基板溫度是至少500℃。在某些實施例中,在鎢氯化物及還原劑脈衝期間之基板溫度是至少550℃。
該方法可更包括沉積主體鎢(W)層在多成分含鎢膜上。在某些實施例中,藉由在鎢氯化物前驅物與還原劑之間之化學氣相沉積(CVD)反應以沉積主體W層。
在某些實施例中,主體層可直接沉積在多成分含鎢膜上,無需中介層。
根據各種實施例,多成分含鎢膜係直接沉積在絕緣膜上,例如在氧化物或氮化物膜上。在某些實施例中,該方法涉及還原劑之分解以形成一層B、Si或Ge在基板上。
亦提出記憶體結構。在某些實施例中,記憶體結構可包括包含B、Si及Ge其中一或多者之多成分含鎢膜之襯墊層;及鎢字元線。在某些實施例中,記憶體結構可包括包含B、Si及Ge其中一或多者之多成分含鎢膜之功函數層;及金屬閘極。
以下將參考著圖式進一步描述這些及其它態樣。
9:矽基板
11:埋藏字元線(bWL)
12:保形阻障層
13:絕緣層
21:字元線
22:保形阻障層
23:3D NAND結構
24:柱狀收縮部
30:基板
31:金屬閘極
32:VNAND結構
33:半導體通道
35:穿隧介電層
37:電荷儲存層
39:功函數層
41:阻擋介電質
302:方塊
304:方塊
306:方塊
307:方塊
308:方塊
309:方塊
312:方塊
352:方塊
354:方塊
400:系統
401:晶圓來源模組
403:傳送模組
407:模組
409:多站反應器
411:站
413:站
415:站
417:站
419:常壓傳送腔室
421:負載鎖室
429:系統控制器
圖1描繪動態隨機存取記憶體(DRAM)架構之概要範例,該動態隨機存取記憶體架構包括埋藏字元線(bWL)在矽基板中。
圖2A描繪三維(3D)NAND結構之概要範例,該3D NAND結構包括鎢字元線。
圖2B為部分製造的3D NAND結構之三維特徵部之二維(2D)寫實圖,該3D NAND結構包括鎢字元線。
圖2C顯示垂直NAND結構之概要範例,該垂直NAND結構包括含鎢功函數層。
圖3A顯示可用於形成含鎢二元或三元膜之方法之範例。
圖3B顯示可用於填充特徵部之方法之範例。
圖4為根據本發明之實施例之適用於實施鎢沉積處理之處理系統之方塊圖。
在以下敘述中,數個特定細節被提出以提供對於所述實施例之徹底了解。所揭露的實施例可在沒有這些特定細節之部分或全部之情況下加以實施。在其它的情況下,熟知的處理操作並未詳細地描述以免不必要地混淆所揭 露的實施例。雖然所揭露的實施例將結合特定實施例而加以敘述,但應當了解,其並非用來限制所揭露的實施例。
半導體元件製造通常涉及鎢膜之沉積,例如在溝渠或介層窗中以形成內連線。在習知的鎢膜沉積方法中,先將成核鎢層沉積在介層窗或接觸窗中。通常,成核層是薄保形層,用於幫助隨後的主體材料形成於其上。可將鎢成核層沉積以保形地覆蓋特徵部之側壁及底部。下方特徵部底部及側壁之保形對於維持高品質的沉積可能是關鍵的。成核層之沉積通常使用原子層沉積(ALD)或脈衝式成核層(PNL)方法。
在PNL技術中,反應物之脈衝係相繼地注入及從反應腔室清除,通常藉由在反應物之間之吹淨氣體(purge gas)之脈衝。第一反應物可吸附在基板上,可用於與下一反應物進行反應。以循環的方式重複該處理,直到達成想要的厚度。PNL類似於ALD技術。PNL與ALD之大致區別在於其較高的操作壓力範圍(大於1Torr)及其每循環較高的成長速率(每循環大於1單層膜成長)。在PNL沉積期間之腔室壓力可介於約1Torr至約400Torr之範圍。在本文所提出之敘述內容中,PNL概括地包含相繼地加入反應物以在半導體基板上進行反應之任何循環處理。因此,該概念包含習知稱為ALD之技術。在所揭露的實施例之內容中,CVD包含其中將反應物一起引入反應器以進行氣相反應之處理。PNL及ALD處理與CVD處理是有區別的,反之亦然。
在沉積鎢成核層之後,一般藉由使用例如氫(H2)之還原劑以還原六氟化鎢(WF6)之化學氣相沉積(CVD)處理以沉積主體鎢。
習知的鎢沉積涉及含氟前驅物WF6之使用。然而,WF6之使用會導致一些氟併入所沉積的鎢膜中。當元件縮小時,特徵部變得更小且有害的影響電遷移和離子擴散變得更顯著,因而造成元件失效。氟之存在可能造成電遷移 及/或氟擴散至相鄰部分中,因而減低元件之效能。包括微量氟之鎢膜可能因此造成整合及可靠度問題、以及與下方膜有關之元件效能問題。
本文所揭露的是用於在記憶體元件中形成鎢字元線之方法及相關設備。本文亦揭露的是用以沉積無氟鎢(fluorine-free tungsten,FFW)之方法及相關設備。圖1描繪DRAM架構之概要範例,該DRAM架構包括埋藏字元線(bWL)11在矽基板9中。bWL係形成在蝕刻在矽基板9中之溝渠中。做為溝渠之襯墊的是保形阻障層12及絕緣層13,絕緣層13係配置在保形阻障層12與矽基板9之間。在圖1之範例中,絕緣層13可為閘極氧化物層,由高介電常數介電材料(例如矽氧化物或矽氮化物材料)所形成。
在本文所揭露的某些實施例中,保形阻障層12是含鎢層。在習知的鎢(W)字元線架構中,使用鈦氮化物(TiN)做為阻障物。然而,TiN/W字元線填充受到電阻率大小之限制;因為TiN具有相當高的電阻率,當尺寸減少且TiN保形層佔據溝渠之較大體積分率時,則電阻增加。根據各種實施例,本文所揭露的鎢bWL是無TiN及其它非W阻障層。
保形阻障層12可包括硼、矽及鍺其中一或多者。在某些實施例中,保形阻障層12是二元化合物,例如WBx、WSix及WGex,其中x是大於零之數字。在某些實施例中,保形阻障層12可包括碳或氮。在某些實施例中,保形阻障層12可包括硼、矽及鍺其中一或多者、及碳及氮其中一或兩者。在某些實施例中,保形阻障層12是三元化合物,例如WBxNy、WSixNy、WGexNy、WSixCy、WBxCy、WGexCy、等,其中x及y是大於零之數字。包括Si、B、Ge、N及C之四元及更多元化合物亦可被使用,範例包括WBxGeyNz、WGexCyNz、等,其中x、y及z是大於零之數字。
圖2A描繪在3D NAND結構23中之字元線21之概要範例。在圖2B中,顯示在鎢填充後之部分製造的3D NAND結構之3D特徵部之2D寫實圖,包 括字元線21及保形阻障層22。圖2B為已填充區域之剖面繪圖,具有如圖中所示之柱狀收縮部24,代表在俯視圖中可見、而非橫剖面圖中可見之收縮部。保形阻障層22可為如上所述之含鎢層(如圖1中之保形阻障層12)。含鎢膜可做為阻障層及成核層以用於隨後的CVD W沉積。
在某些實施例中,提出用於金屬閘極之含鎢功函數層,包括用於3D記憶體結構(例如上述之3D NAND結構)之金屬閘極之功函數層。
圖2C顯示VNAND結構32之概要範例,該VNAND結構32包括形成在基板30上之金屬閘極31,亦顯示金屬閘極31及相關膜堆疊之範例之放大圖。VNAND結構32包括半導體通道33、穿隧介電層35、電荷儲存層37、功函數層39、阻擋介電質41、及金屬閘極31。
在記憶體結構(包括圖2A-2C之範例中所示之結構)中之功函數層之範例包括二元含鎢化合物之膜,例如WBx、WSix及WGex,其中x是大於零之數字。在某些實施例中,功函數層可包括碳或氮。在某些實施例中,功函數層可包括硼、矽及鍺其中一或多者、及碳及氮其中一或兩者。在某些實施例中,功函數層是三元化合物,例如WBxNy、WSixNy、WGexNy、WSixCy、WBxCy、WGexCy、等。包括Si、B、Ge、N及C之四元及更多元化合物亦可被使用。含鎢膜可做為功函數層及成核層以用於隨後的CVD W沉積。功函數層可沉積在介電材料(例如閘極氧化物)上。
在某些實施例中,參考圖2A-2C而加以說明之記憶體結構不包括TiN擴散阻障物或TiN功函數層。
圖3A顯示可用於形成含鎢二元或三元膜之方法之範例。首先,使基板暴露至還原劑脈衝(302)。在某些實施例中,該基板可為部分製造的記憶體元件。在某些實施例中,暴露於還原劑脈衝而形成膜於其上之表面是介電 質。根據各種實施例,該膜可形成在其它類型的表面(包括導電及半導電表面)上。
使用在方塊302中之還原劑將還原在後續操作中使用之含鎢前驅物並且提供待併入所產生膜之中之化合物。這類還原劑之範例包括含硼、含矽及含鍺還原劑。含硼還原劑之範例包括硼烷,例如BnHn+4、BnHn+6、BnHn+8、BnHm,其中n是1至10之整數,m是與n不同之整數。在特定的實施例中,可使用二硼烷。亦可使用其它含硼化合物,例如,烷基硼烷、烷基硼、胺基硼烷(CH3)2NB(CH2)2、及碳硼烷,例如C2BnHn+2。含矽化合物之範例包括矽烷,例如SiH4及Si2H6。含鍺化合物之範例包括鍺烷,例如GenHn+4、GenHn+6、GenHn+8及GenHm,其中n是1至10之整數,且n是與m不同之整數。亦可使用其它含鍺化合物,例如,烷基鍺烷、烷基鍺、胺基鍺烷及碳鍺烷。
根據各種實施例,方塊302可能涉及一薄層的熱分解元素硼、矽或鍺之吸附至基板表面上。在某些實施例中,方塊302可能涉及前驅物分子之吸附至基板表面上。
其次,基板所在之腔室可選擇性地被吹淨(304)。可利用吹淨脈衝或抽真空以移除任何副產物(若存在的話)及未吸附的前驅物。接著是鎢氯化物前驅物之脈衝(306)。鎢氯化物前驅物包括WCl2、WCl4、WCl5及WCl6、及其混合物。在某些實施例中,鎢氯化物前驅物是六氯化鎢(WCl6),五氯化鎢(WCl5)或其混合物。在方塊306之後,亦可實施選擇性的吹淨(307)。鎢前驅物被還原劑(或其分解或反應產物)所還原以形成多成分膜。
沉積循環通常會沉積一部分的含鎢層。在某些實行例中,在方塊307之後,沉積循環可能完成,所沉積的膜是含鎢二元膜,例如WBx、WSix及WGex,其中x是大於零。在這樣的實施例中,處理可進行至方塊312以重複方塊302-307之循環直到沉積至想要的厚度。示例的成長速率可為約每循環100Å。
在某些實施例中,處理將進行選擇性地引入第三反應物(308)。第三反應物通常包括待引入膜中之元素,例如碳或氮。含氮反應物之範例包括N2、NH3及N2H4。含碳反應物之範例包括CH4及C2H2。隨後可進行選擇性的吹淨(309)。接著,處理可進行至方塊312以重複沉積循環。
包括氮或碳之三元膜之範例提供如上。在某些實施例中,膜可包括氮及碳兩者(例如WSiCN)。
根據各種實施例,多成分鎢膜可具有下列的原子百分比:W約5%至90%,B/Ge/Si約5%至60%,C/N約5%至80%。在某些實施例中,多成分膜具有下列的原子百分比:W約15%至約80%,B/Ge/Si約15%至約50%,C/N約20%至約50%。根據各種實施例,多成分鎢膜為至少50%鎢。
根據各種實施例,沉積溫度是相當高,例如在400℃及650℃之間,包括在450℃及600℃之間,在某些實施例中大於約500℃。此有助於鎢氯化物之還原並且亦使B、Si或Ge能夠併入二元膜中。該範圍之下端通常受限於鎢氯化物化合物能夠以合理的反應速率被還原之溫度,該溫度通常高於鎢氟化物還原。該範圍之上端可能受限於熱預算考量。在某些實施例中,方塊302、306及308其中任何一或多者可在不同於其它方塊其中任一者之溫度加以實施。美國專利申請案第14/703,732號(其合併於此做為參考)描述一處理範例,其中實施還原劑脈衝之溫度係低於隨後的鎢氯化物脈衝。類似的溫度控制可使用在圖3A之實施例中。在某些實施例中,從方塊302轉變至方塊306以及從方塊306轉變至方塊308涉及在多站腔室中將基板從一沉積站移動至另一者。此外,方塊302、方塊306、方塊308每一者可在相同多站腔室之不同站中加以實施。
在某些實施例中,可藉由引入氮或碳而調整二元或三元膜之電性,例如功函數。類似地,可調整還原劑之量(藉由調整用量及/或脈衝時間)以調整併入膜中之B、Si或Ge之量。此外,方塊302、306及308其中任何一或兩者 在每循環可實施超過一次,以調整二元或三元膜之鎢與其它成分之相對量及其物理、電及化學特性。美國專利公開案第20140027664號(其合併於此做為參考)描述用於形成三元WBN膜之不同循環之範例。在某些實施例中,所沉積的含鎢膜具有約4.5-4.8eV之有效功函數。
圖3B顯示可用於填充特徵部之方法之範例。首先,沉積含鎢多成分層(352)。多成分層可包括W、B、Si及Ge其中一或多者、及選擇性的C及N其中一或多者。範例包括WBx、WSix、WGex、WBxNy、WSixNy、WGexNy、WSixCy、WBxCy、WGexCy,其中x及y是大於零。可以關於圖3A之以上敘述以沉積該膜。
其次,含鎢多成分層可暴露至鎢氯化物前驅物以藉由CVD而沉積W金屬。對照於方塊352,CVD沉積的W通常是純鎢,亦即只有微量的雜質。在某些實施例中,該膜為至少95% W。在方塊352中沉積的層可做為在方塊354中之CVD W沉積用之成核層。方塊354可填充在基板上之特徵部,包括垂直特徵部(例如鎢介層窗及bWL)及水平特徵部(例如VNAND字元線)。如上所述,關於圖3A及3B所實施之方法通常不包括含氟前驅物。
在CVD反應中示例的基板溫度為如450℃一般低且可為如650℃一般高。在某些實施例中,鎢氯化物前驅物是WCl5或WCl6。在某些實施例中,還原劑是氫氣,但可使用其它還原劑,包括矽烷、硼烷及鍺烷。在某些實施例中,可以不同的階段實施CVD,例如低溫階段及高溫階段。在某些實施例中,CVD操作可發生在多個階段中,其中反應物之連續及同時流動之多個時期被一或更多反應物流動被轉向之時期所分隔開。
在方塊352及354中可使用惰性載氣以運送反應物流其中一或多者,其可能或可能不是預先混合的。在各種實施例中,使用氬做為載氣以引入前驅物。可使用其它適合的載氣。可提供惰性氣體(例如氬)或另一氣體(例 如氮)或其組合做為背景氣體,同時具有還原劑或WCl5或WCl6氣體。在某些實施例中,背景氣體流是連續的,亦即其在整個方塊352及354中不被開啟及關閉。
不像PNL或ALD處理,方塊354通常可涉及連續地引入反應物直到沉積想要的量。在某些實施例中,CVD操作可發生在多個階段中,其中反應物之連續及同時流動之多個時期被一或更多反應物流動被轉向之時期所分隔開。流動亦可脈衝式輸送於介於約1秒與約2秒之間之脈衝時間內。在某些實施例中,反應物是連續流動於介於約400秒與約600秒之間之時間內。在CVD沉積期間內腔室壓力之示例範圍可從約10Torr至約500Torr、或約40Torr。
在某些實施例中,從方塊352至方塊354之轉變涉及在多站腔室中將基板從一沉積站移動至另一者。
設備
可使用任何適當的腔室以實施所揭露的實施例。示例的沉積設備包括各種系統,例如由Lam Research Corp.,of Fremont California發售之ALTUS®及ALTUS® Max、或各種其它商業上可獲得的處理系統之任何一者。處理可以在多沉積站上平行實施。
在某些實施例中,鎢成核處理是在第一站實施,該第一站是設置在單一沉積腔室中之二、五、或甚至更多沉積站其中一者。在某些實施例中,成核處理之不同步驟是在沉積腔室之二不同站加以實施。例如,基板可在第一站中暴露至二硼烷(B2H6),該第一站使用個別的氣體供應系統,該個別的氣體供應系統在基板表面產生局部氛圍,接著可將基板傳送至第二站以暴露至前驅物(例如六氯化鎢WCl6)以沉積成核層。在某些實施例中,接著可將基板傳送回第一站以用於第二次暴露至二硼烷或傳送至第三站以用於第三反應物暴 露。接著,可將基板傳送至第二站以用於暴露至WCl6(或其它鎢氯化物)以完成鎢成核以及在相同或不同站中繼續進行主體鎢沉積。接著可使用一或更多站以實施化學氣相沉積(CVD),如上所述。
圖4為根據本發明之實施例之適用於實施鎢沉積處理之處理系統之方塊圖。系統400包括傳送模組403。傳送模組403提供一乾淨、加壓的環境以當處理中基板在不同反應器模組之間移動時使它們的污染之風險最小化。安裝在傳送模組403上的是多站反應器409,多站反應器409能實施根據本發明實施例之CVD沉積以及成核層沉積(其可被稱為脈衝式成核層(PNL)沉積)。腔室409可包括可依序執行這些操作之多個站411、413、415及417。例如:腔室409可配置成使得站411及413執行PNL沉積,而站413及415執行CVD。每個沉積站可包括經加熱的晶圓支座及噴淋頭、分散板或其它氣體入口。
亦安裝在傳送模組403上的可為一或更多單一或多重站的模組407,其可執行電漿或化學(非電漿)預清潔。該模組亦可用於各種其它處理,例如:還原劑浸泡。系統400亦包括一或更多(在此例子中是兩個)晶圓來源模組401,其在處理之前和之後儲存晶圓。在常壓傳送腔室419中的常壓機械臂(atmospheric robot)(未顯示)首先將晶圓從來源模組401移動至負載鎖室(loadlock)421。在傳送模組403中之晶圓傳送裝置(通常為機械臂單元)從負載鎖室421將晶圓移動至安裝在傳送模組403上之複數模組及移動在該複數模組之間。
在某些實施例中,系統控制器429在沉積期間用於控制處理條件。控制器通常包括一或更多記憶裝置及一或更多處理器。處理器可包括CPU或電腦、類比及/或數位輸入/輸出連接、步進馬達控制器板等。
控制器可控制沉積設備的所有活動。系統控制器執行系統控制軟體,該系統控制軟體包括用於控制下述的指令集:時序、氣體混合、腔室壓力、 腔室溫度、晶圓溫度、射頻(RF)功率位準(若使用)、晶圓卡盤或支座位置、及特定處理之其它參數。儲存於記憶裝置與控制器有關的其它電腦程式可使用在某些實施例中。
通常,具有與控制器有關的使用者介面。該使用者介面可包括顯示螢幕、設備及/或處理條件的圖形軟體顯示器、及使用者輸入裝置,例如指向裝置、鍵盤、觸控螢幕、麥克風等。
系統控制邏輯可以任何適合的方式加以配置。通常,邏輯可被設計或配置在硬體及/或軟體中。控制驅動電路的指令可為硬編碼或被提供作為軟體。該等指令可由「程式設計」提供。這類的程式設計被理解為包括任何形式的邏輯,包括在數位訊號處理器、特殊應用積體電路、及具有實現為硬體之特定演算法之其它裝置。程式設計亦被理解為包括可在通用處理器上執行之軟體或韌體指令。系統控制軟體可以任何適合的電腦可讀程式設計語言加以編碼。或者,控制邏輯可硬編碼在控制器中。特殊應用積體電路、可程式邏輯裝置(例如:現場可程式閘陣列(field-programmable gate array)或FPGA)等可用於這些目的。在以下的討論中,無論「軟體」或「編碼」於何處使用,功能上相當的硬編碼邏輯可在這些地方使用。
用於控制在處理序列中之沉積及其它處理之電腦程式碼可以任何習知的電腦可讀程式設計語言撰寫:例如,組合語言、C、C++、巴斯卡(Pascal)、福傳(Fortran)、或其它。編譯的目的碼或腳本係由處理器實行以執行在程式中所確定的任務。
控制器參數涉及處理條件,例如:處理氣體成分及流率、溫度、壓力、電漿條件(例如RF功率位準及低頻RF頻率)、冷卻氣體壓力、及腔室壁溫度。這些參數係以配方的形式提供給使用者,並且可利用使用者介面加以輸入。
可藉由系統控制器之類比及/或數位輸入連接以提供用於監控處理之訊號。用於控制處理之訊號係輸出在沉積設備之類比及數位輸出連接上。
系統軟體可以許多不同的方式設計或配置。例如:各種腔室元件副程式(subroutine)或控制物件可被撰寫,以控制執行本發明之沉積處理所需的腔室元件之操作。為了此目的之程式或程式部分之範例包含基板定位碼、處理氣體控制碼、壓力控制碼、加熱器控制碼、及電漿控制碼。
基板定位程式可包括用以控制腔室元件之程式碼,用以裝載基板至支座或卡盤之上、以及用以控制在基板與腔室其它部分(例如氣體入口及/或目標物)之間之間距。處理氣體控制程式可包括程式碼,用於控制氣體成分及流率,及選擇性地用於在沉積之前使氣體流入腔室中以穩定腔室中之壓力。壓力控制程式可包括程式碼,用於藉由調節,例如,腔室排氣系統中之節流閥以控制腔室中之壓力。加熱器控制程式可包括控制電流至用以加熱基板之加熱單元的碼。或者,該加熱器控制程式可控制加熱轉移氣體(例如氦氣)之遞送至晶圓卡盤。
於沉積期間可被監控之腔室感測器的例子包括:質量流量控制器、壓力感測器(例如壓力計)、及位於支座或卡盤中之熱電偶。適當編程的反饋及控制演算法可與來自這些感測器的資料一起使用以維持想要的處理條件。以上描述在單一或多腔室半導體處理工具內所揭露實施例的實施方式。
以上描述在單一或多腔室半導體處理工具內所揭露實施例的實施方式。在此描述之設備及處理可結合微影圖案化的工具或處理而使用,例如,半導體元件、顯示器、LED、太陽光電板等之製造或生產。通常,雖然不一定,這樣的工具/處理將一起使用或執行於共同的製造設施內。膜之微影圖案化通常包含一些或全部下述步驟,每個步驟以幾個可能的工具提供:(1)工件(亦即基板)上光阻之塗佈,使用旋轉式或噴塗式之工具;(2)光阻之固化,使 用加熱板或加熱爐或UV固化工具;(3)以工具(例如晶圓步進機)使光阻暴露於可見光或UV或x射線光;(4)使光阻顯影以便使用工具(例如溼式清洗台)選擇性地移除光阻及從而使其圖案化;(5)藉由使用乾式或電漿輔助蝕刻工具轉移光阻圖案至下方膜或工件中;及(6)使用工具(例如RF或微波電漿光阻剝除器)移除光阻。
結論
雖然上述實施例為了清楚理解之目的已經利用一些細節加以描述,但顯然地,某些改變和修飾可在隨附申請專利範圍之範疇中實施。應注意,有許多執行本發明實施例之處理、系統及設備之替代方式。因此,應將本發明實施例視為說明性的而非限制性的,且該等實施例不受限於本文所提出之細節。
302‧‧‧方塊
304‧‧‧方塊
306‧‧‧方塊
307‧‧‧方塊
308‧‧‧方塊
309‧‧‧方塊
312‧‧‧方塊

Claims (26)

  1. 一種在基板上沉積鎢的方法,該方法包括:脈衝式輸送還原劑,其中該還原劑係含硼(B)的、含矽(Si)的或含鍺(Ge)的;及脈衝式輸送鎢氯化物前驅物,其中藉由該還原劑或其產物將該鎢氯化物前驅物還原,以形成多成分含鎢膜在該基板上,該多成分含鎢膜包括B、Si及Ge其中一或多者,其中該多成分含鎢膜包括介於5%與60%原子百分比之間的B、Si、或Ge。
  2. 如申請專利範圍第1項之在基板上沉積鎢的方法,更包括:脈衝式輸送第三反應物,以形成三元含鎢膜。
  3. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中該多成分含鎢膜係二元膜。
  4. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中該多成分含鎢膜係用於字元線之擴散阻障物。
  5. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中該多成分含鎢膜係用於金屬閘極之功函數層。
  6. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中在該鎢氯化物脈衝期間之基板溫度係至少400℃。
  7. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中在該鎢氯化物脈衝期間之基板溫度係至少450℃。
  8. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中在該鎢氯化物脈衝期間之基板溫度係至少500℃。
  9. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中在該等還原劑及鎢氯化物脈衝期間之基板溫度係至少400℃。
  10. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中在該等還原劑及鎢氯化物脈衝期間之基板溫度係至少450℃。
  11. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中在該等還原劑及鎢氯化物脈衝期間之基板溫度係至少500℃。
  12. 如申請專利範圍第1項之在基板上沉積鎢的方法,更包括:沉積主體鎢(W)層在該多成分含鎢膜上。
  13. 如申請專利範圍第12項之在基板上沉積鎢的方法,其中藉由在鎢氯化物前驅物與還原劑之間之化學氣相沉積(CVD)反應以沉積該主體W層。
  14. 如申請專利範圍第12項之在基板上沉積鎢的方法,其中該主體W層係直接沉積在該多成分含鎢膜上而沒有中介層。
  15. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中該多成分含鎢膜係直接沉積在絕緣膜上。
  16. 如申請專利範圍第15項之在基板上沉積鎢的方法,其中該絕緣膜係氧化物或氮化物膜。
  17. 如申請專利範圍第1項之在基板上沉積鎢的方法,該方法更包括該還原劑之分解,以形成一層B、Si或Ge在該基板上。
  18. 如申請專利範圍第1項之在基板上沉積鎢的方法,其中該多成分含鎢膜係選自於由WGex、WGexNy、WGexCy、WBxGeyNz、以及WGexCyNz所組成之群組,其中x、y、以及z為大於零之數字。
  19. 一種記憶體結構,包括:多成分含鎢膜之襯墊層,該多成分含鎢膜包括B、Si及Ge其中一或多者,其中該多成分含鎢膜包括介於5%與60%原子百分比之間的B、Si、或Ge;及 鎢字元線。
  20. 一種記憶體結構,包括:多成分含鎢膜之功函數層,該多成分含鎢膜包括B、Si及Ge其中一或多者,其中該多成分含鎢膜包括介於5%與60%原子百分比之間的B、Si、或Ge;及金屬閘極。
  21. 一種在基板上沉積多成分含鎢擴散阻障層的方法,該方法包括:沉積多成分含鎢擴散阻障層在基板的介電表面上,其中沉積該多成分含鎢擴散阻障層包括使該基板暴露至還原劑與鎢氯化物的交替脈衝,其中該還原劑係選自於含硼還原劑、含矽還原劑、以及含鍺還原劑,其中該多成分含鎢擴散阻障層包括介於5%與60%原子百分比之間的B、Si、或Ge;及沉積主體鎢層在該多成分含鎢擴散阻障層上。
  22. 如申請專利範圍第21項之在基板上沉積多成分含鎢擴散阻障層的方法,其中該多成分含鎢擴散阻障層係三元或四元含鎢膜。
  23. 如申請專利範圍第22項之在基板上沉積多成分含鎢擴散阻障層的方法,更包括:脈衝式輸送第三反應物,以形成該多成分含鎢擴散阻障層。
  24. 如申請專利範圍第23項之在基板上沉積多成分含鎢擴散阻障層的方法,其中該第三反應物係含氮反應物,以及該多成分含鎢擴散阻障層包括由該含氮反應物所提供的氮。
  25. 如申請專利範圍第23項之在基板上沉積多成分含鎢擴散阻障層的方法,其中該第三反應物係含碳反應物,以及該多成分含鎢擴散阻障層包括由該含碳反應物所提供的碳。
  26. 如申請專利範圍第21項之在基板上沉積多成分含鎢擴散阻障層的方法,其中該多成分含鎢擴散阻障層係選自於由四元含矽化合物與WSixNy及WSixCy所組成之群組,其中x以及y為大於零之數字。
TW105104238A 2015-02-11 2016-02-15 字元線應用所使用的鎢 TWI704251B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201562115012P 2015-02-11 2015-02-11
US62/115,012 2015-02-11

Publications (2)

Publication Number Publication Date
TW201700773A TW201700773A (zh) 2017-01-01
TWI704251B true TWI704251B (zh) 2020-09-11

Family

ID=56566178

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105104238A TWI704251B (zh) 2015-02-11 2016-02-15 字元線應用所使用的鎢

Country Status (4)

Country Link
US (2) US9953984B2 (zh)
KR (2) KR20160098986A (zh)
CN (1) CN105870119B (zh)
TW (1) TWI704251B (zh)

Families Citing this family (32)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
KR102131581B1 (ko) 2012-03-27 2020-07-08 노벨러스 시스템즈, 인코포레이티드 텅스텐 피처 충진
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
JP6710089B2 (ja) * 2016-04-04 2020-06-17 東京エレクトロン株式会社 タングステン膜の成膜方法
US10573522B2 (en) 2016-08-16 2020-02-25 Lam Research Corporation Method for preventing line bending during metal fill process
US10269569B2 (en) 2016-11-29 2019-04-23 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and methods of manufacture
KR20180063947A (ko) * 2016-12-02 2018-06-14 삼성전자주식회사 반도체 메모리 소자
JP7214656B2 (ja) * 2017-01-25 2023-01-30 ユミコア・アクチエンゲゼルシャフト・ウント・コムパニー・コマンディットゲゼルシャフト 金属ハロゲン化物の還元方法
US10283404B2 (en) 2017-03-30 2019-05-07 Lam Research Corporation Selective deposition of WCN barrier/adhesion layer for interconnect
KR20230127377A (ko) * 2017-04-10 2023-08-31 램 리써치 코포레이션 몰리브덴을 함유하는 저 저항률 막들
US10460987B2 (en) * 2017-05-09 2019-10-29 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated antenna and manufacturing method thereof
CN108962891B (zh) 2017-05-18 2019-11-19 联华电子股份有限公司 用以避免列锤击问题的半导体结构及其制作方法
CN108962892B (zh) * 2017-05-26 2021-02-26 联华电子股份有限公司 半导体元件及其制作方法
US10199267B2 (en) * 2017-06-30 2019-02-05 Lam Research Corporation Tungsten nitride barrier layer deposition
KR20200140391A (ko) 2018-05-03 2020-12-15 램 리써치 코포레이션 3d nand 구조체들에 텅스텐 및 다른 금속들을 증착하는 방법
JP2020047706A (ja) * 2018-09-18 2020-03-26 キオクシア株式会社 半導体装置およびその製造方法
JP2022509621A (ja) * 2018-11-19 2022-01-21 ラム リサーチ コーポレーション タングステン用モリブデンテンプレート
CN113424300A (zh) 2018-12-14 2021-09-21 朗姆研究公司 在3d nand结构上的原子层沉积
US10847367B2 (en) * 2018-12-28 2020-11-24 Micron Technology, Inc. Methods of forming tungsten structures
JP2022523689A (ja) 2019-01-28 2022-04-26 ラム リサーチ コーポレーション 金属膜の蒸着
KR20210127262A (ko) 2019-03-11 2021-10-21 램 리써치 코포레이션 몰리브덴-함유 막들의 증착을 위한 전구체들
US12002679B2 (en) 2019-04-11 2024-06-04 Lam Research Corporation High step coverage tungsten deposition
CN114269963A (zh) * 2019-08-12 2022-04-01 朗姆研究公司 钨沉积
US11244903B2 (en) * 2019-12-30 2022-02-08 Micron Technology, Inc. Tungsten structures and methods of forming the structures
JP2022045700A (ja) * 2020-09-09 2022-03-22 キオクシア株式会社 半導体装置およびその製造方法
TWI817445B (zh) * 2022-01-19 2023-10-01 南亞科技股份有限公司 導電特徵及半導體元件的製備方法
US11676861B1 (en) * 2022-01-19 2023-06-13 Nanya Technology Corporation Method for fabricating semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101154576A (zh) * 2006-09-29 2008-04-02 海力士半导体有限公司 形成具有低电阻的钨多金属栅极的方法
US20080124926A1 (en) * 2001-05-22 2008-05-29 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
CN104272441A (zh) * 2012-03-27 2015-01-07 诺发系统公司 钨特征填充

Family Cites Families (263)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI117944B (fi) 1999-10-15 2007-04-30 Asm Int Menetelmä siirtymämetallinitridiohutkalvojen kasvattamiseksi
JPS5629648A (en) 1979-08-16 1981-03-25 Toshiba Tungaloy Co Ltd High hardness sintered body
JPS61224313A (ja) 1985-03-29 1986-10-06 Hitachi Ltd 気相薄膜成長方法
JPS62216224A (ja) 1986-03-17 1987-09-22 Fujitsu Ltd タングステンの選択成長方法
JPS62260340A (ja) 1986-05-06 1987-11-12 Toshiba Corp 半導体装置の製造方法
US4746375A (en) 1987-05-08 1988-05-24 General Electric Company Activation of refractory metal surfaces for electroless plating
US4962063A (en) 1988-11-10 1990-10-09 Applied Materials, Inc. Multistep planarized chemical vapor deposition process with the use of low melting inorganic material for flowing while depositing
JPH02187031A (ja) 1989-01-14 1990-07-23 Sharp Corp 半導体装置
US5250329A (en) 1989-04-06 1993-10-05 Microelectronics And Computer Technology Corporation Method of depositing conductive lines on a dielectric
GB8907898D0 (en) 1989-04-07 1989-05-24 Inmos Ltd Semiconductor devices and fabrication thereof
US5028565A (en) 1989-08-25 1991-07-02 Applied Materials, Inc. Process for CVD deposition of tungsten layer on semiconductor wafer
EP1069610A2 (en) 1990-01-08 2001-01-17 Lsi Logic Corporation Refractory metal deposition process for low contact resistivity to silicon and corresponding apparatus
KR100209856B1 (ko) 1990-08-31 1999-07-15 가나이 쓰도무 반도체장치의 제조방법
JPH04142061A (ja) 1990-10-02 1992-05-15 Sony Corp タングステンプラグの形成方法
US5250467A (en) 1991-03-29 1993-10-05 Applied Materials, Inc. Method for forming low resistance and low defect density tungsten contacts to silicon semiconductor wafer
US5308655A (en) 1991-08-16 1994-05-03 Materials Research Corporation Processing for forming low resistivity titanium nitride films
US5567583A (en) 1991-12-16 1996-10-22 Biotronics Corporation Methods for reducing non-specific priming in DNA detection
JPH05226280A (ja) 1992-02-14 1993-09-03 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
US5370739A (en) 1992-06-15 1994-12-06 Materials Research Corporation Rotating susceptor semiconductor wafer processing cluster tool module useful for tungsten CVD
US5326723A (en) 1992-09-09 1994-07-05 Intel Corporation Method for improving stability of tungsten chemical vapor deposition
KR950012738B1 (ko) 1992-12-10 1995-10-20 현대전자산업주식회사 반도체소자의 텅스텐 콘택 플러그 제조방법
JP3014019B2 (ja) 1993-11-26 2000-02-28 日本電気株式会社 半導体装置の製造方法
KR970009867B1 (ko) 1993-12-17 1997-06-18 현대전자산업 주식회사 반도체 소자의 텅스텐 실리사이드 형성방법
JP3291889B2 (ja) 1994-02-15 2002-06-17 ソニー株式会社 ドライエッチング方法
DE69518710T2 (de) 1994-09-27 2001-05-23 Applied Materials Inc Verfahren zum Behandeln eines Substrats in einer Vakuumbehandlungskammer
JPH08115984A (ja) 1994-10-17 1996-05-07 Hitachi Ltd 半導体装置及びその製造方法
US6001729A (en) 1995-01-10 1999-12-14 Kawasaki Steel Corporation Method of forming wiring structure for semiconductor device
JP2737764B2 (ja) 1995-03-03 1998-04-08 日本電気株式会社 半導体装置及びその製造方法
JPH0922896A (ja) 1995-07-07 1997-01-21 Toshiba Corp 金属膜の選択的形成方法
JPH0927596A (ja) 1995-07-11 1997-01-28 Sanyo Electric Co Ltd 半導体装置の製造方法
US5863819A (en) 1995-10-25 1999-01-26 Micron Technology, Inc. Method of fabricating a DRAM access transistor with dual gate oxide technique
TW310461B (zh) 1995-11-10 1997-07-11 Matsushita Electric Ind Co Ltd
US6017818A (en) 1996-01-22 2000-01-25 Texas Instruments Incorporated Process for fabricating conformal Ti-Si-N and Ti-B-N based barrier films with low defect density
US5833817A (en) 1996-04-22 1998-11-10 Taiwan Semiconductor Manufacturing Company, Ltd. Method for improving conformity and contact bottom coverage of sputtered titanium nitride barrier layers
US5633200A (en) 1996-05-24 1997-05-27 Micron Technology, Inc. Process for manufacturing a large grain tungsten nitride film and process for manufacturing a lightly nitrided titanium salicide diffusion barrier with a large grain tungsten nitride cover layer
US5963833A (en) 1996-07-03 1999-10-05 Micron Technology, Inc. Method for cleaning semiconductor wafers and
US5916365A (en) 1996-08-16 1999-06-29 Sherman; Arthur Sequential chemical vapor deposition
TW314654B (en) * 1996-09-07 1997-09-01 United Microelectronics Corp Manufacturing method of conductive plug
US5916634A (en) 1996-10-01 1999-06-29 Sandia Corporation Chemical vapor deposition of W-Si-N and W-B-N
KR100214852B1 (ko) 1996-11-02 1999-08-02 김영환 반도체 디바이스의 금속 배선 형성 방법
US6310300B1 (en) 1996-11-08 2001-10-30 International Business Machines Corporation Fluorine-free barrier layer between conductor and insulator for degradation prevention
CN1115723C (zh) 1996-11-15 2003-07-23 三星电子株式会社 氮化钨层制造方法及使用同样原理的金属连线制造方法
KR100255516B1 (ko) 1996-11-28 2000-05-01 김영환 반도체 장치의 금속배선 및 그 형성방법
US6297152B1 (en) 1996-12-12 2001-10-02 Applied Materials, Inc. CVD process for DCS-based tungsten silicide
JP3090074B2 (ja) 1997-01-20 2000-09-18 日本電気株式会社 半導体装置及びその製造方法
US5804249A (en) 1997-02-07 1998-09-08 Lsi Logic Corporation Multistep tungsten CVD process with amorphization step
US6156382A (en) 1997-05-16 2000-12-05 Applied Materials, Inc. Chemical vapor deposition process for depositing tungsten
US6037248A (en) 1997-06-13 2000-03-14 Micron Technology, Inc. Method of fabricating integrated circuit wiring with low RC time delay
US6162715A (en) 1997-06-30 2000-12-19 Applied Materials, Inc. Method of forming gate electrode connection structure by in situ chemical vapor deposition of tungsten and tungsten nitride
US6287965B1 (en) 1997-07-28 2001-09-11 Samsung Electronics Co, Ltd. Method of forming metal layer using atomic layer deposition and semiconductor device having the metal layer as barrier metal layer or upper or lower electrode of capacitor
US5956609A (en) 1997-08-11 1999-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Method for reducing stress and improving step-coverage of tungsten interconnects and plugs
US5795824A (en) 1997-08-28 1998-08-18 Novellus Systems, Inc. Method for nucleation of CVD tungsten films
US5913145A (en) 1997-08-28 1999-06-15 Texas Instruments Incorporated Method for fabricating thermally stable contacts with a diffusion barrier formed at high temperatures
US5926720A (en) 1997-09-08 1999-07-20 Lsi Logic Corporation Consistent alignment mark profiles on semiconductor wafers using PVD shadowing
US6861356B2 (en) 1997-11-05 2005-03-01 Tokyo Electron Limited Method of forming a barrier film and method of forming wiring structure and electrodes of semiconductor device having a barrier film
US7829144B2 (en) 1997-11-05 2010-11-09 Tokyo Electron Limited Method of forming a metal film for electrode
US6099904A (en) 1997-12-02 2000-08-08 Applied Materials, Inc. Low resistivity W using B2 H6 nucleation step
KR100272523B1 (ko) 1998-01-26 2000-12-01 김영환 반도체소자의배선형성방법
US6284316B1 (en) 1998-02-25 2001-09-04 Micron Technology, Inc. Chemical vapor deposition of titanium
JPH11260759A (ja) 1998-03-12 1999-09-24 Fujitsu Ltd 半導体装置の製造方法
US6452276B1 (en) 1998-04-30 2002-09-17 International Business Machines Corporation Ultra thin, single phase, diffusion barrier for metal conductors
US6066366A (en) 1998-07-22 2000-05-23 Applied Materials, Inc. Method for depositing uniform tungsten layers by CVD
US6143082A (en) 1998-10-08 2000-11-07 Novellus Systems, Inc. Isolation of incompatible processes in a multi-station processing chamber
KR100273767B1 (ko) 1998-10-28 2001-01-15 윤종용 반도체소자의 텅스텐막 제조방법 및 그에 따라 제조되는 반도체소자
US6037263A (en) 1998-11-05 2000-03-14 Vanguard International Semiconductor Corporation Plasma enhanced CVD deposition of tungsten and tungsten compounds
US6331483B1 (en) 1998-12-18 2001-12-18 Tokyo Electron Limited Method of film-forming of tungsten
KR100296126B1 (ko) 1998-12-22 2001-08-07 박종섭 고집적 메모리 소자의 게이트전극 형성방법
US20010014533A1 (en) 1999-01-08 2001-08-16 Shih-Wei Sun Method of fabricating salicide
JP3206578B2 (ja) 1999-01-11 2001-09-10 日本電気株式会社 多層配線構造をもつ半導体装置の製造方法
JP4570704B2 (ja) 1999-02-17 2010-10-27 株式会社アルバック バリア膜製造方法
US6306211B1 (en) 1999-03-23 2001-10-23 Matsushita Electric Industrial Co., Ltd. Method for growing semiconductor film and method for fabricating semiconductor device
TW452607B (en) 1999-03-26 2001-09-01 Nat Science Council Production of a refractory metal by chemical vapor deposition of a bilayer-stacked tungsten metal
US6245654B1 (en) 1999-03-31 2001-06-12 Taiwan Semiconductor Manufacturing Company, Ltd Method for preventing tungsten contact/via plug loss after a backside pressure fault
US6294468B1 (en) 1999-05-24 2001-09-25 Agere Systems Guardian Corp. Method of chemical vapor depositing tungsten films
US6720261B1 (en) 1999-06-02 2004-04-13 Agere Systems Inc. Method and system for eliminating extrusions in semiconductor vias
US6174812B1 (en) 1999-06-08 2001-01-16 United Microelectronics Corp. Copper damascene technology for ultra large scale integration circuits
US6355558B1 (en) 1999-06-10 2002-03-12 Texas Instruments Incorporated Metallization structure, and associated method, to improve crystallographic texture and cavity fill for CVD aluminum/PVD aluminum alloy films
US6309964B1 (en) 1999-07-08 2001-10-30 Taiwan Semiconductor Manufacturing Company Method for forming a copper damascene structure over tungsten plugs with improved adhesion, oxidation resistance, and diffusion barrier properties using nitridation of the tungsten plug
US6265312B1 (en) 1999-08-02 2001-07-24 Stmicroelectronics, Inc. Method for depositing an integrated circuit tungsten film stack that includes a post-nucleation pump down step
US6391785B1 (en) 1999-08-24 2002-05-21 Interuniversitair Microelektronica Centrum (Imec) Method for bottomless deposition of barrier layers in integrated circuit metallization schemes
US6358788B1 (en) * 1999-08-30 2002-03-19 Micron Technology, Inc. Method of fabricating a wordline in a memory array of a semiconductor device
US6309966B1 (en) 1999-09-03 2001-10-30 Motorola, Inc. Apparatus and method of a low pressure, two-step nucleation tungsten deposition
US6303480B1 (en) 1999-09-13 2001-10-16 Applied Materials, Inc. Silicon layer to improve plug filling by CVD
US6924226B2 (en) 1999-10-02 2005-08-02 Uri Cohen Methods for making multiple seed layers for metallic interconnects
US6610151B1 (en) 1999-10-02 2003-08-26 Uri Cohen Seed layers for interconnects and methods and apparatus for their fabrication
US6902763B1 (en) 1999-10-15 2005-06-07 Asm International N.V. Method for depositing nanolaminate thin films on sensitive surfaces
KR100330163B1 (ko) 2000-01-06 2002-03-28 윤종용 반도체 장치의 텅스텐 콘택 플러그 형성 방법
US6277744B1 (en) 2000-01-21 2001-08-21 Advanced Micro Devices, Inc. Two-level silane nucleation for blanket tungsten deposition
US6777331B2 (en) 2000-03-07 2004-08-17 Simplus Systems Corporation Multilayered copper structure for improving adhesion property
US6429126B1 (en) 2000-03-29 2002-08-06 Applied Materials, Inc. Reduced fluorine contamination for tungsten CVD
JP5184731B2 (ja) 2000-05-18 2013-04-17 コーニング インコーポレイテッド 固体酸化物燃料電池用可撓性電極/電解質構造体、燃料電池装置、およびその作成方法
JP3651360B2 (ja) 2000-05-19 2005-05-25 株式会社村田製作所 電極膜の形成方法
US7253076B1 (en) 2000-06-08 2007-08-07 Micron Technologies, Inc. Methods for forming and integrated circuit structures containing ruthenium and tungsten containing layers
JP2002016066A (ja) 2000-06-27 2002-01-18 Mitsubishi Electric Corp 半導体装置およびその製造方法
US6620723B1 (en) 2000-06-27 2003-09-16 Applied Materials, Inc. Formation of boride barrier layers using chemisorption techniques
US6936538B2 (en) 2001-07-16 2005-08-30 Applied Materials, Inc. Method and apparatus for depositing tungsten after surface treatment to improve film characteristics
US7101795B1 (en) 2000-06-28 2006-09-05 Applied Materials, Inc. Method and apparatus for depositing refractory metal layers employing sequential deposition techniques to form a nucleation layer
US7732327B2 (en) 2000-06-28 2010-06-08 Applied Materials, Inc. Vapor deposition of tungsten materials
US6551929B1 (en) 2000-06-28 2003-04-22 Applied Materials, Inc. Bifurcated deposition process for depositing refractory metal layers employing atomic layer deposition and chemical vapor deposition techniques
US7405158B2 (en) 2000-06-28 2008-07-29 Applied Materials, Inc. Methods for depositing tungsten layers employing atomic layer deposition techniques
US7964505B2 (en) 2005-01-19 2011-06-21 Applied Materials, Inc. Atomic layer deposition of tungsten materials
US6491978B1 (en) 2000-07-10 2002-12-10 Applied Materials, Inc. Deposition of CVD layers for copper metallization using novel metal organic chemical vapor deposition (MOCVD) precursors
US6218301B1 (en) 2000-07-31 2001-04-17 Applied Materials, Inc. Deposition of tungsten films from W(CO)6
US20030190424A1 (en) 2000-10-20 2003-10-09 Ofer Sneh Process for tungsten silicide atomic layer deposition
US6740591B1 (en) 2000-11-16 2004-05-25 Intel Corporation Slurry and method for chemical mechanical polishing of copper
JP2004514289A (ja) 2000-11-17 2004-05-13 東京エレクトロン株式会社 金属配線の形成方法および金属配線形成用半導体製造装置
US6908848B2 (en) 2000-12-20 2005-06-21 Samsung Electronics, Co., Ltd. Method for forming an electrical interconnection providing improved surface morphology of tungsten
KR100375230B1 (ko) 2000-12-20 2003-03-08 삼성전자주식회사 매끄러운 텅스텐 표면을 갖는 반도체 장치의 배선 제조방법
KR100399417B1 (ko) 2001-01-08 2003-09-26 삼성전자주식회사 반도체 집적 회로의 제조 방법
US20020117399A1 (en) 2001-02-23 2002-08-29 Applied Materials, Inc. Atomically thin highly resistive barrier layer in a copper via
KR20020072996A (ko) 2001-03-14 2002-09-19 주성엔지니어링(주) 금속 플러그 형성방법
US20020190379A1 (en) 2001-03-28 2002-12-19 Applied Materials, Inc. W-CVD with fluorine-free tungsten nucleation
US20020168840A1 (en) 2001-05-11 2002-11-14 Applied Materials, Inc. Deposition of tungsten silicide films
US7262125B2 (en) * 2001-05-22 2007-08-28 Novellus Systems, Inc. Method of forming low-resistivity tungsten interconnects
US7955972B2 (en) 2001-05-22 2011-06-07 Novellus Systems, Inc. Methods for growing low-resistivity tungsten for high aspect ratio and small features
US7141494B2 (en) 2001-05-22 2006-11-28 Novellus Systems, Inc. Method for reducing tungsten film roughness and improving step coverage
US9076843B2 (en) 2001-05-22 2015-07-07 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US6635965B1 (en) 2001-05-22 2003-10-21 Novellus Systems, Inc. Method for producing ultra-thin tungsten layers with improved step coverage
US7005372B2 (en) 2003-01-21 2006-02-28 Novellus Systems, Inc. Deposition of tungsten nitride
US6686278B2 (en) 2001-06-19 2004-02-03 United Microelectronics Corp. Method for forming a plug metal layer
US7211144B2 (en) 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
JP2005518088A (ja) 2001-07-16 2005-06-16 アプライド マテリアルズ インコーポレイテッド タングステン複合膜の形成
US20030029715A1 (en) 2001-07-25 2003-02-13 Applied Materials, Inc. An Apparatus For Annealing Substrates In Physical Vapor Deposition Systems
WO2003030224A2 (en) 2001-07-25 2003-04-10 Applied Materials, Inc. Barrier formation using novel sputter-deposition method
JP4032872B2 (ja) 2001-08-14 2008-01-16 東京エレクトロン株式会社 タングステン膜の形成方法
JP4595989B2 (ja) 2001-08-24 2010-12-08 東京エレクトロン株式会社 成膜方法
US6607976B2 (en) 2001-09-25 2003-08-19 Applied Materials, Inc. Copper interconnect barrier layer structure and formation method
TW589684B (en) 2001-10-10 2004-06-01 Applied Materials Inc Method for depositing refractory metal layers employing sequential deposition techniques
JP2003142484A (ja) 2001-10-31 2003-05-16 Mitsubishi Electric Corp 半導体装置の製造方法
US6566262B1 (en) 2001-11-01 2003-05-20 Lsi Logic Corporation Method for creating self-aligned alloy capping layers for copper interconnect structures
TWI253478B (en) 2001-11-14 2006-04-21 Mitsubishi Heavy Ind Ltd Barrier metal film production apparatus, barrier metal film production method, metal film production method, and metal film production apparatus
US20030091870A1 (en) 2001-11-15 2003-05-15 Siddhartha Bhowmik Method of forming a liner for tungsten plugs
US20030123216A1 (en) 2001-12-27 2003-07-03 Yoon Hyungsuk A. Deposition of tungsten for the formation of conformal tungsten silicide
US6998014B2 (en) 2002-01-26 2006-02-14 Applied Materials, Inc. Apparatus and method for plasma assisted deposition
US6833161B2 (en) 2002-02-26 2004-12-21 Applied Materials, Inc. Cyclical deposition of tungsten nitride for metal oxide gate electrode
US6566250B1 (en) 2002-03-18 2003-05-20 Taiwant Semiconductor Manufacturing Co., Ltd Method for forming a self aligned capping layer
US6797620B2 (en) 2002-04-16 2004-09-28 Applied Materials, Inc. Method and apparatus for improved electroplating fill of an aperture
KR100446300B1 (ko) 2002-05-30 2004-08-30 삼성전자주식회사 반도체 소자의 금속 배선 형성 방법
US20030224217A1 (en) 2002-05-31 2003-12-04 Applied Materials, Inc. Metal nitride formation
US6905543B1 (en) 2002-06-19 2005-06-14 Novellus Systems, Inc Methods of forming tungsten nucleation layer
US20040020278A1 (en) * 2002-07-31 2004-02-05 Mcgarvey Gordon Bryce Erosion monitoring of ceramic insulation or shield with wide area electrical grids
TWI287559B (en) 2002-08-22 2007-10-01 Konica Corp Organic-inorganic hybrid film, its manufacturing method, optical film, and polarizing film
US6706625B1 (en) 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6962873B1 (en) 2002-12-10 2005-11-08 Novellus Systems, Inc. Nitridation of electrolessly deposited cobalt
KR20050110613A (ko) 2002-12-23 2005-11-23 어플라이드 씬 필름스 인코포레이티드 알루미늄 포스페이트 코팅
WO2004061154A1 (ja) 2002-12-27 2004-07-22 Ulvac Inc. 窒化タングステン膜の成膜方法
JP2004235456A (ja) 2003-01-30 2004-08-19 Seiko Epson Corp 成膜装置、成膜方法および半導体装置の製造方法
US7713592B2 (en) 2003-02-04 2010-05-11 Tegal Corporation Nanolayer deposition process
JP3956049B2 (ja) 2003-03-07 2007-08-08 東京エレクトロン株式会社 タングステン膜の形成方法
US6844258B1 (en) 2003-05-09 2005-01-18 Novellus Systems, Inc. Selective refractory metal and nitride capping
US7211508B2 (en) 2003-06-18 2007-05-01 Applied Materials, Inc. Atomic layer deposition of tantalum based barrier materials
JP2005029821A (ja) 2003-07-09 2005-02-03 Tokyo Electron Ltd 成膜方法
US7754604B2 (en) 2003-08-26 2010-07-13 Novellus Systems, Inc. Reducing silicon attack and improving resistivity of tungsten nitride film
JP4606006B2 (ja) 2003-09-11 2011-01-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6924223B2 (en) 2003-09-30 2005-08-02 Tokyo Electron Limited Method of forming a metal layer using an intermittent precursor gas flow process
US7078341B2 (en) 2003-09-30 2006-07-18 Tokyo Electron Limited Method of depositing metal layers from metal-carbonyl precursors
KR100557626B1 (ko) 2003-12-23 2006-03-10 주식회사 하이닉스반도체 반도체 소자의 비트라인 형성 방법
US20050139838A1 (en) 2003-12-26 2005-06-30 Matsushita Electric Industrial Co., Ltd. Semiconductor device and method for manufacturing semiconductor device
KR101108304B1 (ko) 2004-02-26 2012-01-25 노벨러스 시스템즈, 인코포레이티드 질화 텅스텐의 증착
CN100370585C (zh) 2004-04-12 2008-02-20 株式会社爱发科 隔离膜的形成方法及电极膜的形成方法
WO2005104165A1 (en) 2004-04-21 2005-11-03 Philips Intellectual Property & Standards Gmbh Method for the thermal treatment of tungsten electrodes free from thorium oxide for high-pressure discharge lamps
US7605469B2 (en) 2004-06-30 2009-10-20 Intel Corporation Atomic layer deposited tantalum containing adhesion layer
US7429402B2 (en) 2004-12-10 2008-09-30 Applied Materials, Inc. Ruthenium as an underlayer for tungsten film deposition
US20060145190A1 (en) 2004-12-31 2006-07-06 Salzman David B Surface passivation for III-V compound semiconductors
KR100642750B1 (ko) 2005-01-31 2006-11-10 삼성전자주식회사 반도체 소자 및 그 제조 방법
US7344983B2 (en) 2005-03-18 2008-03-18 International Business Machines Corporation Clustered surface preparation for silicide and metal contacts
US7220671B2 (en) 2005-03-31 2007-05-22 Intel Corporation Organometallic precursors for the chemical phase deposition of metal films in interconnect applications
JP4738178B2 (ja) 2005-06-17 2011-08-03 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4945937B2 (ja) 2005-07-01 2012-06-06 東京エレクトロン株式会社 タングステン膜の形成方法、成膜装置及び記憶媒体
JP4864368B2 (ja) 2005-07-21 2012-02-01 シャープ株式会社 気相堆積方法
US7517798B2 (en) 2005-09-01 2009-04-14 Micron Technology, Inc. Methods for forming through-wafer interconnects and structures resulting therefrom
US7235485B2 (en) 2005-10-14 2007-06-26 Samsung Electronics Co., Ltd. Method of manufacturing semiconductor device
US8993055B2 (en) 2005-10-27 2015-03-31 Asm International N.V. Enhanced thin film deposition
US7524765B2 (en) 2005-11-02 2009-04-28 Intel Corporation Direct tailoring of the composition and density of ALD films
US7276796B1 (en) 2006-03-15 2007-10-02 International Business Machines Corporation Formation of oxidation-resistant seed layer for interconnect applications
JP2007250907A (ja) 2006-03-16 2007-09-27 Renesas Technology Corp 半導体装置およびその製造方法
US8258057B2 (en) 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
TW200746268A (en) 2006-04-11 2007-12-16 Applied Materials Inc Process for forming cobalt-containing materials
US7828504B2 (en) 2006-05-12 2010-11-09 Axcellis Technologies, Inc. Combination load lock for handling workpieces
US7557047B2 (en) 2006-06-09 2009-07-07 Micron Technology, Inc. Method of forming a layer of material using an atomic layer deposition process
KR100884339B1 (ko) 2006-06-29 2009-02-18 주식회사 하이닉스반도체 반도체 소자의 텅스텐막 형성방법 및 이를 이용한 텅스텐배선층 형성방법
KR100705936B1 (ko) 2006-06-30 2007-04-13 주식회사 하이닉스반도체 반도체 소자의 비트라인 형성방법
US7355254B2 (en) 2006-06-30 2008-04-08 Intel Corporation Pinning layer for low resistivity N-type source drain ohmic contacts
US8153831B2 (en) 2006-09-28 2012-04-10 Praxair Technology, Inc. Organometallic compounds, processes for the preparation thereof and methods of use thereof
KR100894769B1 (ko) 2006-09-29 2009-04-24 주식회사 하이닉스반도체 반도체 소자의 금속 배선 형성방법
KR20080036679A (ko) 2006-10-24 2008-04-29 삼성전자주식회사 불 휘발성 메모리 소자의 형성 방법
US7675119B2 (en) 2006-12-25 2010-03-09 Elpida Memory, Inc. Semiconductor device and manufacturing method thereof
US20080254619A1 (en) 2007-04-14 2008-10-16 Tsang-Jung Lin Method of fabricating a semiconductor device
CN101308794B (zh) 2007-05-15 2010-09-15 应用材料股份有限公司 钨材料的原子层沉积
JP2008288289A (ja) 2007-05-16 2008-11-27 Oki Electric Ind Co Ltd 電界効果トランジスタとその製造方法
US7655567B1 (en) 2007-07-24 2010-02-02 Novellus Systems, Inc. Methods for improving uniformity and resistivity of thin tungsten films
KR101225642B1 (ko) 2007-11-15 2013-01-24 삼성전자주식회사 H2 원격 플라즈마 처리를 이용한 반도체 소자의 콘택플러그 형성방법
CN102969240B (zh) 2007-11-21 2016-11-09 朗姆研究公司 控制对含钨层的蚀刻微负载的方法
US8609546B2 (en) 2007-11-29 2013-12-17 Lam Research Corporation Pulsed bias plasma process to control microloading
US8080324B2 (en) 2007-12-03 2011-12-20 Kobe Steel, Ltd. Hard coating excellent in sliding property and method for forming same
US7772114B2 (en) 2007-12-05 2010-08-10 Novellus Systems, Inc. Method for improving uniformity and adhesion of low resistivity tungsten film
US8053365B2 (en) 2007-12-21 2011-11-08 Novellus Systems, Inc. Methods for forming all tungsten contacts and lines
US8062977B1 (en) 2008-01-31 2011-11-22 Novellus Systems, Inc. Ternary tungsten-containing resistive thin films
KR101163825B1 (ko) 2008-03-28 2012-07-09 도쿄엘렉트론가부시키가이샤 정전척 및 그 제조 방법
US8058170B2 (en) 2008-06-12 2011-11-15 Novellus Systems, Inc. Method for depositing thin tungsten film with low resistivity and robust micro-adhesion characteristics
US8385644B2 (en) 2008-07-08 2013-02-26 Zeitera, Llc Digital video fingerprinting based on resultant weighted gradient orientation computation
US7968460B2 (en) 2008-06-19 2011-06-28 Micron Technology, Inc. Semiconductor with through-substrate interconnect
US8551885B2 (en) 2008-08-29 2013-10-08 Novellus Systems, Inc. Method for reducing tungsten roughness and improving reflectivity
US20100062149A1 (en) 2008-09-08 2010-03-11 Applied Materials, Inc. Method for tuning a deposition rate during an atomic layer deposition process
US20100072623A1 (en) 2008-09-19 2010-03-25 Advanced Micro Devices, Inc. Semiconductor device with improved contact plugs, and related fabrication methods
JP2010093116A (ja) 2008-10-09 2010-04-22 Panasonic Corp 半導体装置及び半導体装置の製造方法
US20100120245A1 (en) * 2008-11-07 2010-05-13 Agus Sofian Tjandra Plasma and thermal anneal treatment to improve oxidation resistance of metal-containing films
US7825024B2 (en) 2008-11-25 2010-11-02 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming through-silicon vias
US7964502B2 (en) 2008-11-25 2011-06-21 Freescale Semiconductor, Inc. Multilayered through via
US8129270B1 (en) 2008-12-10 2012-03-06 Novellus Systems, Inc. Method for depositing tungsten film having low resistivity, low roughness and high reflectivity
US20100144140A1 (en) 2008-12-10 2010-06-10 Novellus Systems, Inc. Methods for depositing tungsten films having low resistivity for gapfill applications
US8110877B2 (en) 2008-12-19 2012-02-07 Intel Corporation Metal-insulator-semiconductor tunneling contacts having an insulative layer disposed between source/drain contacts and source/drain regions
US8071478B2 (en) 2008-12-31 2011-12-06 Applied Materials, Inc. Method of depositing tungsten film with reduced resistivity and improved surface morphology
KR101559425B1 (ko) 2009-01-16 2015-10-13 삼성전자주식회사 반도체 소자의 제조 방법
JP5550843B2 (ja) 2009-03-19 2014-07-16 ラピスセミコンダクタ株式会社 半導体装置の製造方法
DE102009015747B4 (de) 2009-03-31 2013-08-08 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Verfahren zur Herstellung von Transistoren mit Metallgateelektrodenstrukturen und Gatedielektrikum mit großem ε und einer Zwischenätzstoppschicht
US8623733B2 (en) 2009-04-16 2014-01-07 Novellus Systems, Inc. Methods for depositing ultra thin low resistivity tungsten film for small critical dimension contacts and interconnects
US9159571B2 (en) 2009-04-16 2015-10-13 Lam Research Corporation Tungsten deposition process using germanium-containing reducing agent
US8039394B2 (en) 2009-06-26 2011-10-18 Seagate Technology Llc Methods of forming layers of alpha-tantalum
US9034768B2 (en) 2010-07-09 2015-05-19 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8124531B2 (en) 2009-08-04 2012-02-28 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US8119527B1 (en) 2009-08-04 2012-02-21 Novellus Systems, Inc. Depositing tungsten into high aspect ratio features
US10256142B2 (en) 2009-08-04 2019-04-09 Novellus Systems, Inc. Tungsten feature fill with nucleation inhibition
US8207062B2 (en) 2009-09-09 2012-06-26 Novellus Systems, Inc. Method for improving adhesion of low resistivity tungsten/tungsten nitride layers
SG10201407519TA (en) 2009-11-19 2015-01-29 Univ Singapore Method For Producing T Cell Receptor-Like Monoclonal Antibodies And Uses Thereof
DE102009055392B4 (de) 2009-12-30 2014-05-22 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Halbleiterbauelement und Verfahren zur Herstellung des Halbleiterbauelements
US8709948B2 (en) 2010-03-12 2014-04-29 Novellus Systems, Inc. Tungsten barrier and seed for copper filled TSV
US9129945B2 (en) 2010-03-24 2015-09-08 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8741394B2 (en) 2010-03-25 2014-06-03 Novellus Systems, Inc. In-situ deposition of film stacks
US20120003833A1 (en) 2010-07-01 2012-01-05 Applied Materials, Inc. Methods for forming tungsten-containing layers
US8778797B2 (en) 2010-09-27 2014-07-15 Novellus Systems, Inc. Systems and methods for selective tungsten deposition in vias
US20120199887A1 (en) 2011-02-03 2012-08-09 Lana Chan Methods of controlling tungsten film properties
US20120225191A1 (en) 2011-03-01 2012-09-06 Applied Materials, Inc. Apparatus and Process for Atomic Layer Deposition
US8865594B2 (en) 2011-03-10 2014-10-21 Applied Materials, Inc. Formation of liner and barrier for tungsten as gate electrode and as contact plug to reduce resistance and enhance device performance
US8546250B2 (en) 2011-08-18 2013-10-01 Wafertech Llc Method of fabricating vertical integrated semiconductor device with multiple continuous single crystal silicon layers vertically separated from one another
US8916435B2 (en) 2011-09-09 2014-12-23 International Business Machines Corporation Self-aligned bottom plate for metal high-K dielectric metal insulator metal (MIM) embedded dynamic random access memory
WO2013063260A1 (en) 2011-10-28 2013-05-02 Applied Materials, Inc. High temperature tungsten metallization process
SG11201403033YA (en) 2011-12-12 2014-09-26 Novellus Systems Inc Monitoring leveler concentrations in electroplating solutions
CN104272440B (zh) * 2012-03-27 2017-02-22 诺发系统公司 用核化抑制的钨特征填充
US9034760B2 (en) 2012-06-29 2015-05-19 Novellus Systems, Inc. Methods of forming tensile tungsten films and compressive tungsten films
US9969622B2 (en) 2012-07-26 2018-05-15 Lam Research Corporation Ternary tungsten boride nitride films and methods for forming same
US8975184B2 (en) 2012-07-27 2015-03-10 Novellus Systems, Inc. Methods of improving tungsten contact resistance in small critical dimension features
KR101990051B1 (ko) 2012-08-31 2019-10-01 에스케이하이닉스 주식회사 무불소텅스텐 배리어층을 구비한 반도체장치 및 그 제조 방법
KR20140028992A (ko) 2012-08-31 2014-03-10 에스케이하이닉스 주식회사 텅스텐 게이트전극을 구비한 반도체장치 및 그 제조 방법
US8853080B2 (en) 2012-09-09 2014-10-07 Novellus Systems, Inc. Method for depositing tungsten film with low roughness and low resistivity
US9637395B2 (en) 2012-09-28 2017-05-02 Entegris, Inc. Fluorine free tungsten ALD/CVD process
US9169556B2 (en) 2012-10-11 2015-10-27 Applied Materials, Inc. Tungsten growth modulation by controlling surface composition
US9230815B2 (en) 2012-10-26 2016-01-05 Appled Materials, Inc. Methods for depositing fluorine/carbon-free conformal tungsten
US9153486B2 (en) 2013-04-12 2015-10-06 Lam Research Corporation CVD based metal/semiconductor OHMIC contact for high volume manufacturing applications
US8975142B2 (en) 2013-04-25 2015-03-10 Globalfoundries Inc. FinFET channel stress using tungsten contacts in raised epitaxial source and drain
US9362163B2 (en) 2013-07-30 2016-06-07 Lam Research Corporation Methods and apparatuses for atomic layer cleaning of contacts and vias
US9748105B2 (en) 2013-08-16 2017-08-29 Applied Materials, Inc. Tungsten deposition with tungsten hexafluoride (WF6) etchback
JP6594304B2 (ja) 2013-10-18 2019-10-23 ブルックス オートメーション インコーポレイテッド 処理装置
US9589808B2 (en) 2013-12-19 2017-03-07 Lam Research Corporation Method for depositing extremely low resistivity tungsten
JP6297884B2 (ja) 2014-03-28 2018-03-20 東京エレクトロン株式会社 タングステン膜の成膜方法
US9595470B2 (en) 2014-05-09 2017-03-14 Lam Research Corporation Methods of preparing tungsten and tungsten nitride thin films using tungsten chloride precursor
US20150348840A1 (en) 2014-05-31 2015-12-03 Lam Research Corporation Methods of filling high aspect ratio features with fluorine free tungsten
US9953984B2 (en) 2015-02-11 2018-04-24 Lam Research Corporation Tungsten for wordline applications
TW201700761A (zh) 2015-05-13 2017-01-01 應用材料股份有限公司 經由基材的有機金屬或矽烷預處理而改良的鎢膜
US9754824B2 (en) 2015-05-27 2017-09-05 Lam Research Corporation Tungsten films having low fluorine content
US9978605B2 (en) 2015-05-27 2018-05-22 Lam Research Corporation Method of forming low resistivity fluorine free tungsten film without nucleation
US9613818B2 (en) 2015-05-27 2017-04-04 Lam Research Corporation Deposition of low fluorine tungsten by sequential CVD process
US9978610B2 (en) 2015-08-21 2018-05-22 Lam Research Corporation Pulsing RF power in etch process to enhance tungsten gapfill performance

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080124926A1 (en) * 2001-05-22 2008-05-29 Novellus Systems, Inc. Methods for growing low-resistivity tungsten film
CN101154576A (zh) * 2006-09-29 2008-04-02 海力士半导体有限公司 形成具有低电阻的钨多金属栅极的方法
CN104272441A (zh) * 2012-03-27 2015-01-07 诺发系统公司 钨特征填充

Also Published As

Publication number Publication date
US10529722B2 (en) 2020-01-07
KR20240005648A (ko) 2024-01-12
TW201700773A (zh) 2017-01-01
US9953984B2 (en) 2018-04-24
US20160233220A1 (en) 2016-08-11
KR20160098986A (ko) 2016-08-19
US20180219014A1 (en) 2018-08-02
CN105870119A (zh) 2016-08-17
CN105870119B (zh) 2019-07-19

Similar Documents

Publication Publication Date Title
TWI704251B (zh) 字元線應用所使用的鎢
KR102466639B1 (ko) 몰리브덴을 함유하는 저 저항률 막들
US20230290680A1 (en) Self-limiting growth
KR102515236B1 (ko) 저 저항 텅스텐 피처 충진을 가능하게 하는 텅스텐 핵생성 프로세스
US9613818B2 (en) Deposition of low fluorine tungsten by sequential CVD process
US10546751B2 (en) Forming low resistivity fluorine free tungsten film without nucleation
US9159571B2 (en) Tungsten deposition process using germanium-containing reducing agent
KR20210027507A (ko) 순수 금속 막의 증착
KR102397797B1 (ko) 순차적인 cvd 프로세스에 의한 저 불소 텅스텐의 증착
JP2023113892A (ja) 3d nand及び他の用途のためのモリブデン充填
KR20210092840A (ko) 3d nand 구조체 상의 원자 층 증착
KR20210110886A (ko) 금속 막들의 증착
US20220254685A1 (en) Nucleation-free tungsten deposition
TW202237880A (zh) 低電阻脈衝cvd鎢